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ARM: dts: Move .dts files to vendor sub-directories
[thirdparty/linux.git] / arch / arm / boot / dts / st / stm32mp131.dtsi
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1da8779c
AT		 1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
f95634be
GF		 7#include <dt-bindings/clock/stm32mp13-clks.h>
8#include <dt-bindings/reset/stm32mp13-resets.h>
1da8779c
AT		 9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
23 };
24
25 arm-pmu {
26 compatible = "arm,cortex-a7-pmu";
27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
28 interrupt-affinity = <&cpu0>;
29 interrupt-parent = <&intc>;
30 };
31
63058bfb
GF		 32 firmware {
33 optee {
34 method = "smc";
35 compatible = "linaro,optee-tz";
36 };
37
38 scmi: scmi {
39 compatible = "linaro,scmi-optee";
40 #address-cells = <1>;
41 #size-cells = <0>;
42 linaro,optee-channel-id = <0>;
43 shmem = <&scmi_shm>;
44
45 scmi_clk: protocol@14 {
46 reg = <0x14>;
47 #clock-cells = <1>;
48 };
49
50 scmi_reset: protocol@16 {
51 reg = <0x16>;
52 #reset-cells = <1>;
53 };
54 };
55 };
56
1da8779c
AT		 57 intc: interrupt-controller@a0021000 {
58 compatible = "arm,cortex-a7-gic";
59 #interrupt-cells = <3>;
60 interrupt-controller;
61 reg = <0xa0021000 0x1000>,
62 <0xa0022000 0x2000>;
63 };
64
65 psci {
66 compatible = "arm,psci-1.0";
67 method = "smc";
68 };
69
70 timer {
71 compatible = "arm,armv7-timer";
bf5f07e7
AT		 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1da8779c
AT		 76 interrupt-parent = <&intc>;
77 always-on;
78 };
79
acdce5cd
FG		 80 /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */
81 reg11: reg11 {
82 compatible = "regulator-fixed";
83 regulator-name = "reg11";
84 regulator-min-microvolt = <1100000>;
85 regulator-max-microvolt = <1100000>;
86 };
87
88 reg18: reg18 {
89 compatible = "regulator-fixed";
90 regulator-name = "reg18";
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <1800000>;
93 };
94
95 usb33: usb33 {
96 compatible = "regulator-fixed";
97 regulator-name = "usb33";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 };
101
1da8779c
AT		 102 soc {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 interrupt-parent = <&intc>;
107 ranges;
108
63058bfb
GF		 109 scmi_sram: sram@2ffff000 {
110 compatible = "mmio-sram";
111 reg = <0x2ffff000 0x1000>;
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0x2ffff000 0x1000>;
115
116 scmi_shm: scmi-sram@0 {
117 compatible = "arm,scmi-shmem";
118 reg = <0 0x80>;
119 };
120 };
121
bf9d876b
OM		 122 timers2: timer@40000000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
126 reg = <0x40000000 0x400>;
127 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-names = "global";
129 clocks = <&rcc TIM2_K>;
130 clock-names = "int";
131 dmas = <&dmamux1 18 0x400 0x1>,
132 <&dmamux1 19 0x400 0x1>,
133 <&dmamux1 20 0x400 0x1>,
134 <&dmamux1 21 0x400 0x1>,
135 <&dmamux1 22 0x400 0x1>;
136 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
137 status = "disabled";
138
139 pwm {
140 compatible = "st,stm32-pwm";
141 #pwm-cells = <3>;
142 status = "disabled";
143 };
144
145 timer@1 {
146 compatible = "st,stm32h7-timer-trigger";
147 reg = <1>;
148 status = "disabled";
149 };
150
151 counter {
152 compatible = "st,stm32-timer-counter";
153 status = "disabled";
154 };
155 };
156
157 timers3: timer@40001000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "st,stm32-timers";
161 reg = <0x40001000 0x400>;
162 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-names = "global";
164 clocks = <&rcc TIM3_K>;
165 clock-names = "int";
166 dmas = <&dmamux1 23 0x400 0x1>,
167 <&dmamux1 24 0x400 0x1>,
168 <&dmamux1 25 0x400 0x1>,
169 <&dmamux1 26 0x400 0x1>,
170 <&dmamux1 27 0x400 0x1>,
171 <&dmamux1 28 0x400 0x1>;
172 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
173 status = "disabled";
174
175 pwm {
176 compatible = "st,stm32-pwm";
177 #pwm-cells = <3>;
178 status = "disabled";
179 };
180
181 timer@2 {
182 compatible = "st,stm32h7-timer-trigger";
183 reg = <2>;
184 status = "disabled";
185 };
186
187 counter {
188 compatible = "st,stm32-timer-counter";
189 status = "disabled";
190 };
191 };
192
193 timers4: timer@40002000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "st,stm32-timers";
197 reg = <0x40002000 0x400>;
198 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
199 interrupt-names = "global";
200 clocks = <&rcc TIM4_K>;
201 clock-names = "int";
202 dmas = <&dmamux1 29 0x400 0x1>,
203 <&dmamux1 30 0x400 0x1>,
204 <&dmamux1 31 0x400 0x1>,
205 <&dmamux1 32 0x400 0x1>;
206 dma-names = "ch1", "ch2", "ch3", "up";
207 status = "disabled";
208
209 pwm {
210 compatible = "st,stm32-pwm";
211 #pwm-cells = <3>;
212 status = "disabled";
213 };
214
215 timer@3 {
216 compatible = "st,stm32h7-timer-trigger";
217 reg = <3>;
218 status = "disabled";
219 };
220
221 counter {
222 compatible = "st,stm32-timer-counter";
223 status = "disabled";
224 };
225 };
226
227 timers5: timer@40003000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "st,stm32-timers";
231 reg = <0x40003000 0x400>;
232 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
233 interrupt-names = "global";
234 clocks = <&rcc TIM5_K>;
235 clock-names = "int";
236 dmas = <&dmamux1 55 0x400 0x1>,
237 <&dmamux1 56 0x400 0x1>,
238 <&dmamux1 57 0x400 0x1>,
239 <&dmamux1 58 0x400 0x1>,
240 <&dmamux1 59 0x400 0x1>,
241 <&dmamux1 60 0x400 0x1>;
242 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
243 status = "disabled";
244
245 pwm {
246 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
248 status = "disabled";
249 };
250
251 timer@4 {
252 compatible = "st,stm32h7-timer-trigger";
253 reg = <4>;
254 status = "disabled";
255 };
256
257 counter {
258 compatible = "st,stm32-timer-counter";
259 status = "disabled";
260 };
261 };
262
263 timers6: timer@40004000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "st,stm32-timers";
267 reg = <0x40004000 0x400>;
268 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-names = "global";
270 clocks = <&rcc TIM6_K>;
271 clock-names = "int";
272 dmas = <&dmamux1 69 0x400 0x1>;
273 dma-names = "up";
274 status = "disabled";
275
276 timer@5 {
277 compatible = "st,stm32h7-timer-trigger";
278 reg = <5>;
279 status = "disabled";
280 };
281 };
282
283 timers7: timer@40005000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "st,stm32-timers";
287 reg = <0x40005000 0x400>;
288 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-names = "global";
290 clocks = <&rcc TIM7_K>;
291 clock-names = "int";
292 dmas = <&dmamux1 70 0x400 0x1>;
293 dma-names = "up";
294 status = "disabled";
295
296 timer@6 {
297 compatible = "st,stm32h7-timer-trigger";
298 reg = <6>;
299 status = "disabled";
300 };
301 };
302
303 lptimer1: timer@40009000 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 compatible = "st,stm32-lptimer";
307 reg = <0x40009000 0x400>;
308 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&rcc LPTIM1_K>;
310 clock-names = "mux";
311 wakeup-source;
312 status = "disabled";
313
314 pwm {
315 compatible = "st,stm32-pwm-lp";
316 #pwm-cells = <3>;
317 status = "disabled";
318 };
319
320 trigger@0 {
321 compatible = "st,stm32-lptimer-trigger";
322 reg = <0>;
323 status = "disabled";
324 };
325
326 counter {
327 compatible = "st,stm32-lptimer-counter";
328 status = "disabled";
329 };
330
331 timer {
332 compatible = "st,stm32-lptimer-timer";
333 status = "disabled";
334 };
335 };
336
ae8cf3b4
OM		 337 i2s2: audio-controller@4000b000 {
338 compatible = "st,stm32h7-i2s";
339 reg = <0x4000b000 0x400>;
340 #sound-dai-cells = <0>;
341 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
342 dmas = <&dmamux1 39 0x400 0x01>,
343 <&dmamux1 40 0x400 0x01>;
344 dma-names = "rx", "tx";
345 status = "disabled";
346 };
347
8539ebb4
AV		 348 spi2: spi@4000b000 {
349 compatible = "st,stm32h7-spi";
350 reg = <0x4000b000 0x400>;
351 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&rcc SPI2_K>;
353 resets = <&rcc SPI2_R>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 dmas = <&dmamux1 39 0x400 0x01>,
357 <&dmamux1 40 0x400 0x01>;
358 dma-names = "rx", "tx";
359 status = "disabled";
360 };
361
ae8cf3b4
OM		 362 i2s3: audio-controller@4000c000 {
363 compatible = "st,stm32h7-i2s";
364 reg = <0x4000c000 0x400>;
365 #sound-dai-cells = <0>;
366 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
367 dmas = <&dmamux1 61 0x400 0x01>,
368 <&dmamux1 62 0x400 0x01>;
369 dma-names = "rx", "tx";
370 status = "disabled";
371 };
372
8539ebb4
AV		 373 spi3: spi@4000c000 {
374 compatible = "st,stm32h7-spi";
375 reg = <0x4000c000 0x400>;
376 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&rcc SPI3_K>;
378 resets = <&rcc SPI3_R>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 dmas = <&dmamux1 61 0x400 0x01>,
382 <&dmamux1 62 0x400 0x01>;
383 dma-names = "rx", "tx";
384 status = "disabled";
385 };
386
c5e05d08
OM		 387 spdifrx: audio-controller@4000d000 {
388 compatible = "st,stm32h7-spdifrx";
389 reg = <0x4000d000 0x400>;
390 #sound-dai-cells = <0>;
391 clocks = <&rcc SPDIF_K>;
392 clock-names = "kclk";
393 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&dmamux1 93 0x400 0x01>,
395 <&dmamux1 94 0x400 0x01>;
396 dma-names = "rx", "rx-ctrl";
397 status = "disabled";
398 };
399
c1689f85
VC		 400 usart3: serial@4000f000 {
401 compatible = "st,stm32h7-uart";
402 reg = <0x4000f000 0x400>;
403 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&rcc USART3_K>;
405 resets = <&rcc USART3_R>;
406 wakeup-source;
407 dmas = <&dmamux1 45 0x400 0x5>,
408 <&dmamux1 46 0x400 0x1>;
409 dma-names = "rx", "tx";
410 status = "disabled";
411 };
412
1da8779c
AT		 413 uart4: serial@40010000 {
414 compatible = "st,stm32h7-uart";
415 reg = <0x40010000 0x400>;
c1689f85 416 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
f95634be
GF		 417 clocks = <&rcc UART4_K>;
418 resets = <&rcc UART4_R>;
c1689f85
VC		 419 wakeup-source;
420 dmas = <&dmamux1 63 0x400 0x5>,
421 <&dmamux1 64 0x400 0x1>;
422 dma-names = "rx", "tx";
423 status = "disabled";
424 };
425
426 uart5: serial@40011000 {
427 compatible = "st,stm32h7-uart";
428 reg = <0x40011000 0x400>;
429 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&rcc UART5_K>;
431 resets = <&rcc UART5_R>;
432 wakeup-source;
433 dmas = <&dmamux1 65 0x400 0x5>,
434 <&dmamux1 66 0x400 0x1>;
435 dma-names = "rx", "tx";
1da8779c
AT		 436 status = "disabled";
437 };
438
446d5be8
AV		 439 i2c1: i2c@40012000 {
440 compatible = "st,stm32mp13-i2c";
441 reg = <0x40012000 0x400>;
442 interrupt-names = "event", "error";
443 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&rcc I2C1_K>;
446 resets = <&rcc I2C1_R>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 dmas = <&dmamux1 33 0x400 0x1>,
450 <&dmamux1 34 0x400 0x1>;
451 dma-names = "rx", "tx";
452 st,syscfg-fmp = <&syscfg 0x4 0x1>;
453 i2c-analog-filter;
454 status = "disabled";
455 };
456
457 i2c2: i2c@40013000 {
458 compatible = "st,stm32mp13-i2c";
459 reg = <0x40013000 0x400>;
460 interrupt-names = "event", "error";
461 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc I2C2_K>;
464 resets = <&rcc I2C2_R>;
465 #address-cells = <1>;
466 #size-cells = <0>;
467 dmas = <&dmamux1 35 0x400 0x1>,
468 <&dmamux1 36 0x400 0x1>;
469 dma-names = "rx", "tx";
470 st,syscfg-fmp = <&syscfg 0x4 0x2>;
471 i2c-analog-filter;
472 status = "disabled";
473 };
474
c1689f85
VC		 475 uart7: serial@40018000 {
476 compatible = "st,stm32h7-uart";
477 reg = <0x40018000 0x400>;
478 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&rcc UART7_K>;
480 resets = <&rcc UART7_R>;
481 wakeup-source;
482 dmas = <&dmamux1 79 0x400 0x5>,
483 <&dmamux1 80 0x400 0x1>;
484 dma-names = "rx", "tx";
485 status = "disabled";
486 };
487
488 uart8: serial@40019000 {
489 compatible = "st,stm32h7-uart";
490 reg = <0x40019000 0x400>;
491 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&rcc UART8_K>;
493 resets = <&rcc UART8_R>;
494 wakeup-source;
495 dmas = <&dmamux1 81 0x400 0x5>,
496 <&dmamux1 82 0x400 0x1>;
497 dma-names = "rx", "tx";
498 status = "disabled";
499 };
500
bf9d876b
OM		 501 timers1: timer@44000000 {
502 #address-cells = <1>;
503 #size-cells = <0>;
504 compatible = "st,stm32-timers";
505 reg = <0x44000000 0x400>;
506 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
510 interrupt-names = "brk", "up", "trg-com", "cc";
511 clocks = <&rcc TIM1_K>;
512 clock-names = "int";
513 dmas = <&dmamux1 11 0x400 0x1>,
514 <&dmamux1 12 0x400 0x1>,
515 <&dmamux1 13 0x400 0x1>,
516 <&dmamux1 14 0x400 0x1>,
517 <&dmamux1 15 0x400 0x1>,
518 <&dmamux1 16 0x400 0x1>,
519 <&dmamux1 17 0x400 0x1>;
520 dma-names = "ch1", "ch2", "ch3", "ch4",
521 "up", "trig", "com";
522 status = "disabled";
523
524 pwm {
525 compatible = "st,stm32-pwm";
526 #pwm-cells = <3>;
527 status = "disabled";
528 };
529
530 timer@0 {
531 compatible = "st,stm32h7-timer-trigger";
532 reg = <0>;
533 status = "disabled";
534 };
535
536 counter {
537 compatible = "st,stm32-timer-counter";
538 status = "disabled";
539 };
540 };
541
542 timers8: timer@44001000 {
543 #address-cells = <1>;
544 #size-cells = <0>;
545 compatible = "st,stm32-timers";
546 reg = <0x44001000 0x400>;
547 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-names = "brk", "up", "trg-com", "cc";
552 clocks = <&rcc TIM8_K>;
553 clock-names = "int";
554 dmas = <&dmamux1 47 0x400 0x1>,
555 <&dmamux1 48 0x400 0x1>,
556 <&dmamux1 49 0x400 0x1>,
557 <&dmamux1 50 0x400 0x1>,
558 <&dmamux1 51 0x400 0x1>,
559 <&dmamux1 52 0x400 0x1>,
560 <&dmamux1 53 0x400 0x1>;
561 dma-names = "ch1", "ch2", "ch3", "ch4",
562 "up", "trig", "com";
563 status = "disabled";
564
565 pwm {
566 compatible = "st,stm32-pwm";
567 #pwm-cells = <3>;
568 status = "disabled";
569 };
570
571 timer@7 {
572 compatible = "st,stm32h7-timer-trigger";
573 reg = <7>;
574 status = "disabled";
575 };
576
577 counter {
578 compatible = "st,stm32-timer-counter";
579 status = "disabled";
580 };
581 };
582
c1689f85
VC		 583 usart6: serial@44003000 {
584 compatible = "st,stm32h7-uart";
585 reg = <0x44003000 0x400>;
586 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&rcc USART6_K>;
588 resets = <&rcc USART6_R>;
589 wakeup-source;
590 dmas = <&dmamux1 71 0x400 0x5>,
591 <&dmamux1 72 0x400 0x1>;
592 dma-names = "rx", "tx";
593 status = "disabled";
594 };
595
ae8cf3b4
OM		 596 i2s1: audio-controller@44004000 {
597 compatible = "st,stm32h7-i2s";
598 reg = <0x44004000 0x400>;
599 #sound-dai-cells = <0>;
600 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
601 dmas = <&dmamux1 37 0x400 0x01>,
602 <&dmamux1 38 0x400 0x01>;
603 dma-names = "rx", "tx";
604 status = "disabled";
605 };
606
8539ebb4
AV		 607 spi1: spi@44004000 {
608 compatible = "st,stm32h7-spi";
609 reg = <0x44004000 0x400>;
610 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&rcc SPI1_K>;
612 resets = <&rcc SPI1_R>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615 dmas = <&dmamux1 37 0x400 0x01>,
616 <&dmamux1 38 0x400 0x01>;
617 dma-names = "rx", "tx";
618 status = "disabled";
619 };
620
619746a2
OM		 621 sai1: sai@4400a000 {
622 compatible = "st,stm32h7-sai";
623 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
624 ranges = <0 0x4400a000 0x400>;
625 #address-cells = <1>;
626 #size-cells = <1>;
627 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
628 resets = <&rcc SAI1_R>;
629 status = "disabled";
630
631 sai1a: audio-controller@4400a004 {
632 compatible = "st,stm32-sai-sub-a";
633 reg = <0x4 0x20>;
634 #sound-dai-cells = <0>;
635 clocks = <&rcc SAI1_K>;
636 clock-names = "sai_ck";
637 dmas = <&dmamux1 87 0x400 0x01>;
638 status = "disabled";
639 };
640
641 sai1b: audio-controller@4400a024 {
642 compatible = "st,stm32-sai-sub-b";
643 reg = <0x24 0x20>;
644 #sound-dai-cells = <0>;
645 clocks = <&rcc SAI1_K>;
646 clock-names = "sai_ck";
647 dmas = <&dmamux1 88 0x400 0x01>;
648 status = "disabled";
649 };
650 };
651
652 sai2: sai@4400b000 {
653 compatible = "st,stm32h7-sai";
654 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
655 ranges = <0 0x4400b000 0x400>;
656 #address-cells = <1>;
657 #size-cells = <1>;
658 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
659 resets = <&rcc SAI2_R>;
660 status = "disabled";
661
662 sai2a: audio-controller@4400b004 {
663 compatible = "st,stm32-sai-sub-a";
664 reg = <0x4 0x20>;
665 #sound-dai-cells = <0>;
666 clocks = <&rcc SAI2_K>;
667 clock-names = "sai_ck";
668 dmas = <&dmamux1 89 0x400 0x01>;
669 status = "disabled";
670 };
671
672 sai2b: audio-controller@4400b024 {
673 compatible = "st,stm32-sai-sub-b";
674 reg = <0x24 0x20>;
675 #sound-dai-cells = <0>;
676 clocks = <&rcc SAI2_K>;
677 clock-names = "sai_ck";
678 dmas = <&dmamux1 90 0x400 0x01>;
679 status = "disabled";
680 };
681 };
682
0a5afd3e
OM		 683 dfsdm: dfsdm@4400d000 {
684 compatible = "st,stm32mp1-dfsdm";
685 reg = <0x4400d000 0x800>;
686 clocks = <&rcc DFSDM_K>;
687 clock-names = "dfsdm";
688 #address-cells = <1>;
689 #size-cells = <0>;
690 status = "disabled";
691
692 dfsdm0: filter@0 {
693 compatible = "st,stm32-dfsdm-adc";
694 reg = <0>;
695 #io-channel-cells = <1>;
696 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
697 dmas = <&dmamux1 101 0x400 0x01>;
698 dma-names = "rx";
699 status = "disabled";
700 };
701
702 dfsdm1: filter@1 {
703 compatible = "st,stm32-dfsdm-adc";
704 reg = <1>;
705 #io-channel-cells = <1>;
706 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
707 dmas = <&dmamux1 102 0x400 0x01>;
708 dma-names = "rx";
709 status = "disabled";
710 };
711 };
712
54ceceea
AD		 713 dma1: dma-controller@48000000 {
714 compatible = "st,stm32-dma";
715 reg = <0x48000000 0x400>;
716 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
f95634be
GF		 724 clocks = <&rcc DMA1>;
725 resets = <&rcc DMA1_R>;
54ceceea
AD		 726 #dma-cells = <4>;
727 st,mem2mem;
728 dma-requests = <8>;
729 };
730
731 dma2: dma-controller@48001000 {
732 compatible = "st,stm32-dma";
733 reg = <0x48001000 0x400>;
734 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
f95634be
GF		 742 clocks = <&rcc DMA2>;
743 resets = <&rcc DMA2_R>;
54ceceea
AD		 744 #dma-cells = <4>;
745 st,mem2mem;
746 dma-requests = <8>;
747 };
748
749 dmamux1: dma-router@48002000 {
750 compatible = "st,stm32h7-dmamux";
751 reg = <0x48002000 0x40>;
f95634be
GF		 752 clocks = <&rcc DMAMUX1>;
753 resets = <&rcc DMAMUX1_R>;
54ceceea
AD		 754 #dma-cells = <3>;
755 dma-masters = <&dma1 &dma2>;
756 dma-requests = <128>;
757 dma-channels = <16>;
758 };
759
ccdab197
OM		 760 adc_2: adc@48004000 {
761 compatible = "st,stm32mp13-adc-core";
762 reg = <0x48004000 0x400>;
763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&rcc ADC2>, <&rcc ADC2_K>;
765 clock-names = "bus", "adc";
766 interrupt-controller;
767 #interrupt-cells = <1>;
768 #address-cells = <1>;
769 #size-cells = <0>;
770 status = "disabled";
771
772 adc2: adc@0 {
773 compatible = "st,stm32mp13-adc";
774 #io-channel-cells = <1>;
775 #address-cells = <1>;
776 #size-cells = <0>;
777 reg = <0x0>;
778 interrupt-parent = <&adc_2>;
779 interrupts = <0>;
780 dmas = <&dmamux1 10 0x400 0x80000001>;
781 dma-names = "rx";
782 status = "disabled";
783
784 channel@13 {
785 reg = <13>;
786 label = "vrefint";
787 };
788 channel@14 {
789 reg = <14>;
790 label = "vddcore";
791 };
792 channel@16 {
793 reg = <16>;
794 label = "vddcpu";
795 };
796 channel@17 {
797 reg = <17>;
798 label = "vddq_ddr";
799 };
800 };
801 };
802
2a46bb66
AD		 803 usbotg_hs: usb@49000000 {
804 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
805 reg = <0x49000000 0x40000>;
806 clocks = <&rcc USBO_K>;
807 clock-names = "otg";
808 resets = <&rcc USBO_R>;
809 reset-names = "dwc2";
810 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
811 g-rx-fifo-size = <512>;
812 g-np-tx-fifo-size = <32>;
813 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
814 dr_mode = "otg";
815 otg-rev = <0x200>;
816 usb33d-supply = <&usb33>;
817 status = "disabled";
818 };
819
c1689f85
VC		 820 usart1: serial@4c000000 {
821 compatible = "st,stm32h7-uart";
822 reg = <0x4c000000 0x400>;
823 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&rcc USART1_K>;
825 resets = <&rcc USART1_R>;
826 wakeup-source;
827 dmas = <&dmamux1 41 0x400 0x5>,
828 <&dmamux1 42 0x400 0x1>;
829 dma-names = "rx", "tx";
830 status = "disabled";
831 };
832
833 usart2: serial@4c001000 {
834 compatible = "st,stm32h7-uart";
835 reg = <0x4c001000 0x400>;
836 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&rcc USART2_K>;
838 resets = <&rcc USART2_R>;
839 wakeup-source;
840 dmas = <&dmamux1 43 0x400 0x5>,
841 <&dmamux1 44 0x400 0x1>;
842 dma-names = "rx", "tx";
843 status = "disabled";
844 };
845
ae8cf3b4
OM		 846 i2s4: audio-controller@4c002000 {
847 compatible = "st,stm32h7-i2s";
848 reg = <0x4c002000 0x400>;
849 #sound-dai-cells = <0>;
850 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
851 dmas = <&dmamux1 83 0x400 0x01>,
852 <&dmamux1 84 0x400 0x01>;
853 dma-names = "rx", "tx";
854 status = "disabled";
855 };
856
8539ebb4
AV		 857 spi4: spi@4c002000 {
858 compatible = "st,stm32h7-spi";
859 reg = <0x4c002000 0x400>;
860 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&rcc SPI4_K>;
862 resets = <&rcc SPI4_R>;
863 #address-cells = <1>;
864 #size-cells = <0>;
865 dmas = <&dmamux1 83 0x400 0x01>,
866 <&dmamux1 84 0x400 0x01>;
867 dma-names = "rx", "tx";
868 status = "disabled";
869 };
870
871 spi5: spi@4c003000 {
872 compatible = "st,stm32h7-spi";
873 reg = <0x4c003000 0x400>;
874 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&rcc SPI5_K>;
876 resets = <&rcc SPI5_R>;
877 #address-cells = <1>;
878 #size-cells = <0>;
879 dmas = <&dmamux1 85 0x400 0x01>,
880 <&dmamux1 86 0x400 0x01>;
881 dma-names = "rx", "tx";
882 status = "disabled";
883 };
884
446d5be8
AV		 885 i2c3: i2c@4c004000 {
886 compatible = "st,stm32mp13-i2c";
887 reg = <0x4c004000 0x400>;
888 interrupt-names = "event", "error";
889 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&rcc I2C3_K>;
892 resets = <&rcc I2C3_R>;
893 #address-cells = <1>;
894 #size-cells = <0>;
895 dmas = <&dmamux1 73 0x400 0x1>,
896 <&dmamux1 74 0x400 0x1>;
897 dma-names = "rx", "tx";
898 st,syscfg-fmp = <&syscfg 0x4 0x4>;
899 i2c-analog-filter;
900 status = "disabled";
901 };
902
903 i2c4: i2c@4c005000 {
904 compatible = "st,stm32mp13-i2c";
905 reg = <0x4c005000 0x400>;
906 interrupt-names = "event", "error";
907 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&rcc I2C4_K>;
910 resets = <&rcc I2C4_R>;
911 #address-cells = <1>;
912 #size-cells = <0>;
913 dmas = <&dmamux1 75 0x400 0x1>,
914 <&dmamux1 76 0x400 0x1>;
915 dma-names = "rx", "tx";
916 st,syscfg-fmp = <&syscfg 0x4 0x8>;
917 i2c-analog-filter;
918 status = "disabled";
919 };
920
921 i2c5: i2c@4c006000 {
922 compatible = "st,stm32mp13-i2c";
923 reg = <0x4c006000 0x400>;
924 interrupt-names = "event", "error";
925 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&rcc I2C5_K>;
928 resets = <&rcc I2C5_R>;
929 #address-cells = <1>;
930 #size-cells = <0>;
931 dmas = <&dmamux1 115 0x400 0x1>,
932 <&dmamux1 116 0x400 0x1>;
933 dma-names = "rx", "tx";
934 st,syscfg-fmp = <&syscfg 0x4 0x10>;
935 i2c-analog-filter;
936 status = "disabled";
937 };
938
bf9d876b
OM		 939 timers12: timer@4c007000 {
940 #address-cells = <1>;
941 #size-cells = <0>;
942 compatible = "st,stm32-timers";
943 reg = <0x4c007000 0x400>;
944 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
945 interrupt-names = "global";
946 clocks = <&rcc TIM12_K>;
947 clock-names = "int";
948 status = "disabled";
949
950 pwm {
951 compatible = "st,stm32-pwm";
952 #pwm-cells = <3>;
953 status = "disabled";
954 };
955
956 timer@11 {
957 compatible = "st,stm32h7-timer-trigger";
958 reg = <11>;
959 status = "disabled";
960 };
961 };
962
963 timers13: timer@4c008000 {
964 #address-cells = <1>;
965 #size-cells = <0>;
966 compatible = "st,stm32-timers";
967 reg = <0x4c008000 0x400>;
968 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
969 interrupt-names = "global";
970 clocks = <&rcc TIM13_K>;
971 clock-names = "int";
972 status = "disabled";
973
974 pwm {
975 compatible = "st,stm32-pwm";
976 #pwm-cells = <3>;
977 status = "disabled";
978 };
979
980 timer@12 {
981 compatible = "st,stm32h7-timer-trigger";
982 reg = <12>;
983 status = "disabled";
984 };
985 };
986
987 timers14: timer@4c009000 {
988 #address-cells = <1>;
989 #size-cells = <0>;
990 compatible = "st,stm32-timers";
991 reg = <0x4c009000 0x400>;
992 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "global";
994 clocks = <&rcc TIM14_K>;
995 clock-names = "int";
996 status = "disabled";
997
998 pwm {
999 compatible = "st,stm32-pwm";
1000 #pwm-cells = <3>;
1001 status = "disabled";
1002 };
1003
1004 timer@13 {
1005 compatible = "st,stm32h7-timer-trigger";
1006 reg = <13>;
1007 status = "disabled";
1008 };
1009 };
1010
1011 timers15: timer@4c00a000 {
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 compatible = "st,stm32-timers";
1015 reg = <0x4c00a000 0x400>;
1016 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1017 interrupt-names = "global";
1018 clocks = <&rcc TIM15_K>;
1019 clock-names = "int";
1020 dmas = <&dmamux1 105 0x400 0x1>,
1021 <&dmamux1 106 0x400 0x1>,
1022 <&dmamux1 107 0x400 0x1>,
1023 <&dmamux1 108 0x400 0x1>;
1024 dma-names = "ch1", "up", "trig", "com";
1025 status = "disabled";
1026
1027 pwm {
1028 compatible = "st,stm32-pwm";
1029 #pwm-cells = <3>;
1030 status = "disabled";
1031 };
1032
1033 timer@14 {
1034 compatible = "st,stm32h7-timer-trigger";
1035 reg = <14>;
1036 status = "disabled";
1037 };
1038 };
1039
1040 timers16: timer@4c00b000 {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 compatible = "st,stm32-timers";
1044 reg = <0x4c00b000 0x400>;
1045 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "global";
1047 clocks = <&rcc TIM16_K>;
1048 clock-names = "int";
1049 dmas = <&dmamux1 109 0x400 0x1>,
1050 <&dmamux1 110 0x400 0x1>;
1051 dma-names = "ch1", "up";
1052 status = "disabled";
1053
1054 pwm {
1055 compatible = "st,stm32-pwm";
1056 #pwm-cells = <3>;
1057 status = "disabled";
1058 };
1059
1060 timer@15 {
1061 compatible = "st,stm32h7-timer-trigger";
1062 reg = <15>;
1063 status = "disabled";
1064 };
1065 };
1066
1067 timers17: timer@4c00c000 {
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1070 compatible = "st,stm32-timers";
1071 reg = <0x4c00c000 0x400>;
1072 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1073 interrupt-names = "global";
1074 clocks = <&rcc TIM17_K>;
1075 clock-names = "int";
1076 dmas = <&dmamux1 111 0x400 0x1>,
1077 <&dmamux1 112 0x400 0x1>;
1078 dma-names = "ch1", "up";
1079 status = "disabled";
1080
1081 pwm {
1082 compatible = "st,stm32-pwm";
1083 #pwm-cells = <3>;
1084 status = "disabled";
1085 };
1086
1087 timer@16 {
1088 compatible = "st,stm32h7-timer-trigger";
1089 reg = <16>;
1090 status = "disabled";
1091 };
1092 };
1093
f95634be
GF		 1094 rcc: rcc@50000000 {
1095 compatible = "st,stm32mp13-rcc", "syscon";
1096 reg = <0x50000000 0x1000>;
1097 #clock-cells = <1>;
1098 #reset-cells = <1>;
1099 clock-names = "hse", "hsi", "csi", "lse", "lsi";
1100 clocks = <&scmi_clk CK_SCMI_HSE>,
1101 <&scmi_clk CK_SCMI_HSI>,
1102 <&scmi_clk CK_SCMI_CSI>,
1103 <&scmi_clk CK_SCMI_LSE>,
1104 <&scmi_clk CK_SCMI_LSI>;
1105 };
1106
f03b9808
AT		 1107 exti: interrupt-controller@5000d000 {
1108 compatible = "st,stm32mp13-exti", "syscon";
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1111 reg = <0x5000d000 0x400>;
1112 };
1113
1da8779c
AT		 1114 syscfg: syscon@50020000 {
1115 compatible = "st,stm32mp157-syscfg", "syscon";
1116 reg = <0x50020000 0x400>;
f95634be 1117 clocks = <&rcc SYSCFG>;
1da8779c
AT		 1118 };
1119
bf9d876b
OM		 1120 lptimer2: timer@50021000 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 compatible = "st,stm32-lptimer";
1124 reg = <0x50021000 0x400>;
1125 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&rcc LPTIM2_K>;
1127 clock-names = "mux";
1128 wakeup-source;
1129 status = "disabled";
1130
1131 pwm {
1132 compatible = "st,stm32-pwm-lp";
1133 #pwm-cells = <3>;
1134 status = "disabled";
1135 };
1136
1137 trigger@1 {
1138 compatible = "st,stm32-lptimer-trigger";
1139 reg = <1>;
1140 status = "disabled";
1141 };
1142
1143 counter {
1144 compatible = "st,stm32-lptimer-counter";
1145 status = "disabled";
1146 };
1147
1148 timer {
1149 compatible = "st,stm32-lptimer-timer";
1150 status = "disabled";
1151 };
1152 };
1153
1154 lptimer3: timer@50022000 {
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1157 compatible = "st,stm32-lptimer";
1158 reg = <0x50022000 0x400>;
1159 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&rcc LPTIM3_K>;
1161 clock-names = "mux";
1162 wakeup-source;
1163 status = "disabled";
1164
1165 pwm {
1166 compatible = "st,stm32-pwm-lp";
1167 #pwm-cells = <3>;
1168 status = "disabled";
1169 };
1170
1171 trigger@2 {
1172 compatible = "st,stm32-lptimer-trigger";
1173 reg = <2>;
1174 status = "disabled";
1175 };
1176
1177 timer {
1178 compatible = "st,stm32-lptimer-timer";
1179 status = "disabled";
1180 };
1181 };
1182
1183 lptimer4: timer@50023000 {
1184 compatible = "st,stm32-lptimer";
1185 reg = <0x50023000 0x400>;
1186 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&rcc LPTIM4_K>;
1188 clock-names = "mux";
1189 wakeup-source;
1190 status = "disabled";
1191
1192 pwm {
1193 compatible = "st,stm32-pwm-lp";
1194 #pwm-cells = <3>;
1195 status = "disabled";
1196 };
1197
1198 timer {
1199 compatible = "st,stm32-lptimer-timer";
1200 status = "disabled";
1201 };
1202 };
1203
1204 lptimer5: timer@50024000 {
1205 compatible = "st,stm32-lptimer";
1206 reg = <0x50024000 0x400>;
1207 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&rcc LPTIM5_K>;
1209 clock-names = "mux";
1210 wakeup-source;
1211 status = "disabled";
1212
1213 pwm {
1214 compatible = "st,stm32-pwm-lp";
1215 #pwm-cells = <3>;
1216 status = "disabled";
1217 };
1218
1219 timer {
1220 compatible = "st,stm32-lptimer-timer";
1221 status = "disabled";
1222 };
1223 };
1224
26c1d8c7
AD		 1225 mdma: dma-controller@58000000 {
1226 compatible = "st,stm32h7-mdma";
1227 reg = <0x58000000 0x1000>;
1228 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
f95634be 1229 clocks = <&rcc MDMA>;
26c1d8c7
AD		 1230 #dma-cells = <5>;
1231 dma-channels = <32>;
1232 dma-requests = <48>;
1233 };
1234
645a6037
CK		 1235 fmc: memory-controller@58002000 {
1236 compatible = "st,stm32mp1-fmc2-ebi";
1237 reg = <0x58002000 0x1000>;
1238 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1239 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1240 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1241 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1242 <4 0 0x80000000 0x10000000>; /* NAND */
1243 #address-cells = <2>;
1244 #size-cells = <1>;
1245 clocks = <&rcc FMC_K>;
1246 resets = <&rcc FMC_R>;
1247 status = "disabled";
1248
1249 nand-controller@4,0 {
1250 compatible = "st,stm32mp1-fmc2-nfc";
1251 reg = <4 0x00000000 0x1000>,
1252 <4 0x08010000 0x1000>,
1253 <4 0x08020000 0x1000>,
1254 <4 0x01000000 0x1000>,
1255 <4 0x09010000 0x1000>,
1256 <4 0x09020000 0x1000>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1260 dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>,
1261 <&mdma 24 0x2 0x12000a08 0x0 0x0>,
1262 <&mdma 25 0x2 0x12000a0a 0x0 0x0>;
1263 dma-names = "tx", "rx", "ecc";
1264 status = "disabled";
1265 };
1266 };
1267
8768487f
PC		 1268 qspi: spi@58003000 {
1269 compatible = "st,stm32f469-qspi";
1270 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1271 reg-names = "qspi", "qspi_mm";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1275 dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>,
1276 <&mdma 26 0x2 0x10100008 0x0 0x0>;
1277 dma-names = "tx", "rx";
1278 clocks = <&rcc QSPI_K>;
1279 resets = <&rcc QSPI_R>;
1280 status = "disabled";
1281 };
1282
1da8779c 1283 sdmmc1: mmc@58005000 {
3314f45c 1284 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
efdf018e 1285 arm,primecell-periphid = <0x20253180>;
1da8779c
AT		 1286 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1287 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
f95634be 1288 clocks = <&rcc SDMMC1_K>;
1da8779c 1289 clock-names = "apb_pclk";
f95634be 1290 resets = <&rcc SDMMC1_R>;
1da8779c
AT		 1291 cap-sd-highspeed;
1292 cap-mmc-highspeed;
2434845b 1293 max-frequency = <130000000>;
1da8779c
AT		 1294 status = "disabled";
1295 };
1296
a7f6433f
YG		 1297 sdmmc2: mmc@58007000 {
1298 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1299 arm,primecell-periphid = <0x20253180>;
1300 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1301 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
f95634be 1302 clocks = <&rcc SDMMC2_K>;
a7f6433f 1303 clock-names = "apb_pclk";
f95634be 1304 resets = <&rcc SDMMC2_R>;
a7f6433f
YG		 1305 cap-sd-highspeed;
1306 cap-mmc-highspeed;
1307 max-frequency = <130000000>;
1308 status = "disabled";
1309 };
1310
4a47f0f3
AD		 1311 usbh_ohci: usb@5800c000 {
1312 compatible = "generic-ohci";
1313 reg = <0x5800c000 0x1000>;
1314 clocks = <&usbphyc>, <&rcc USBH>;
1315 resets = <&rcc USBH_R>;
1316 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1317 status = "disabled";
1318 };
1319
1320 usbh_ehci: usb@5800d000 {
1321 compatible = "generic-ehci";
1322 reg = <0x5800d000 0x1000>;
1323 clocks = <&usbphyc>, <&rcc USBH>;
1324 resets = <&rcc USBH_R>;
1325 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1326 companion = <&usbh_ohci>;
1327 status = "disabled";
1328 };
1329
1da8779c
AT		 1330 iwdg2: watchdog@5a002000 {
1331 compatible = "st,stm32mp1-iwdg";
1332 reg = <0x5a002000 0x400>;
f95634be 1333 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
1da8779c
AT		 1334 clock-names = "pclk", "lsi";
1335 status = "disabled";
1336 };
1337
f54271ff
AD		 1338 usbphyc: usbphyc@5a006000 {
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 #clock-cells = <0>;
1342 compatible = "st,stm32mp1-usbphyc";
1343 reg = <0x5a006000 0x1000>;
1344 clocks = <&rcc USBPHY_K>;
1345 resets = <&rcc USBPHY_R>;
1346 vdda1v1-supply = <&reg11>;
1347 vdda1v8-supply = <&reg18>;
1348 status = "disabled";
1349
1350 usbphyc_port0: usb-phy@0 {
1351 #phy-cells = <0>;
1352 reg = <0>;
1353 };
1354
1355 usbphyc_port1: usb-phy@1 {
1356 #phy-cells = <1>;
1357 reg = <1>;
1358 };
1359 };
1360
cc2b6b6f
VC		 1361 rtc: rtc@5c004000 {
1362 compatible = "st,stm32mp1-rtc";
1363 reg = <0x5c004000 0x400>;
1364 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
f95634be
GF		 1365 clocks = <&scmi_clk CK_SCMI_RTCAPB>,
1366 <&scmi_clk CK_SCMI_RTC>;
cc2b6b6f
VC		 1367 clock-names = "pclk", "rtc_ck";
1368 status = "disabled";
1369 };
1370
1da8779c 1371 bsec: efuse@5c005000 {
7e1790d2 1372 compatible = "st,stm32mp13-bsec";
1da8779c
AT		 1373 reg = <0x5c005000 0x400>;
1374 #address-cells = <1>;
1375 #size-cells = <1>;
1376
1377 part_number_otp: part_number_otp@4 {
1378 reg = <0x4 0x2>;
366384e4 1379 bits = <0 12>;
1da8779c
AT		 1380 };
1381 ts_cal1: calib@5c {
1382 reg = <0x5c 0x2>;
1383 };
1384 ts_cal2: calib@5e {
1385 reg = <0x5e 0x2>;
1386 };
1387 };
1388
1389 /*
1390 * Break node order to solve dependency probe issue between
1391 * pinctrl and exti.
1392 */
42da167b 1393 pinctrl: pinctrl@50002000 {
1da8779c
AT		 1394 #address-cells = <1>;
1395 #size-cells = <1>;
1396 compatible = "st,stm32mp135-pinctrl";
1397 ranges = <0 0x50002000 0x8400>;
6e82a968
FD		 1398 interrupt-parent = <&exti>;
1399 st,syscfg = <&exti 0x60 0xff>;
1da8779c
AT		 1400
1401 gpioa: gpio@50002000 {
1402 gpio-controller;
1403 #gpio-cells = <2>;
1404 interrupt-controller;
1405 #interrupt-cells = <2>;
1406 reg = <0x0 0x400>;
f95634be 1407 clocks = <&rcc GPIOA>;
1da8779c
AT		 1408 st,bank-name = "GPIOA";
1409 ngpios = <16>;
1410 gpio-ranges = <&pinctrl 0 0 16>;
1411 };
1412
1413 gpiob: gpio@50003000 {
1414 gpio-controller;
1415 #gpio-cells = <2>;
1416 interrupt-controller;
1417 #interrupt-cells = <2>;
1418 reg = <0x1000 0x400>;
f95634be 1419 clocks = <&rcc GPIOB>;
1da8779c
AT		 1420 st,bank-name = "GPIOB";
1421 ngpios = <16>;
1422 gpio-ranges = <&pinctrl 0 16 16>;
1423 };
1424
1425 gpioc: gpio@50004000 {
1426 gpio-controller;
1427 #gpio-cells = <2>;
1428 interrupt-controller;
1429 #interrupt-cells = <2>;
1430 reg = <0x2000 0x400>;
f95634be 1431 clocks = <&rcc GPIOC>;
1da8779c
AT		 1432 st,bank-name = "GPIOC";
1433 ngpios = <16>;
1434 gpio-ranges = <&pinctrl 0 32 16>;
1435 };
1436
1437 gpiod: gpio@50005000 {
1438 gpio-controller;
1439 #gpio-cells = <2>;
1440 interrupt-controller;
1441 #interrupt-cells = <2>;
1442 reg = <0x3000 0x400>;
f95634be 1443 clocks = <&rcc GPIOD>;
1da8779c
AT		 1444 st,bank-name = "GPIOD";
1445 ngpios = <16>;
1446 gpio-ranges = <&pinctrl 0 48 16>;
1447 };
1448
1449 gpioe: gpio@50006000 {
1450 gpio-controller;
1451 #gpio-cells = <2>;
1452 interrupt-controller;
1453 #interrupt-cells = <2>;
1454 reg = <0x4000 0x400>;
f95634be 1455 clocks = <&rcc GPIOE>;
1da8779c
AT		 1456 st,bank-name = "GPIOE";
1457 ngpios = <16>;
1458 gpio-ranges = <&pinctrl 0 64 16>;
1459 };
1460
1461 gpiof: gpio@50007000 {
1462 gpio-controller;
1463 #gpio-cells = <2>;
1464 interrupt-controller;
1465 #interrupt-cells = <2>;
1466 reg = <0x5000 0x400>;
f95634be 1467 clocks = <&rcc GPIOF>;
1da8779c
AT		 1468 st,bank-name = "GPIOF";
1469 ngpios = <16>;
1470 gpio-ranges = <&pinctrl 0 80 16>;
1471 };
1472
1473 gpiog: gpio@50008000 {
1474 gpio-controller;
1475 #gpio-cells = <2>;
1476 interrupt-controller;
1477 #interrupt-cells = <2>;
1478 reg = <0x6000 0x400>;
f95634be 1479 clocks = <&rcc GPIOG>;
1da8779c
AT		 1480 st,bank-name = "GPIOG";
1481 ngpios = <16>;
1482 gpio-ranges = <&pinctrl 0 96 16>;
1483 };
1484
1485 gpioh: gpio@50009000 {
1486 gpio-controller;
1487 #gpio-cells = <2>;
1488 interrupt-controller;
1489 #interrupt-cells = <2>;
1490 reg = <0x7000 0x400>;
f95634be 1491 clocks = <&rcc GPIOH>;
1da8779c
AT		 1492 st,bank-name = "GPIOH";
1493 ngpios = <15>;
1494 gpio-ranges = <&pinctrl 0 112 15>;
1495 };
1496
1497 gpioi: gpio@5000a000 {
1498 gpio-controller;
1499 #gpio-cells = <2>;
1500 interrupt-controller;
1501 #interrupt-cells = <2>;
1502 reg = <0x8000 0x400>;
f95634be 1503 clocks = <&rcc GPIOI>;
1da8779c
AT		 1504 st,bank-name = "GPIOI";
1505 ngpios = <8>;
1506 gpio-ranges = <&pinctrl 0 128 8>;
1507 };
1508 };
1509 };
1510};
A mirror of Linus' kernel repository