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Commit | Line | Data |
---|---|---|
15e524a4 SW |
1 | /dts-v1/; |
2 | ||
3 | #include <dt-bindings/input/input.h> | |
4 | #include "tegra124.dtsi" | |
5 | ||
6e72cf00 MP |
6 | #include "tegra124-jetson-tk1-emc.dtsi" |
7 | ||
15e524a4 SW |
8 | / { |
9 | model = "NVIDIA Tegra124 Jetson TK1"; | |
10 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; | |
11 | ||
12 | aliases { | |
13 | rtc0 = "/i2c@0,7000d000/pmic@40"; | |
14 | rtc1 = "/rtc@0,7000e000"; | |
c4574aa0 | 15 | serial0 = &uartd; |
15e524a4 SW |
16 | }; |
17 | ||
18 | memory { | |
19 | reg = <0x0 0x80000000 0x0 0x80000000>; | |
20 | }; | |
21 | ||
8e2b9e4d TR |
22 | pcie-controller@0,01003000 { |
23 | status = "okay"; | |
24 | ||
25 | avddio-pex-supply = <&vdd_1v05_run>; | |
26 | dvddio-pex-supply = <&vdd_1v05_run>; | |
27 | avdd-pex-pll-supply = <&vdd_1v05_run>; | |
28 | hvdd-pex-supply = <&vdd_3v3_lp0>; | |
29 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; | |
30 | vddio-pex-ctl-supply = <&vdd_3v3_lp0>; | |
31 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
32 | ||
33 | pci@1,0 { | |
34 | status = "okay"; | |
35 | }; | |
36 | ||
37 | pci@2,0 { | |
38 | status = "okay"; | |
39 | }; | |
40 | }; | |
41 | ||
6054dd39 TR |
42 | host1x@0,50000000 { |
43 | hdmi@0,54280000 { | |
44 | status = "okay"; | |
45 | ||
46 | hdmi-supply = <&vdd_5v0_hdmi>; | |
47 | pll-supply = <&vdd_hdmi_pll>; | |
48 | vdd-supply = <&vdd_3v3_hdmi>; | |
49 | ||
50 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
51 | nvidia,hpd-gpio = | |
52 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
53 | }; | |
54 | }; | |
55 | ||
15e524a4 | 56 | pinmux: pinmux@0,70000868 { |
6dbaff2b SW |
57 | pinctrl-names = "boot"; |
58 | pinctrl-0 = <&state_boot>; | |
15e524a4 | 59 | |
6dbaff2b | 60 | state_boot: pinmux { |
15e524a4 SW |
61 | clk_32k_out_pa0 { |
62 | nvidia,pins = "clk_32k_out_pa0"; | |
63 | nvidia,function = "soc"; | |
64 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 65 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
66 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
67 | }; | |
68 | uart3_cts_n_pa1 { | |
69 | nvidia,pins = "uart3_cts_n_pa1"; | |
fb816641 SW |
70 | nvidia,function = "gmi"; |
71 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
72 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
73 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
74 | }; |
75 | dap2_fs_pa2 { | |
76 | nvidia,pins = "dap2_fs_pa2"; | |
77 | nvidia,function = "i2s1"; | |
78 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
79 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 80 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
81 | }; |
82 | dap2_sclk_pa3 { | |
83 | nvidia,pins = "dap2_sclk_pa3"; | |
84 | nvidia,function = "i2s1"; | |
85 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
86 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
88 | }; |
89 | dap2_din_pa4 { | |
90 | nvidia,pins = "dap2_din_pa4"; | |
91 | nvidia,function = "i2s1"; | |
92 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 93 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
94 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
95 | }; | |
96 | dap2_dout_pa5 { | |
97 | nvidia,pins = "dap2_dout_pa5"; | |
98 | nvidia,function = "i2s1"; | |
99 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
100 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 101 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
102 | }; |
103 | sdmmc3_clk_pa6 { | |
104 | nvidia,pins = "sdmmc3_clk_pa6"; | |
105 | nvidia,function = "sdmmc3"; | |
106 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 108 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
109 | }; |
110 | sdmmc3_cmd_pa7 { | |
111 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
112 | nvidia,function = "sdmmc3"; | |
113 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
115 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
116 | }; | |
117 | pb0 { | |
118 | nvidia,pins = "pb0"; | |
119 | nvidia,function = "uartd"; | |
120 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 121 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
122 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
123 | }; | |
124 | pb1 { | |
125 | nvidia,pins = "pb1"; | |
126 | nvidia,function = "uartd"; | |
127 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 128 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
130 | }; | |
131 | sdmmc3_dat3_pb4 { | |
132 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
133 | nvidia,function = "sdmmc3"; | |
134 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
135 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
136 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
137 | }; | |
138 | sdmmc3_dat2_pb5 { | |
139 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
140 | nvidia,function = "sdmmc3"; | |
141 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
142 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
143 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
144 | }; | |
145 | sdmmc3_dat1_pb6 { | |
146 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
147 | nvidia,function = "sdmmc3"; | |
148 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
149 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
150 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
151 | }; | |
152 | sdmmc3_dat0_pb7 { | |
153 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
154 | nvidia,function = "sdmmc3"; | |
155 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
156 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
157 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
158 | }; | |
159 | uart3_rts_n_pc0 { | |
160 | nvidia,pins = "uart3_rts_n_pc0"; | |
fb816641 SW |
161 | nvidia,function = "gmi"; |
162 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
163 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
164 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
165 | }; | |
166 | uart2_txd_pc2 { | |
167 | nvidia,pins = "uart2_txd_pc2"; | |
168 | nvidia,function = "irda"; | |
169 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
170 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
171 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
172 | }; | |
173 | uart2_rxd_pc3 { | |
174 | nvidia,pins = "uart2_rxd_pc3"; | |
175 | nvidia,function = "irda"; | |
176 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 177 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
179 | }; | |
180 | gen1_i2c_scl_pc4 { | |
181 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
182 | nvidia,function = "i2c1"; | |
183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
185 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
186 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
187 | }; | |
188 | gen1_i2c_sda_pc5 { | |
189 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
190 | nvidia,function = "i2c1"; | |
191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
193 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
194 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
195 | }; | |
196 | pc7 { | |
197 | nvidia,pins = "pc7"; | |
198 | nvidia,function = "rsvd1"; | |
fb816641 SW |
199 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
200 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
202 | }; |
203 | pg0 { | |
204 | nvidia,pins = "pg0"; | |
15e524a4 | 205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
207 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
208 | }; |
209 | pg1 { | |
210 | nvidia,pins = "pg1"; | |
15e524a4 | 211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
212 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
213 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
214 | }; |
215 | pg2 { | |
216 | nvidia,pins = "pg2"; | |
fb816641 SW |
217 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
218 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
219 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
220 | }; | |
221 | pg3 { | |
222 | nvidia,pins = "pg3"; | |
fb816641 SW |
223 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
225 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
226 | }; | |
227 | pg4 { | |
228 | nvidia,pins = "pg4"; | |
15e524a4 | 229 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
230 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
231 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
232 | }; |
233 | pg5 { | |
234 | nvidia,pins = "pg5"; | |
235 | nvidia,function = "spi4"; | |
236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
238 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
239 | }; | |
240 | pg6 { | |
241 | nvidia,pins = "pg6"; | |
242 | nvidia,function = "spi4"; | |
243 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
244 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
245 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
246 | }; | |
247 | pg7 { | |
248 | nvidia,pins = "pg7"; | |
249 | nvidia,function = "spi4"; | |
250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 251 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
252 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
253 | }; | |
254 | ph0 { | |
255 | nvidia,pins = "ph0"; | |
256 | nvidia,function = "gmi"; | |
257 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
258 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
259 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
260 | }; | |
261 | ph1 { | |
262 | nvidia,pins = "ph1"; | |
263 | nvidia,function = "pwm1"; | |
264 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
265 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
266 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
267 | }; | |
268 | ph2 { | |
269 | nvidia,pins = "ph2"; | |
15e524a4 SW |
270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
272 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
273 | }; | |
274 | ph3 { | |
275 | nvidia,pins = "ph3"; | |
276 | nvidia,function = "gmi"; | |
fb816641 SW |
277 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
279 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
280 | }; | |
281 | ph4 { | |
282 | nvidia,pins = "ph4"; | |
fb816641 SW |
283 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
284 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
286 | }; | |
287 | ph5 { | |
288 | nvidia,pins = "ph5"; | |
289 | nvidia,function = "rsvd2"; | |
fb816641 SW |
290 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
291 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
293 | }; | |
294 | ph6 { | |
295 | nvidia,pins = "ph6"; | |
296 | nvidia,function = "gmi"; | |
fb816641 SW |
297 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
298 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
299 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
300 | }; |
301 | ph7 { | |
302 | nvidia,pins = "ph7"; | |
15e524a4 SW |
303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
304 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 305 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
306 | }; |
307 | pi0 { | |
308 | nvidia,pins = "pi0"; | |
15e524a4 SW |
309 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
311 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
312 | }; | |
313 | pi1 { | |
314 | nvidia,pins = "pi1"; | |
fb816641 | 315 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 317 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
318 | }; |
319 | pi2 { | |
320 | nvidia,pins = "pi2"; | |
321 | nvidia,function = "rsvd4"; | |
fb816641 SW |
322 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
323 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
324 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
325 | }; | |
326 | pi3 { | |
327 | nvidia,pins = "pi3"; | |
328 | nvidia,function = "spi4"; | |
329 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
331 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
332 | }; | |
333 | pi4 { | |
334 | nvidia,pins = "pi4"; | |
335 | nvidia,function = "gmi"; | |
fb816641 SW |
336 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
337 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
338 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
339 | }; | |
340 | pi5 { | |
341 | nvidia,pins = "pi5"; | |
342 | nvidia,function = "rsvd2"; | |
fb816641 SW |
343 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
344 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
345 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
346 | }; |
347 | pi6 { | |
348 | nvidia,pins = "pi6"; | |
fb816641 SW |
349 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
350 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
351 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
352 | }; | |
353 | pi7 { | |
354 | nvidia,pins = "pi7"; | |
355 | nvidia,function = "rsvd1"; | |
356 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
357 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
358 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
359 | }; | |
360 | pj0 { | |
361 | nvidia,pins = "pj0"; | |
fb816641 SW |
362 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
363 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
364 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
365 | }; | |
366 | pj2 { | |
367 | nvidia,pins = "pj2"; | |
368 | nvidia,function = "rsvd1"; | |
fb816641 SW |
369 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
370 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
371 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
372 | }; |
373 | uart2_cts_n_pj5 { | |
374 | nvidia,pins = "uart2_cts_n_pj5"; | |
375 | nvidia,function = "uartb"; | |
376 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 377 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
378 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
379 | }; | |
380 | uart2_rts_n_pj6 { | |
381 | nvidia,pins = "uart2_rts_n_pj6"; | |
382 | nvidia,function = "uartb"; | |
383 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
384 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
385 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
386 | }; | |
387 | pj7 { | |
388 | nvidia,pins = "pj7"; | |
389 | nvidia,function = "uartd"; | |
390 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
391 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
392 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
393 | }; | |
394 | pk0 { | |
395 | nvidia,pins = "pk0"; | |
fb816641 SW |
396 | nvidia,function = "rsvd1"; |
397 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
398 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
399 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
400 | }; |
401 | pk1 { | |
402 | nvidia,pins = "pk1"; | |
15e524a4 SW |
403 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
404 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
405 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
406 | }; | |
407 | pk2 { | |
408 | nvidia,pins = "pk2"; | |
fb816641 | 409 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
410 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
411 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
412 | }; | |
413 | pk3 { | |
414 | nvidia,pins = "pk3"; | |
415 | nvidia,function = "gmi"; | |
fb816641 SW |
416 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
417 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
418 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
419 | }; |
420 | pk4 { | |
421 | nvidia,pins = "pk4"; | |
15e524a4 SW |
422 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
423 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
424 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
425 | }; | |
426 | spdif_out_pk5 { | |
427 | nvidia,pins = "spdif_out_pk5"; | |
428 | nvidia,function = "rsvd2"; | |
fb816641 SW |
429 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
430 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
431 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
432 | }; | |
433 | spdif_in_pk6 { | |
434 | nvidia,pins = "spdif_in_pk6"; | |
15e524a4 SW |
435 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
436 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
438 | }; | |
439 | pk7 { | |
440 | nvidia,pins = "pk7"; | |
441 | nvidia,function = "uartd"; | |
442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
444 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
445 | }; | |
446 | dap1_fs_pn0 { | |
447 | nvidia,pins = "dap1_fs_pn0"; | |
fb816641 | 448 | nvidia,function = "rsvd4"; |
15e524a4 | 449 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
450 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
451 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
452 | }; |
453 | dap1_din_pn1 { | |
454 | nvidia,pins = "dap1_din_pn1"; | |
fb816641 | 455 | nvidia,function = "rsvd4"; |
15e524a4 | 456 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
457 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
458 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
459 | }; |
460 | dap1_dout_pn2 { | |
461 | nvidia,pins = "dap1_dout_pn2"; | |
462 | nvidia,function = "sata"; | |
463 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
465 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
466 | }; | |
467 | dap1_sclk_pn3 { | |
468 | nvidia,pins = "dap1_sclk_pn3"; | |
fb816641 | 469 | nvidia,function = "rsvd4"; |
15e524a4 | 470 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
471 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
472 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
473 | }; |
474 | usb_vbus_en0_pn4 { | |
475 | nvidia,pins = "usb_vbus_en0_pn4"; | |
476 | nvidia,function = "usb"; | |
fb816641 | 477 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
479 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 480 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
481 | }; |
482 | usb_vbus_en1_pn5 { | |
483 | nvidia,pins = "usb_vbus_en1_pn5"; | |
484 | nvidia,function = "usb"; | |
fb816641 | 485 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
486 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
487 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 488 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
489 | }; |
490 | hdmi_int_pn7 { | |
491 | nvidia,pins = "hdmi_int_pn7"; | |
15e524a4 | 492 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 | 493 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
494 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
495 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
496 | }; | |
497 | ulpi_data7_po0 { | |
498 | nvidia,pins = "ulpi_data7_po0"; | |
499 | nvidia,function = "ulpi"; | |
fb816641 SW |
500 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
501 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
502 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
503 | }; |
504 | ulpi_data0_po1 { | |
505 | nvidia,pins = "ulpi_data0_po1"; | |
fb816641 SW |
506 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
507 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
508 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
509 | }; | |
510 | ulpi_data1_po2 { | |
511 | nvidia,pins = "ulpi_data1_po2"; | |
512 | nvidia,function = "ulpi"; | |
fb816641 SW |
513 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
514 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
515 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
516 | }; |
517 | ulpi_data2_po3 { | |
518 | nvidia,pins = "ulpi_data2_po3"; | |
519 | nvidia,function = "ulpi"; | |
fb816641 SW |
520 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
521 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
522 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
523 | }; |
524 | ulpi_data3_po4 { | |
525 | nvidia,pins = "ulpi_data3_po4"; | |
fb816641 SW |
526 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
527 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
528 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
529 | }; | |
530 | ulpi_data4_po5 { | |
531 | nvidia,pins = "ulpi_data4_po5"; | |
532 | nvidia,function = "ulpi"; | |
fb816641 SW |
533 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
534 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
535 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
536 | }; |
537 | ulpi_data5_po6 { | |
538 | nvidia,pins = "ulpi_data5_po6"; | |
539 | nvidia,function = "ulpi"; | |
fb816641 SW |
540 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
541 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
542 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
543 | }; | |
544 | ulpi_data6_po7 { | |
545 | nvidia,pins = "ulpi_data6_po7"; | |
546 | nvidia,function = "ulpi"; | |
fb816641 SW |
547 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
548 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
549 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
550 | }; |
551 | dap3_fs_pp0 { | |
552 | nvidia,pins = "dap3_fs_pp0"; | |
553 | nvidia,function = "i2s2"; | |
fb816641 SW |
554 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
555 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
556 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
557 | }; | |
558 | dap3_din_pp1 { | |
559 | nvidia,pins = "dap3_din_pp1"; | |
560 | nvidia,function = "i2s2"; | |
fb816641 SW |
561 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
562 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
563 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
564 | }; | |
565 | dap3_dout_pp2 { | |
566 | nvidia,pins = "dap3_dout_pp2"; | |
15e524a4 SW |
567 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
568 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
569 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
570 | }; | |
571 | dap3_sclk_pp3 { | |
572 | nvidia,pins = "dap3_sclk_pp3"; | |
573 | nvidia,function = "rsvd3"; | |
574 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
575 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
576 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
577 | }; | |
578 | dap4_fs_pp4 { | |
579 | nvidia,pins = "dap4_fs_pp4"; | |
fb816641 | 580 | nvidia,function = "rsvd4"; |
15e524a4 | 581 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
582 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
583 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
584 | }; |
585 | dap4_din_pp5 { | |
586 | nvidia,pins = "dap4_din_pp5"; | |
fb816641 | 587 | nvidia,function = "rsvd3"; |
15e524a4 | 588 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
589 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
590 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
591 | }; |
592 | dap4_dout_pp6 { | |
593 | nvidia,pins = "dap4_dout_pp6"; | |
fb816641 | 594 | nvidia,function = "rsvd4"; |
15e524a4 | 595 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
596 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
597 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
598 | }; |
599 | dap4_sclk_pp7 { | |
600 | nvidia,pins = "dap4_sclk_pp7"; | |
fb816641 | 601 | nvidia,function = "rsvd3"; |
15e524a4 | 602 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
603 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
604 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
605 | }; |
606 | kb_col0_pq0 { | |
607 | nvidia,pins = "kb_col0_pq0"; | |
15e524a4 | 608 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 609 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
610 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
611 | }; | |
612 | kb_col1_pq1 { | |
613 | nvidia,pins = "kb_col1_pq1"; | |
614 | nvidia,function = "rsvd2"; | |
fb816641 SW |
615 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
616 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
617 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
618 | }; |
619 | kb_col2_pq2 { | |
620 | nvidia,pins = "kb_col2_pq2"; | |
621 | nvidia,function = "rsvd2"; | |
fb816641 SW |
622 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
623 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
624 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
625 | }; |
626 | kb_col3_pq3 { | |
627 | nvidia,pins = "kb_col3_pq3"; | |
fb816641 | 628 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 629 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 630 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
631 | }; |
632 | kb_col4_pq4 { | |
633 | nvidia,pins = "kb_col4_pq4"; | |
634 | nvidia,function = "sdmmc3"; | |
635 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 636 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
637 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
638 | }; | |
639 | kb_col5_pq5 { | |
640 | nvidia,pins = "kb_col5_pq5"; | |
fb816641 SW |
641 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
642 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
644 | }; | |
645 | kb_col6_pq6 { | |
646 | nvidia,pins = "kb_col6_pq6"; | |
647 | nvidia,function = "rsvd2"; | |
fb816641 SW |
648 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
649 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
650 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
651 | }; |
652 | kb_col7_pq7 { | |
653 | nvidia,pins = "kb_col7_pq7"; | |
fb816641 SW |
654 | nvidia,function = "rsvd2"; |
655 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
656 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
657 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
658 | }; |
659 | kb_row0_pr0 { | |
660 | nvidia,pins = "kb_row0_pr0"; | |
15e524a4 SW |
661 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
662 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
663 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
664 | }; | |
665 | kb_row1_pr1 { | |
666 | nvidia,pins = "kb_row1_pr1"; | |
667 | nvidia,function = "rsvd2"; | |
fb816641 SW |
668 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
669 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
670 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
671 | }; | |
672 | kb_row2_pr2 { | |
673 | nvidia,pins = "kb_row2_pr2"; | |
15e524a4 SW |
674 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
675 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
676 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
677 | }; | |
678 | kb_row3_pr3 { | |
679 | nvidia,pins = "kb_row3_pr3"; | |
fb816641 SW |
680 | nvidia,function = "kbc"; |
681 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
682 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
683 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
684 | }; | |
685 | kb_row4_pr4 { | |
686 | nvidia,pins = "kb_row4_pr4"; | |
fb816641 SW |
687 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
688 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
689 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
690 | }; | |
691 | kb_row5_pr5 { | |
692 | nvidia,pins = "kb_row5_pr5"; | |
693 | nvidia,function = "rsvd3"; | |
fb816641 SW |
694 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
695 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
696 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
697 | }; | |
698 | kb_row6_pr6 { | |
699 | nvidia,pins = "kb_row6_pr6"; | |
700 | nvidia,function = "displaya_alt"; | |
fb816641 SW |
701 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
702 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
703 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
704 | }; | |
705 | kb_row7_pr7 { | |
706 | nvidia,pins = "kb_row7_pr7"; | |
fb816641 SW |
707 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
708 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
709 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
710 | }; | |
711 | kb_row8_ps0 { | |
712 | nvidia,pins = "kb_row8_ps0"; | |
713 | nvidia,function = "rsvd2"; | |
fb816641 SW |
714 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
715 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
716 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
717 | }; |
718 | kb_row9_ps1 { | |
719 | nvidia,pins = "kb_row9_ps1"; | |
fb816641 | 720 | nvidia,function = "uarta"; |
15e524a4 SW |
721 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
722 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
723 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
724 | }; | |
725 | kb_row10_ps2 { | |
726 | nvidia,pins = "kb_row10_ps2"; | |
fb816641 | 727 | nvidia,function = "uarta"; |
15e524a4 | 728 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 729 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
730 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
731 | }; | |
732 | kb_row11_ps3 { | |
733 | nvidia,pins = "kb_row11_ps3"; | |
734 | nvidia,function = "rsvd2"; | |
fb816641 SW |
735 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
736 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
737 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
738 | }; | |
739 | kb_row12_ps4 { | |
740 | nvidia,pins = "kb_row12_ps4"; | |
741 | nvidia,function = "rsvd2"; | |
fb816641 SW |
742 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
743 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
744 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
745 | }; | |
746 | kb_row13_ps5 { | |
747 | nvidia,pins = "kb_row13_ps5"; | |
748 | nvidia,function = "rsvd2"; | |
fb816641 SW |
749 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
750 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
751 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
752 | }; |
753 | kb_row14_ps6 { | |
754 | nvidia,pins = "kb_row14_ps6"; | |
755 | nvidia,function = "rsvd2"; | |
fb816641 SW |
756 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
757 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
758 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
759 | }; | |
760 | kb_row15_ps7 { | |
761 | nvidia,pins = "kb_row15_ps7"; | |
fb816641 SW |
762 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
763 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
764 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
765 | }; | |
766 | kb_row16_pt0 { | |
767 | nvidia,pins = "kb_row16_pt0"; | |
15e524a4 SW |
768 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
769 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
770 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
771 | }; | |
772 | kb_row17_pt1 { | |
773 | nvidia,pins = "kb_row17_pt1"; | |
15e524a4 | 774 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
775 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
776 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
777 | }; |
778 | gen2_i2c_scl_pt5 { | |
779 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
780 | nvidia,function = "i2c2"; | |
781 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
782 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
783 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
784 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
785 | }; | |
786 | gen2_i2c_sda_pt6 { | |
787 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
788 | nvidia,function = "i2c2"; | |
789 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
790 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
791 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
792 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
793 | }; | |
794 | sdmmc4_cmd_pt7 { | |
795 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
796 | nvidia,function = "sdmmc4"; | |
797 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
798 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
799 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
800 | }; | |
801 | pu0 { | |
802 | nvidia,pins = "pu0"; | |
15e524a4 SW |
803 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
806 | }; |
807 | pu1 { | |
808 | nvidia,pins = "pu1"; | |
fb816641 | 809 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
810 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
811 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
812 | }; | |
813 | pu2 { | |
814 | nvidia,pins = "pu2"; | |
fb816641 | 815 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
816 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
817 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
818 | }; | |
819 | pu3 { | |
820 | nvidia,pins = "pu3"; | |
15e524a4 SW |
821 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
822 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 823 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
824 | }; |
825 | pu4 { | |
826 | nvidia,pins = "pu4"; | |
15e524a4 SW |
827 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
828 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 829 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
830 | }; |
831 | pu5 { | |
832 | nvidia,pins = "pu5"; | |
fb816641 | 833 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
834 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
835 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
836 | }; | |
837 | pu6 { | |
838 | nvidia,pins = "pu6"; | |
fb816641 | 839 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
840 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
841 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
842 | }; | |
843 | pv0 { | |
844 | nvidia,pins = "pv0"; | |
fb816641 SW |
845 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
846 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
847 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
848 | }; | |
849 | pv1 { | |
850 | nvidia,pins = "pv1"; | |
fb816641 SW |
851 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
852 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
853 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
854 | }; | |
855 | sdmmc3_cd_n_pv2 { | |
856 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
857 | nvidia,function = "sdmmc3"; | |
858 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 859 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
860 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
861 | }; | |
862 | sdmmc1_wp_n_pv3 { | |
863 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
864 | nvidia,function = "sdmmc1"; | |
865 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
866 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
867 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
868 | }; | |
869 | ddc_scl_pv4 { | |
870 | nvidia,pins = "ddc_scl_pv4"; | |
871 | nvidia,function = "i2c4"; | |
872 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
873 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
874 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
875 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
876 | }; | |
877 | ddc_sda_pv5 { | |
878 | nvidia,pins = "ddc_sda_pv5"; | |
879 | nvidia,function = "i2c4"; | |
880 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
881 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
882 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
883 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
884 | }; | |
885 | gpio_w2_aud_pw2 { | |
886 | nvidia,pins = "gpio_w2_aud_pw2"; | |
887 | nvidia,function = "rsvd2"; | |
fb816641 SW |
888 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
889 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
890 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
891 | }; |
892 | gpio_w3_aud_pw3 { | |
893 | nvidia,pins = "gpio_w3_aud_pw3"; | |
894 | nvidia,function = "spi6"; | |
fb816641 SW |
895 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
896 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
897 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
898 | }; |
899 | dap_mclk1_pw4 { | |
900 | nvidia,pins = "dap_mclk1_pw4"; | |
901 | nvidia,function = "extperiph1"; | |
902 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
903 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
904 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
905 | }; | |
906 | clk2_out_pw5 { | |
907 | nvidia,pins = "clk2_out_pw5"; | |
908 | nvidia,function = "extperiph2"; | |
909 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
910 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
911 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
912 | }; | |
913 | uart3_txd_pw6 { | |
914 | nvidia,pins = "uart3_txd_pw6"; | |
fb816641 SW |
915 | nvidia,function = "rsvd2"; |
916 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
917 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
918 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
919 | }; | |
920 | uart3_rxd_pw7 { | |
921 | nvidia,pins = "uart3_rxd_pw7"; | |
fb816641 SW |
922 | nvidia,function = "rsvd2"; |
923 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
924 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
925 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
926 | }; |
927 | dvfs_pwm_px0 { | |
928 | nvidia,pins = "dvfs_pwm_px0"; | |
929 | nvidia,function = "cldvfs"; | |
930 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
931 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
932 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
933 | }; | |
934 | gpio_x1_aud_px1 { | |
935 | nvidia,pins = "gpio_x1_aud_px1"; | |
15e524a4 | 936 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
937 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
938 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
939 | }; |
940 | dvfs_clk_px2 { | |
941 | nvidia,pins = "dvfs_clk_px2"; | |
942 | nvidia,function = "cldvfs"; | |
943 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
944 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
945 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
946 | }; | |
947 | gpio_x3_aud_px3 { | |
948 | nvidia,pins = "gpio_x3_aud_px3"; | |
949 | nvidia,function = "rsvd4"; | |
fb816641 SW |
950 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
951 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
952 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
953 | }; |
954 | gpio_x4_aud_px4 { | |
955 | nvidia,pins = "gpio_x4_aud_px4"; | |
15e524a4 | 956 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
957 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
958 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
959 | }; |
960 | gpio_x5_aud_px5 { | |
961 | nvidia,pins = "gpio_x5_aud_px5"; | |
962 | nvidia,function = "rsvd4"; | |
fb816641 SW |
963 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
964 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
965 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
966 | }; |
967 | gpio_x6_aud_px6 { | |
968 | nvidia,pins = "gpio_x6_aud_px6"; | |
969 | nvidia,function = "gmi"; | |
fb816641 SW |
970 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
971 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
972 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
973 | }; |
974 | gpio_x7_aud_px7 { | |
975 | nvidia,pins = "gpio_x7_aud_px7"; | |
15e524a4 SW |
976 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
977 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
978 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
979 | }; | |
980 | ulpi_clk_py0 { | |
981 | nvidia,pins = "ulpi_clk_py0"; | |
982 | nvidia,function = "spi1"; | |
983 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
984 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
985 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
986 | }; | |
987 | ulpi_dir_py1 { | |
988 | nvidia,pins = "ulpi_dir_py1"; | |
989 | nvidia,function = "spi1"; | |
fb816641 SW |
990 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
991 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
992 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
993 | }; | |
994 | ulpi_nxt_py2 { | |
995 | nvidia,pins = "ulpi_nxt_py2"; | |
996 | nvidia,function = "spi1"; | |
997 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
998 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
999 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1000 | }; | |
1001 | ulpi_stp_py3 { | |
1002 | nvidia,pins = "ulpi_stp_py3"; | |
1003 | nvidia,function = "spi1"; | |
1004 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1005 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1006 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1007 | }; | |
1008 | sdmmc1_dat3_py4 { | |
1009 | nvidia,pins = "sdmmc1_dat3_py4"; | |
1010 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1011 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1012 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1013 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1014 | }; |
1015 | sdmmc1_dat2_py5 { | |
1016 | nvidia,pins = "sdmmc1_dat2_py5"; | |
1017 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1018 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1019 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1020 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1021 | }; |
1022 | sdmmc1_dat1_py6 { | |
1023 | nvidia,pins = "sdmmc1_dat1_py6"; | |
1024 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1025 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1026 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1027 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1028 | }; |
1029 | sdmmc1_dat0_py7 { | |
1030 | nvidia,pins = "sdmmc1_dat0_py7"; | |
fb816641 SW |
1031 | nvidia,function = "rsvd2"; |
1032 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1033 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1034 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1035 | }; |
1036 | sdmmc1_clk_pz0 { | |
1037 | nvidia,pins = "sdmmc1_clk_pz0"; | |
fb816641 SW |
1038 | nvidia,function = "rsvd3"; |
1039 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1040 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1041 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1042 | }; |
1043 | sdmmc1_cmd_pz1 { | |
1044 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1045 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1046 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1047 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1048 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1049 | }; |
1050 | pwr_i2c_scl_pz6 { | |
1051 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1052 | nvidia,function = "i2cpwr"; | |
1053 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1054 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1055 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1056 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1057 | }; | |
1058 | pwr_i2c_sda_pz7 { | |
1059 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1060 | nvidia,function = "i2cpwr"; | |
1061 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1062 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1063 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1064 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1065 | }; | |
1066 | sdmmc4_dat0_paa0 { | |
1067 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1068 | nvidia,function = "sdmmc4"; | |
1069 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1070 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1071 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1072 | }; | |
1073 | sdmmc4_dat1_paa1 { | |
1074 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1075 | nvidia,function = "sdmmc4"; | |
1076 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1077 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1078 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1079 | }; | |
1080 | sdmmc4_dat2_paa2 { | |
1081 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1082 | nvidia,function = "sdmmc4"; | |
1083 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1084 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1085 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1086 | }; | |
1087 | sdmmc4_dat3_paa3 { | |
1088 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1089 | nvidia,function = "sdmmc4"; | |
1090 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1091 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1092 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1093 | }; | |
1094 | sdmmc4_dat4_paa4 { | |
1095 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1096 | nvidia,function = "sdmmc4"; | |
1097 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1098 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1099 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1100 | }; | |
1101 | sdmmc4_dat5_paa5 { | |
1102 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1103 | nvidia,function = "sdmmc4"; | |
1104 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1105 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1106 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1107 | }; | |
1108 | sdmmc4_dat6_paa6 { | |
1109 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1110 | nvidia,function = "sdmmc4"; | |
1111 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1112 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1113 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1114 | }; | |
1115 | sdmmc4_dat7_paa7 { | |
1116 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1117 | nvidia,function = "sdmmc4"; | |
1118 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1119 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1120 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1121 | }; | |
1122 | pbb0 { | |
1123 | nvidia,pins = "pbb0"; | |
1124 | nvidia,function = "vimclk2_alt"; | |
1125 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1127 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1128 | }; | |
1129 | cam_i2c_scl_pbb1 { | |
1130 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1131 | nvidia,function = "i2c3"; | |
1132 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1134 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1135 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1136 | }; | |
1137 | cam_i2c_sda_pbb2 { | |
1138 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1139 | nvidia,function = "i2c3"; | |
1140 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1143 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1144 | }; | |
1145 | pbb3 { | |
1146 | nvidia,pins = "pbb3"; | |
15e524a4 SW |
1147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1149 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1150 | }; | |
1151 | pbb4 { | |
1152 | nvidia,pins = "pbb4"; | |
1153 | nvidia,function = "vgp4"; | |
1154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1155 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1156 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1157 | }; | |
1158 | pbb5 { | |
1159 | nvidia,pins = "pbb5"; | |
15e524a4 SW |
1160 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1161 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1162 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1163 | }; | |
1164 | pbb6 { | |
1165 | nvidia,pins = "pbb6"; | |
15e524a4 SW |
1166 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1168 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1169 | }; | |
1170 | pbb7 { | |
1171 | nvidia,pins = "pbb7"; | |
15e524a4 SW |
1172 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1173 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1174 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1175 | }; | |
1176 | cam_mclk_pcc0 { | |
1177 | nvidia,pins = "cam_mclk_pcc0"; | |
1178 | nvidia,function = "vi_alt3"; | |
1179 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1180 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1181 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1182 | }; | |
1183 | pcc1 { | |
1184 | nvidia,pins = "pcc1"; | |
fb816641 | 1185 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1186 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1187 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1188 | }; | |
1189 | pcc2 { | |
1190 | nvidia,pins = "pcc2"; | |
fb816641 | 1191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1193 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1194 | }; | |
1195 | sdmmc4_clk_pcc4 { | |
1196 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1197 | nvidia,function = "sdmmc4"; | |
1198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1199 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1200 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1201 | }; | |
1202 | clk2_req_pcc5 { | |
1203 | nvidia,pins = "clk2_req_pcc5"; | |
1204 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1205 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1207 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1208 | }; | |
b0da12d5 SW |
1209 | pex_l0_rst_n_pdd1 { |
1210 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1211 | nvidia,function = "pe0"; | |
1212 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1213 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1214 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1215 | }; | |
1216 | pex_l0_clkreq_n_pdd2 { | |
1217 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1218 | nvidia,function = "pe0"; | |
fb816641 SW |
1219 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1220 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1221 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1222 | }; | |
1223 | pex_wake_n_pdd3 { | |
1224 | nvidia,pins = "pex_wake_n_pdd3"; | |
1225 | nvidia,function = "pe"; | |
fb816641 SW |
1226 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1227 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1228 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1229 | }; | |
1230 | pex_l1_rst_n_pdd5 { | |
1231 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1232 | nvidia,function = "pe1"; | |
1233 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1234 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1235 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1236 | }; | |
1237 | pex_l1_clkreq_n_pdd6 { | |
1238 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1239 | nvidia,function = "pe1"; | |
fb816641 SW |
1240 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1241 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1242 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1243 | }; | |
15e524a4 SW |
1244 | clk3_out_pee0 { |
1245 | nvidia,pins = "clk3_out_pee0"; | |
1246 | nvidia,function = "extperiph3"; | |
1247 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1248 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1249 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1250 | }; | |
1251 | clk3_req_pee1 { | |
1252 | nvidia,pins = "clk3_req_pee1"; | |
1253 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1254 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1255 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1256 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1257 | }; | |
1258 | dap_mclk1_req_pee2 { | |
1259 | nvidia,pins = "dap_mclk1_req_pee2"; | |
15e524a4 SW |
1260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1263 | }; | |
1264 | hdmi_cec_pee3 { | |
1265 | nvidia,pins = "hdmi_cec_pee3"; | |
1266 | nvidia,function = "cec"; | |
1267 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1268 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1269 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 1270 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
1271 | }; |
1272 | sdmmc3_clk_lb_out_pee4 { | |
1273 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1274 | nvidia,function = "sdmmc3"; | |
1275 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1276 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1277 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1278 | }; | |
1279 | sdmmc3_clk_lb_in_pee5 { | |
1280 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1281 | nvidia,function = "sdmmc3"; | |
1282 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1284 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1285 | }; | |
1286 | dp_hpd_pff0 { | |
1287 | nvidia,pins = "dp_hpd_pff0"; | |
1288 | nvidia,function = "dp"; | |
fb816641 SW |
1289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1290 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1291 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1292 | }; | |
1293 | usb_vbus_en2_pff1 { | |
1294 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1295 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1296 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1297 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1298 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1299 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1300 | }; | |
1301 | pff2 { | |
1302 | nvidia,pins = "pff2"; | |
1303 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1304 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1305 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1306 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1307 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
1308 | }; | |
1309 | core_pwr_req { | |
1310 | nvidia,pins = "core_pwr_req"; | |
1311 | nvidia,function = "pwron"; | |
1312 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1313 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1314 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1315 | }; | |
1316 | cpu_pwr_req { | |
1317 | nvidia,pins = "cpu_pwr_req"; | |
fb816641 | 1318 | nvidia,function = "cpu"; |
15e524a4 SW |
1319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1321 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1322 | }; | |
1323 | pwr_int_n { | |
1324 | nvidia,pins = "pwr_int_n"; | |
1325 | nvidia,function = "pmi"; | |
1326 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 1327 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1328 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1329 | }; | |
1330 | reset_out_n { | |
1331 | nvidia,pins = "reset_out_n"; | |
1332 | nvidia,function = "reset_out_n"; | |
1333 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1334 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 1335 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1336 | }; |
1337 | owr { | |
1338 | nvidia,pins = "owr"; | |
1339 | nvidia,function = "rsvd2"; | |
1340 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1341 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1342 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1343 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
1344 | }; | |
1345 | clk_32k_in { | |
1346 | nvidia,pins = "clk_32k_in"; | |
fb816641 | 1347 | nvidia,function = "clk"; |
15e524a4 | 1348 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 | 1349 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1350 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1351 | }; | |
1352 | jtag_rtck { | |
1353 | nvidia,pins = "jtag_rtck"; | |
1354 | nvidia,function = "rtck"; | |
1355 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1356 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1357 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1358 | }; | |
1359 | }; | |
1360 | }; | |
1361 | ||
1362 | /* DB9 serial port */ | |
1363 | serial@0,70006300 { | |
1364 | status = "okay"; | |
1365 | }; | |
1366 | ||
1367 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ | |
1368 | i2c@0,7000c000 { | |
1369 | status = "okay"; | |
1370 | clock-frequency = <100000>; | |
1371 | ||
98de744e SW |
1372 | rt5639: audio-codec@1c { |
1373 | compatible = "realtek,rt5639"; | |
15e524a4 SW |
1374 | reg = <0x1c>; |
1375 | interrupt-parent = <&gpio>; | |
1376 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
1377 | realtek,ldo1-en-gpios = | |
1378 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; | |
1379 | }; | |
1380 | ||
1381 | temperature-sensor@4c { | |
1382 | compatible = "ti,tmp451"; | |
1383 | reg = <0x4c>; | |
1384 | interrupt-parent = <&gpio>; | |
1385 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | |
1386 | }; | |
1387 | ||
1388 | eeprom@56 { | |
1389 | compatible = "atmel,24c02"; | |
1390 | reg = <0x56>; | |
1391 | pagesize = <8>; | |
1392 | }; | |
1393 | }; | |
1394 | ||
1395 | /* Expansion GEN2_I2C_* */ | |
1396 | i2c@0,7000c400 { | |
1397 | status = "okay"; | |
1398 | clock-frequency = <100000>; | |
1399 | }; | |
1400 | ||
1401 | /* Expansion CAM_I2C_* */ | |
1402 | i2c@0,7000c500 { | |
1403 | status = "okay"; | |
1404 | clock-frequency = <100000>; | |
1405 | }; | |
1406 | ||
1407 | /* HDMI DDC */ | |
6054dd39 | 1408 | hdmi_ddc: i2c@0,7000c700 { |
15e524a4 SW |
1409 | status = "okay"; |
1410 | clock-frequency = <100000>; | |
1411 | }; | |
1412 | ||
1413 | /* Expansion PWR_I2C_*, on-board components */ | |
1414 | i2c@0,7000d000 { | |
1415 | status = "okay"; | |
1416 | clock-frequency = <400000>; | |
1417 | ||
1418 | pmic: pmic@40 { | |
1419 | compatible = "ams,as3722"; | |
1420 | reg = <0x40>; | |
1421 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
1422 | ||
1423 | ams,system-power-controller; | |
1424 | ||
1425 | #interrupt-cells = <2>; | |
1426 | interrupt-controller; | |
1427 | ||
1428 | gpio-controller; | |
1429 | #gpio-cells = <2>; | |
1430 | ||
1431 | pinctrl-names = "default"; | |
1432 | pinctrl-0 = <&as3722_default>; | |
1433 | ||
1434 | as3722_default: pinmux { | |
1435 | gpio0 { | |
1436 | pins = "gpio0"; | |
1437 | function = "gpio"; | |
1438 | bias-pull-down; | |
1439 | }; | |
1440 | ||
1441 | gpio1_2_4_7 { | |
1442 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
1443 | function = "gpio"; | |
1444 | bias-pull-up; | |
1445 | }; | |
1446 | ||
1447 | gpio3_5_6 { | |
1448 | pins = "gpio3", "gpio5", "gpio6"; | |
1449 | bias-high-impedance; | |
1450 | }; | |
1451 | }; | |
22b35776 SW |
1452 | |
1453 | regulators { | |
1454 | vsup-sd2-supply = <&vdd_5v0_sys>; | |
1455 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
1456 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
1457 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
1458 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
1459 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
1460 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
1461 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
1462 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
1463 | vin-ldo11-supply = <&vdd_3v3_run>; | |
1464 | ||
9be1e477 | 1465 | vdd_cpu: sd0 { |
22b35776 SW |
1466 | regulator-name = "+VDD_CPU_AP"; |
1467 | regulator-min-microvolt = <700000>; | |
1468 | regulator-max-microvolt = <1400000>; | |
1469 | regulator-min-microamp = <3500000>; | |
1470 | regulator-max-microamp = <3500000>; | |
1471 | regulator-always-on; | |
1472 | regulator-boot-on; | |
ee913f7a | 1473 | ams,ext-control = <2>; |
22b35776 SW |
1474 | }; |
1475 | ||
1476 | sd1 { | |
1477 | regulator-name = "+VDD_CORE"; | |
1478 | regulator-min-microvolt = <700000>; | |
1479 | regulator-max-microvolt = <1350000>; | |
1480 | regulator-min-microamp = <2500000>; | |
1481 | regulator-max-microamp = <2500000>; | |
1482 | regulator-always-on; | |
1483 | regulator-boot-on; | |
ee913f7a | 1484 | ams,ext-control = <1>; |
22b35776 SW |
1485 | }; |
1486 | ||
1487 | vdd_1v35_lp0: sd2 { | |
1488 | regulator-name = "+1.35V_LP0(sd2)"; | |
1489 | regulator-min-microvolt = <1350000>; | |
1490 | regulator-max-microvolt = <1350000>; | |
1491 | regulator-always-on; | |
1492 | regulator-boot-on; | |
1493 | }; | |
1494 | ||
1495 | sd3 { | |
1496 | regulator-name = "+1.35V_LP0(sd3)"; | |
1497 | regulator-min-microvolt = <1350000>; | |
1498 | regulator-max-microvolt = <1350000>; | |
1499 | regulator-always-on; | |
1500 | regulator-boot-on; | |
1501 | }; | |
1502 | ||
6054dd39 | 1503 | vdd_1v05_run: sd4 { |
22b35776 SW |
1504 | regulator-name = "+1.05V_RUN"; |
1505 | regulator-min-microvolt = <1050000>; | |
1506 | regulator-max-microvolt = <1050000>; | |
1507 | }; | |
1508 | ||
1509 | vddio_1v8: sd5 { | |
1510 | regulator-name = "+1.8V_VDDIO"; | |
1511 | regulator-min-microvolt = <1800000>; | |
1512 | regulator-max-microvolt = <1800000>; | |
1513 | regulator-boot-on; | |
1514 | regulator-always-on; | |
1515 | }; | |
1516 | ||
1517 | sd6 { | |
1518 | regulator-name = "+VDD_GPU_AP"; | |
1519 | regulator-min-microvolt = <650000>; | |
1520 | regulator-max-microvolt = <1200000>; | |
1521 | regulator-min-microamp = <3500000>; | |
1522 | regulator-max-microamp = <3500000>; | |
1523 | regulator-boot-on; | |
1524 | regulator-always-on; | |
1525 | }; | |
1526 | ||
8e2b9e4d | 1527 | avdd_1v05_run: ldo0 { |
22b35776 SW |
1528 | regulator-name = "+1.05V_RUN_AVDD"; |
1529 | regulator-min-microvolt = <1050000>; | |
1530 | regulator-max-microvolt = <1050000>; | |
1531 | regulator-boot-on; | |
1532 | regulator-always-on; | |
ee913f7a | 1533 | ams,ext-control = <1>; |
22b35776 SW |
1534 | }; |
1535 | ||
1536 | ldo1 { | |
1537 | regulator-name = "+1.8V_RUN_CAM"; | |
1538 | regulator-min-microvolt = <1800000>; | |
1539 | regulator-max-microvolt = <1800000>; | |
1540 | }; | |
1541 | ||
1542 | ldo2 { | |
1543 | regulator-name = "+1.2V_GEN_AVDD"; | |
1544 | regulator-min-microvolt = <1200000>; | |
1545 | regulator-max-microvolt = <1200000>; | |
1546 | regulator-boot-on; | |
1547 | regulator-always-on; | |
1548 | }; | |
1549 | ||
1550 | ldo3 { | |
1551 | regulator-name = "+1.05V_LP0_VDD_RTC"; | |
1552 | regulator-min-microvolt = <1000000>; | |
1553 | regulator-max-microvolt = <1000000>; | |
1554 | regulator-boot-on; | |
1555 | regulator-always-on; | |
1556 | ams,enable-tracking; | |
1557 | }; | |
1558 | ||
1559 | ldo4 { | |
1560 | regulator-name = "+2.8V_RUN_CAM"; | |
1561 | regulator-min-microvolt = <2800000>; | |
1562 | regulator-max-microvolt = <2800000>; | |
1563 | }; | |
1564 | ||
1565 | ldo5 { | |
1566 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | |
1567 | regulator-min-microvolt = <1200000>; | |
1568 | regulator-max-microvolt = <1200000>; | |
1569 | }; | |
1570 | ||
1571 | vddio_sdmmc3: ldo6 { | |
1572 | regulator-name = "+VDDIO_SDMMC3"; | |
1573 | regulator-min-microvolt = <1800000>; | |
1574 | regulator-max-microvolt = <3300000>; | |
1575 | }; | |
1576 | ||
1577 | ldo7 { | |
1578 | regulator-name = "+1.05V_RUN_CAM_REAR"; | |
1579 | regulator-min-microvolt = <1050000>; | |
1580 | regulator-max-microvolt = <1050000>; | |
1581 | }; | |
1582 | ||
1583 | ldo9 { | |
1584 | regulator-name = "+3.3V_RUN_TOUCH"; | |
1585 | regulator-min-microvolt = <2800000>; | |
1586 | regulator-max-microvolt = <2800000>; | |
1587 | }; | |
1588 | ||
1589 | ldo10 { | |
1590 | regulator-name = "+2.8V_RUN_CAM_AF"; | |
1591 | regulator-min-microvolt = <2800000>; | |
1592 | regulator-max-microvolt = <2800000>; | |
1593 | }; | |
1594 | ||
1595 | ldo11 { | |
1596 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | |
1597 | regulator-min-microvolt = <1800000>; | |
1598 | regulator-max-microvolt = <1800000>; | |
1599 | }; | |
1600 | }; | |
15e524a4 SW |
1601 | }; |
1602 | }; | |
1603 | ||
1604 | /* Expansion TS_SPI_* */ | |
1605 | spi@0,7000d400 { | |
1606 | status = "okay"; | |
1607 | }; | |
1608 | ||
1609 | /* Internal SPI */ | |
1610 | spi@0,7000da00 { | |
1611 | status = "okay"; | |
1612 | spi-max-frequency = <25000000>; | |
1613 | spi-flash@0 { | |
1614 | compatible = "winbond,w25q32dw"; | |
1615 | reg = <0>; | |
1616 | spi-max-frequency = <20000000>; | |
1617 | }; | |
1618 | }; | |
1619 | ||
1620 | pmc@0,7000e400 { | |
1621 | nvidia,invert-interrupt; | |
1622 | nvidia,suspend-mode = <1>; | |
1623 | nvidia,cpu-pwr-good-time = <500>; | |
1624 | nvidia,cpu-pwr-off-time = <300>; | |
1625 | nvidia,core-pwr-good-time = <641 3845>; | |
1626 | nvidia,core-pwr-off-time = <61036>; | |
1627 | nvidia,core-power-req-active-high; | |
1628 | nvidia,sys-clock-req-active-high; | |
9c963301 MP |
1629 | |
1630 | i2c-thermtrip { | |
1631 | nvidia,i2c-controller-id = <4>; | |
1632 | nvidia,bus-addr = <0x40>; | |
1633 | nvidia,reg-addr = <0x36>; | |
1634 | nvidia,reg-data = <0x2>; | |
1635 | }; | |
15e524a4 SW |
1636 | }; |
1637 | ||
1b3ce99f MP |
1638 | /* Serial ATA */ |
1639 | sata@0,70020000 { | |
1640 | status = "okay"; | |
1641 | ||
1642 | hvdd-supply = <&vdd_3v3_lp0>; | |
1643 | vddio-supply = <&vdd_1v05_run>; | |
1644 | avdd-supply = <&vdd_1v05_run>; | |
1645 | ||
1646 | target-5v-supply = <&vdd_5v0_sata>; | |
1647 | target-12v-supply = <&vdd_12v0_sata>; | |
1648 | }; | |
1649 | ||
4c84472e TR |
1650 | hda@0,70030000 { |
1651 | status = "okay"; | |
1652 | }; | |
1653 | ||
62b8db08 TR |
1654 | padctl@0,7009f000 { |
1655 | pinctrl-0 = <&padctl_default>; | |
1656 | pinctrl-names = "default"; | |
1657 | ||
1658 | padctl_default: pinmux { | |
1659 | usb3 { | |
1660 | nvidia,lanes = "pcie-0", "pcie-1"; | |
1661 | nvidia,function = "usb3"; | |
1662 | nvidia,iddq = <0>; | |
1663 | }; | |
1664 | ||
1665 | pcie { | |
1666 | nvidia,lanes = "pcie-2", "pcie-3", | |
1667 | "pcie-4"; | |
1668 | nvidia,function = "pcie"; | |
1669 | nvidia,iddq = <0>; | |
1670 | }; | |
1671 | ||
1672 | sata { | |
1673 | nvidia,lanes = "sata-0"; | |
1674 | nvidia,function = "sata"; | |
1675 | nvidia,iddq = <0>; | |
1676 | }; | |
1677 | }; | |
1678 | }; | |
1679 | ||
15e524a4 SW |
1680 | /* SD card */ |
1681 | sdhci@0,700b0400 { | |
1682 | status = "okay"; | |
1683 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
1684 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
215f21c9 | 1685 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
15e524a4 | 1686 | bus-width = <4>; |
9260764c | 1687 | vqmmc-supply = <&vddio_sdmmc3>; |
15e524a4 SW |
1688 | }; |
1689 | ||
1690 | /* eMMC */ | |
1691 | sdhci@0,700b0600 { | |
1692 | status = "okay"; | |
1693 | bus-width = <8>; | |
33f34f0c | 1694 | non-removable; |
15e524a4 SW |
1695 | }; |
1696 | ||
9be1e477 TT |
1697 | /* CPU DFLL clock */ |
1698 | clock@0,70110000 { | |
1699 | status = "okay"; | |
1700 | vdd-cpu-supply = <&vdd_cpu>; | |
1701 | nvidia,i2c-fs-rate = <400000>; | |
1702 | }; | |
1703 | ||
15e524a4 SW |
1704 | ahub@0,70300000 { |
1705 | i2s@0,70301100 { | |
1706 | status = "okay"; | |
1707 | }; | |
1708 | }; | |
1709 | ||
1710 | /* mini-PCIe USB */ | |
1711 | usb@0,7d004000 { | |
1712 | status = "okay"; | |
1713 | }; | |
1714 | ||
1715 | usb-phy@0,7d004000 { | |
1716 | status = "okay"; | |
1717 | }; | |
1718 | ||
1719 | /* USB A connector */ | |
1720 | usb@0,7d008000 { | |
1721 | status = "okay"; | |
1722 | }; | |
1723 | ||
1724 | usb-phy@0,7d008000 { | |
1725 | status = "okay"; | |
1726 | vbus-supply = <&vdd_usb3_vbus>; | |
1727 | }; | |
1728 | ||
1729 | clocks { | |
1730 | compatible = "simple-bus"; | |
1731 | #address-cells = <1>; | |
1732 | #size-cells = <0>; | |
1733 | ||
1734 | clk32k_in: clock@0 { | |
1735 | compatible = "fixed-clock"; | |
1736 | reg = <0>; | |
1737 | #clock-cells = <0>; | |
1738 | clock-frequency = <32768>; | |
1739 | }; | |
1740 | }; | |
1741 | ||
1742 | gpio-keys { | |
1743 | compatible = "gpio-keys"; | |
1744 | ||
1745 | power { | |
1746 | label = "Power"; | |
1747 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1748 | linux,code = <KEY_POWER>; | |
1749 | debounce-interval = <10>; | |
1750 | gpio-key,wakeup; | |
1751 | }; | |
1752 | }; | |
1753 | ||
1754 | regulators { | |
1755 | compatible = "simple-bus"; | |
1756 | #address-cells = <1>; | |
1757 | #size-cells = <0>; | |
1758 | ||
22b35776 SW |
1759 | vdd_mux: regulator@0 { |
1760 | compatible = "regulator-fixed"; | |
1761 | reg = <0>; | |
1762 | regulator-name = "+VDD_MUX"; | |
1763 | regulator-min-microvolt = <12000000>; | |
1764 | regulator-max-microvolt = <12000000>; | |
1765 | regulator-always-on; | |
1766 | regulator-boot-on; | |
1767 | }; | |
1768 | ||
1769 | vdd_5v0_sys: regulator@1 { | |
1770 | compatible = "regulator-fixed"; | |
1771 | reg = <1>; | |
1772 | regulator-name = "+5V_SYS"; | |
1773 | regulator-min-microvolt = <5000000>; | |
1774 | regulator-max-microvolt = <5000000>; | |
1775 | regulator-always-on; | |
1776 | regulator-boot-on; | |
1777 | vin-supply = <&vdd_mux>; | |
1778 | }; | |
1779 | ||
1780 | vdd_3v3_sys: regulator@2 { | |
1781 | compatible = "regulator-fixed"; | |
1782 | reg = <2>; | |
1783 | regulator-name = "+3.3V_SYS"; | |
1784 | regulator-min-microvolt = <3300000>; | |
1785 | regulator-max-microvolt = <3300000>; | |
1786 | regulator-always-on; | |
1787 | regulator-boot-on; | |
1788 | vin-supply = <&vdd_mux>; | |
1789 | }; | |
1790 | ||
1791 | vdd_3v3_run: regulator@3 { | |
1792 | compatible = "regulator-fixed"; | |
1793 | reg = <3>; | |
1794 | regulator-name = "+3.3V_RUN"; | |
1795 | regulator-min-microvolt = <3300000>; | |
1796 | regulator-max-microvolt = <3300000>; | |
1797 | regulator-always-on; | |
1798 | regulator-boot-on; | |
1799 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | |
1800 | enable-active-high; | |
1801 | vin-supply = <&vdd_3v3_sys>; | |
1802 | }; | |
1803 | ||
1804 | vdd_3v3_hdmi: regulator@4 { | |
1805 | compatible = "regulator-fixed"; | |
1806 | reg = <4>; | |
1807 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | |
1808 | regulator-min-microvolt = <3300000>; | |
1809 | regulator-max-microvolt = <3300000>; | |
1810 | vin-supply = <&vdd_3v3_run>; | |
1811 | }; | |
1812 | ||
1813 | vdd_usb1_vbus: regulator@7 { | |
1814 | compatible = "regulator-fixed"; | |
1815 | reg = <7>; | |
1816 | regulator-name = "+USB0_VBUS_SW"; | |
1817 | regulator-min-microvolt = <5000000>; | |
1818 | regulator-max-microvolt = <5000000>; | |
1819 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
1820 | enable-active-high; | |
1821 | gpio-open-drain; | |
1822 | vin-supply = <&vdd_5v0_sys>; | |
1823 | }; | |
1824 | ||
15e524a4 SW |
1825 | vdd_usb3_vbus: regulator@8 { |
1826 | compatible = "regulator-fixed"; | |
1827 | reg = <8>; | |
1828 | regulator-name = "+5V_USB_HS"; | |
1829 | regulator-min-microvolt = <5000000>; | |
1830 | regulator-max-microvolt = <5000000>; | |
1831 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1832 | enable-active-high; | |
1833 | gpio-open-drain; | |
22b35776 SW |
1834 | vin-supply = <&vdd_5v0_sys>; |
1835 | }; | |
1836 | ||
1837 | vdd_3v3_lp0: regulator@10 { | |
1838 | compatible = "regulator-fixed"; | |
1839 | reg = <10>; | |
1840 | regulator-name = "+3.3V_LP0"; | |
1841 | regulator-min-microvolt = <3300000>; | |
1842 | regulator-max-microvolt = <3300000>; | |
1843 | regulator-always-on; | |
1844 | regulator-boot-on; | |
1845 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | |
1846 | enable-active-high; | |
1847 | vin-supply = <&vdd_3v3_sys>; | |
15e524a4 | 1848 | }; |
6054dd39 TR |
1849 | |
1850 | vdd_hdmi_pll: regulator@11 { | |
1851 | compatible = "regulator-fixed"; | |
1852 | reg = <11>; | |
1853 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1854 | regulator-min-microvolt = <1050000>; | |
1855 | regulator-max-microvolt = <1050000>; | |
1856 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1857 | vin-supply = <&vdd_1v05_run>; | |
1858 | }; | |
1859 | ||
1860 | vdd_5v0_hdmi: regulator@12 { | |
1861 | compatible = "regulator-fixed"; | |
1862 | reg = <12>; | |
1863 | regulator-name = "+5V_HDMI_CON"; | |
1864 | regulator-min-microvolt = <5000000>; | |
1865 | regulator-max-microvolt = <5000000>; | |
1866 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1867 | enable-active-high; | |
1868 | vin-supply = <&vdd_5v0_sys>; | |
1869 | }; | |
1b3ce99f MP |
1870 | |
1871 | /* Molex power connector */ | |
1872 | vdd_5v0_sata: regulator@13 { | |
1873 | compatible = "regulator-fixed"; | |
1874 | reg = <13>; | |
1875 | regulator-name = "+5V_SATA"; | |
1876 | regulator-min-microvolt = <5000000>; | |
1877 | regulator-max-microvolt = <5000000>; | |
1878 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
1879 | enable-active-high; | |
1880 | vin-supply = <&vdd_5v0_sys>; | |
1881 | }; | |
1882 | ||
1883 | vdd_12v0_sata: regulator@14 { | |
1884 | compatible = "regulator-fixed"; | |
1885 | reg = <14>; | |
1886 | regulator-name = "+12V_SATA"; | |
1887 | regulator-min-microvolt = <12000000>; | |
1888 | regulator-max-microvolt = <12000000>; | |
1889 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
1890 | enable-active-high; | |
1891 | vin-supply = <&vdd_mux>; | |
1892 | }; | |
15e524a4 SW |
1893 | }; |
1894 | ||
1895 | sound { | |
1896 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", | |
1897 | "nvidia,tegra-audio-rt5640"; | |
1898 | nvidia,model = "NVIDIA Tegra Jetson TK1"; | |
1899 | ||
1900 | nvidia,audio-routing = | |
1901 | "Headphones", "HPOR", | |
1902 | "Headphones", "HPOL", | |
1903 | "Mic Jack", "MICBIAS1", | |
1904 | "IN2P", "Mic Jack"; | |
1905 | ||
1906 | nvidia,i2s-controller = <&tegra_i2s1>; | |
98de744e | 1907 | nvidia,audio-codec = <&rt5639>; |
15e524a4 SW |
1908 | |
1909 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | |
1910 | ||
1911 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
1912 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
1913 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
1914 | clock-names = "pll_a", "pll_a_out0", "mclk"; | |
1915 | }; | |
ed7eac33 MP |
1916 | |
1917 | thermal-zones { | |
1918 | cpu { | |
1919 | trips { | |
1920 | trip@0 { | |
1921 | temperature = <101000>; | |
1922 | hysteresis = <0>; | |
1923 | type = "critical"; | |
1924 | }; | |
1925 | }; | |
1926 | ||
1927 | cooling-maps { | |
1928 | /* There are currently no cooling maps because there are no cooling devices */ | |
1929 | }; | |
1930 | }; | |
1931 | ||
1932 | mem { | |
1933 | trips { | |
1934 | trip@0 { | |
1935 | temperature = <101000>; | |
1936 | hysteresis = <0>; | |
1937 | type = "critical"; | |
1938 | }; | |
1939 | }; | |
1940 | ||
1941 | cooling-maps { | |
1942 | /* There are currently no cooling maps because there are no cooling devices */ | |
1943 | }; | |
1944 | }; | |
1945 | ||
1946 | gpu { | |
1947 | trips { | |
1948 | trip@0 { | |
1949 | temperature = <101000>; | |
1950 | hysteresis = <0>; | |
1951 | type = "critical"; | |
1952 | }; | |
1953 | }; | |
1954 | ||
1955 | cooling-maps { | |
1956 | /* There are currently no cooling maps because there are no cooling devices */ | |
1957 | }; | |
1958 | }; | |
1959 | }; | |
15e524a4 | 1960 | }; |