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Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
15e524a4 SW |
2 | /dts-v1/; |
3 | ||
4 | #include <dt-bindings/input/input.h> | |
5 | #include "tegra124.dtsi" | |
6 | ||
6e72cf00 MP |
7 | #include "tegra124-jetson-tk1-emc.dtsi" |
8 | ||
15e524a4 SW |
9 | / { |
10 | model = "NVIDIA Tegra124 Jetson TK1"; | |
11 | compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; | |
12 | ||
13 | aliases { | |
b5896f67 MZ |
14 | rtc0 = "/i2c@7000d000/pmic@40"; |
15 | rtc1 = "/rtc@7000e000"; | |
c90bb7b9 RR |
16 | |
17 | /* This order keeps the mapping DB9 connector <-> ttyS0 */ | |
c4574aa0 | 18 | serial0 = &uartd; |
c90bb7b9 RR |
19 | serial1 = &uarta; |
20 | serial2 = &uartb; | |
15e524a4 SW |
21 | }; |
22 | ||
f5bbb327 JH |
23 | chosen { |
24 | stdout-path = "serial0:115200n8"; | |
25 | }; | |
26 | ||
48299769 | 27 | memory@80000000 { |
15e524a4 SW |
28 | reg = <0x0 0x80000000 0x0 0x80000000>; |
29 | }; | |
30 | ||
508d690e | 31 | pcie@1003000 { |
8e2b9e4d TR |
32 | status = "okay"; |
33 | ||
34 | avddio-pex-supply = <&vdd_1v05_run>; | |
35 | dvddio-pex-supply = <&vdd_1v05_run>; | |
36 | avdd-pex-pll-supply = <&vdd_1v05_run>; | |
37 | hvdd-pex-supply = <&vdd_3v3_lp0>; | |
38 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; | |
39 | vddio-pex-ctl-supply = <&vdd_3v3_lp0>; | |
40 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
41 | ||
87c68119 | 42 | /* Mini PCIe */ |
8e2b9e4d | 43 | pci@1,0 { |
b5896f67 | 44 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; |
87c68119 | 45 | phy-names = "pcie-0"; |
8e2b9e4d TR |
46 | status = "okay"; |
47 | }; | |
48 | ||
87c68119 | 49 | /* Gigabit Ethernet */ |
8e2b9e4d | 50 | pci@2,0 { |
b5896f67 | 51 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; |
87c68119 | 52 | phy-names = "pcie-0"; |
8e2b9e4d TR |
53 | status = "okay"; |
54 | }; | |
55 | }; | |
56 | ||
b5896f67 MZ |
57 | host1x@50000000 { |
58 | hdmi@54280000 { | |
6054dd39 TR |
59 | status = "okay"; |
60 | ||
61 | hdmi-supply = <&vdd_5v0_hdmi>; | |
62 | pll-supply = <&vdd_hdmi_pll>; | |
63 | vdd-supply = <&vdd_3v3_hdmi>; | |
64 | ||
65 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
66 | nvidia,hpd-gpio = | |
67 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
68 | }; | |
69 | }; | |
70 | ||
33dfb1e1 HV |
71 | cec@70015000 { |
72 | status = "okay"; | |
73 | }; | |
74 | ||
21fa196f AC |
75 | gpu@0,57000000 { |
76 | /* | |
77 | * Node left disabled on purpose - the bootloader will enable | |
78 | * it after having set the VPR up | |
79 | */ | |
80 | vdd-supply = <&vdd_gpu>; | |
81 | }; | |
82 | ||
b5896f67 | 83 | pinmux: pinmux@70000868 { |
6dbaff2b SW |
84 | pinctrl-names = "boot"; |
85 | pinctrl-0 = <&state_boot>; | |
15e524a4 | 86 | |
6dbaff2b | 87 | state_boot: pinmux { |
15e524a4 SW |
88 | clk_32k_out_pa0 { |
89 | nvidia,pins = "clk_32k_out_pa0"; | |
90 | nvidia,function = "soc"; | |
91 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 92 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
93 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
94 | }; | |
95 | uart3_cts_n_pa1 { | |
96 | nvidia,pins = "uart3_cts_n_pa1"; | |
fb816641 SW |
97 | nvidia,function = "gmi"; |
98 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
99 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
100 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
101 | }; |
102 | dap2_fs_pa2 { | |
103 | nvidia,pins = "dap2_fs_pa2"; | |
104 | nvidia,function = "i2s1"; | |
105 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
106 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 107 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
108 | }; |
109 | dap2_sclk_pa3 { | |
110 | nvidia,pins = "dap2_sclk_pa3"; | |
111 | nvidia,function = "i2s1"; | |
112 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
113 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 114 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
115 | }; |
116 | dap2_din_pa4 { | |
117 | nvidia,pins = "dap2_din_pa4"; | |
118 | nvidia,function = "i2s1"; | |
119 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 120 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
121 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
122 | }; | |
123 | dap2_dout_pa5 { | |
124 | nvidia,pins = "dap2_dout_pa5"; | |
125 | nvidia,function = "i2s1"; | |
126 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
127 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 128 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
129 | }; |
130 | sdmmc3_clk_pa6 { | |
131 | nvidia,pins = "sdmmc3_clk_pa6"; | |
132 | nvidia,function = "sdmmc3"; | |
133 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
134 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 135 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
136 | }; |
137 | sdmmc3_cmd_pa7 { | |
138 | nvidia,pins = "sdmmc3_cmd_pa7"; | |
139 | nvidia,function = "sdmmc3"; | |
140 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
143 | }; | |
144 | pb0 { | |
145 | nvidia,pins = "pb0"; | |
146 | nvidia,function = "uartd"; | |
147 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 148 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
150 | }; | |
151 | pb1 { | |
152 | nvidia,pins = "pb1"; | |
153 | nvidia,function = "uartd"; | |
154 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 155 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
157 | }; | |
158 | sdmmc3_dat3_pb4 { | |
159 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
160 | nvidia,function = "sdmmc3"; | |
161 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
162 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
163 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
164 | }; | |
165 | sdmmc3_dat2_pb5 { | |
166 | nvidia,pins = "sdmmc3_dat2_pb5"; | |
167 | nvidia,function = "sdmmc3"; | |
168 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
169 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
170 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
171 | }; | |
172 | sdmmc3_dat1_pb6 { | |
173 | nvidia,pins = "sdmmc3_dat1_pb6"; | |
174 | nvidia,function = "sdmmc3"; | |
175 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
176 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
177 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
178 | }; | |
179 | sdmmc3_dat0_pb7 { | |
180 | nvidia,pins = "sdmmc3_dat0_pb7"; | |
181 | nvidia,function = "sdmmc3"; | |
182 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
184 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
185 | }; | |
186 | uart3_rts_n_pc0 { | |
187 | nvidia,pins = "uart3_rts_n_pc0"; | |
fb816641 SW |
188 | nvidia,function = "gmi"; |
189 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
190 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
191 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
192 | }; | |
193 | uart2_txd_pc2 { | |
194 | nvidia,pins = "uart2_txd_pc2"; | |
195 | nvidia,function = "irda"; | |
196 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
197 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
198 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
199 | }; | |
200 | uart2_rxd_pc3 { | |
201 | nvidia,pins = "uart2_rxd_pc3"; | |
202 | nvidia,function = "irda"; | |
203 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 204 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
205 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
206 | }; | |
207 | gen1_i2c_scl_pc4 { | |
208 | nvidia,pins = "gen1_i2c_scl_pc4"; | |
209 | nvidia,function = "i2c1"; | |
210 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
212 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
213 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
214 | }; | |
215 | gen1_i2c_sda_pc5 { | |
216 | nvidia,pins = "gen1_i2c_sda_pc5"; | |
217 | nvidia,function = "i2c1"; | |
218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
220 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
221 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
222 | }; | |
223 | pc7 { | |
224 | nvidia,pins = "pc7"; | |
225 | nvidia,function = "rsvd1"; | |
fb816641 SW |
226 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
227 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
228 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
229 | }; |
230 | pg0 { | |
231 | nvidia,pins = "pg0"; | |
15e524a4 | 232 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
233 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
234 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
235 | }; |
236 | pg1 { | |
237 | nvidia,pins = "pg1"; | |
15e524a4 | 238 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
239 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
240 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
241 | }; |
242 | pg2 { | |
243 | nvidia,pins = "pg2"; | |
fb816641 SW |
244 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
245 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
247 | }; | |
248 | pg3 { | |
249 | nvidia,pins = "pg3"; | |
fb816641 SW |
250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
251 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
252 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
253 | }; | |
254 | pg4 { | |
255 | nvidia,pins = "pg4"; | |
15e524a4 | 256 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
257 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
258 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
259 | }; |
260 | pg5 { | |
261 | nvidia,pins = "pg5"; | |
262 | nvidia,function = "spi4"; | |
263 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
264 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
265 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
266 | }; | |
267 | pg6 { | |
268 | nvidia,pins = "pg6"; | |
269 | nvidia,function = "spi4"; | |
270 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
271 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
272 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
273 | }; | |
274 | pg7 { | |
275 | nvidia,pins = "pg7"; | |
276 | nvidia,function = "spi4"; | |
277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
fb816641 | 278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
279 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
280 | }; | |
281 | ph0 { | |
282 | nvidia,pins = "ph0"; | |
283 | nvidia,function = "gmi"; | |
284 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
285 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
286 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
287 | }; | |
288 | ph1 { | |
289 | nvidia,pins = "ph1"; | |
290 | nvidia,function = "pwm1"; | |
291 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
292 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
293 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
294 | }; | |
295 | ph2 { | |
296 | nvidia,pins = "ph2"; | |
15e524a4 SW |
297 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
299 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
300 | }; | |
301 | ph3 { | |
302 | nvidia,pins = "ph3"; | |
303 | nvidia,function = "gmi"; | |
fb816641 SW |
304 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
305 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
306 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
307 | }; | |
308 | ph4 { | |
309 | nvidia,pins = "ph4"; | |
fb816641 SW |
310 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
311 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
312 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
313 | }; | |
314 | ph5 { | |
315 | nvidia,pins = "ph5"; | |
316 | nvidia,function = "rsvd2"; | |
fb816641 SW |
317 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
318 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
319 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
320 | }; | |
321 | ph6 { | |
322 | nvidia,pins = "ph6"; | |
323 | nvidia,function = "gmi"; | |
fb816641 SW |
324 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
325 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
326 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
327 | }; |
328 | ph7 { | |
329 | nvidia,pins = "ph7"; | |
15e524a4 SW |
330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
333 | }; |
334 | pi0 { | |
335 | nvidia,pins = "pi0"; | |
15e524a4 SW |
336 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
337 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
338 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
339 | }; | |
340 | pi1 { | |
341 | nvidia,pins = "pi1"; | |
fb816641 | 342 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 343 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 344 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
345 | }; |
346 | pi2 { | |
347 | nvidia,pins = "pi2"; | |
348 | nvidia,function = "rsvd4"; | |
fb816641 SW |
349 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
350 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
351 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
352 | }; | |
353 | pi3 { | |
354 | nvidia,pins = "pi3"; | |
355 | nvidia,function = "spi4"; | |
356 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
357 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
358 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
359 | }; | |
360 | pi4 { | |
361 | nvidia,pins = "pi4"; | |
362 | nvidia,function = "gmi"; | |
fb816641 SW |
363 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
364 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
366 | }; | |
367 | pi5 { | |
368 | nvidia,pins = "pi5"; | |
369 | nvidia,function = "rsvd2"; | |
fb816641 SW |
370 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
371 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
372 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
373 | }; |
374 | pi6 { | |
375 | nvidia,pins = "pi6"; | |
fb816641 SW |
376 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
377 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
378 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
379 | }; | |
380 | pi7 { | |
381 | nvidia,pins = "pi7"; | |
382 | nvidia,function = "rsvd1"; | |
383 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
384 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
385 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
386 | }; | |
387 | pj0 { | |
388 | nvidia,pins = "pj0"; | |
fb816641 SW |
389 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
390 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
391 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
392 | }; | |
393 | pj2 { | |
394 | nvidia,pins = "pj2"; | |
395 | nvidia,function = "rsvd1"; | |
fb816641 SW |
396 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
397 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
398 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
399 | }; |
400 | uart2_cts_n_pj5 { | |
401 | nvidia,pins = "uart2_cts_n_pj5"; | |
402 | nvidia,function = "uartb"; | |
403 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 404 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
405 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
406 | }; | |
407 | uart2_rts_n_pj6 { | |
408 | nvidia,pins = "uart2_rts_n_pj6"; | |
409 | nvidia,function = "uartb"; | |
410 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
411 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
412 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
413 | }; | |
414 | pj7 { | |
415 | nvidia,pins = "pj7"; | |
416 | nvidia,function = "uartd"; | |
417 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
418 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
419 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
420 | }; | |
421 | pk0 { | |
422 | nvidia,pins = "pk0"; | |
fb816641 SW |
423 | nvidia,function = "rsvd1"; |
424 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
425 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
426 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
427 | }; |
428 | pk1 { | |
429 | nvidia,pins = "pk1"; | |
15e524a4 SW |
430 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
431 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
432 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
433 | }; | |
434 | pk2 { | |
435 | nvidia,pins = "pk2"; | |
fb816641 | 436 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
437 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
438 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
439 | }; | |
440 | pk3 { | |
441 | nvidia,pins = "pk3"; | |
442 | nvidia,function = "gmi"; | |
fb816641 SW |
443 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
444 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
445 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
446 | }; |
447 | pk4 { | |
448 | nvidia,pins = "pk4"; | |
15e524a4 SW |
449 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
451 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
452 | }; | |
453 | spdif_out_pk5 { | |
454 | nvidia,pins = "spdif_out_pk5"; | |
455 | nvidia,function = "rsvd2"; | |
fb816641 SW |
456 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
457 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
458 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
459 | }; | |
460 | spdif_in_pk6 { | |
461 | nvidia,pins = "spdif_in_pk6"; | |
15e524a4 SW |
462 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
463 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
464 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
465 | }; | |
466 | pk7 { | |
467 | nvidia,pins = "pk7"; | |
468 | nvidia,function = "uartd"; | |
469 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
470 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
471 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
472 | }; | |
473 | dap1_fs_pn0 { | |
474 | nvidia,pins = "dap1_fs_pn0"; | |
fb816641 | 475 | nvidia,function = "rsvd4"; |
15e524a4 | 476 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
477 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
478 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
479 | }; |
480 | dap1_din_pn1 { | |
481 | nvidia,pins = "dap1_din_pn1"; | |
fb816641 | 482 | nvidia,function = "rsvd4"; |
15e524a4 | 483 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
484 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
485 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
486 | }; |
487 | dap1_dout_pn2 { | |
488 | nvidia,pins = "dap1_dout_pn2"; | |
489 | nvidia,function = "sata"; | |
490 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
491 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
492 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
493 | }; | |
494 | dap1_sclk_pn3 { | |
495 | nvidia,pins = "dap1_sclk_pn3"; | |
fb816641 | 496 | nvidia,function = "rsvd4"; |
15e524a4 | 497 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
498 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
499 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
500 | }; |
501 | usb_vbus_en0_pn4 { | |
502 | nvidia,pins = "usb_vbus_en0_pn4"; | |
503 | nvidia,function = "usb"; | |
fb816641 | 504 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
505 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
506 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 507 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
508 | }; |
509 | usb_vbus_en1_pn5 { | |
510 | nvidia,pins = "usb_vbus_en1_pn5"; | |
511 | nvidia,function = "usb"; | |
fb816641 | 512 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
513 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
514 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 515 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
516 | }; |
517 | hdmi_int_pn7 { | |
518 | nvidia,pins = "hdmi_int_pn7"; | |
15e524a4 | 519 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 | 520 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
521 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
522 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
523 | }; | |
524 | ulpi_data7_po0 { | |
525 | nvidia,pins = "ulpi_data7_po0"; | |
526 | nvidia,function = "ulpi"; | |
fb816641 SW |
527 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
528 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
529 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
530 | }; |
531 | ulpi_data0_po1 { | |
532 | nvidia,pins = "ulpi_data0_po1"; | |
fb816641 SW |
533 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
534 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
535 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
536 | }; | |
537 | ulpi_data1_po2 { | |
538 | nvidia,pins = "ulpi_data1_po2"; | |
539 | nvidia,function = "ulpi"; | |
fb816641 SW |
540 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
541 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
542 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
543 | }; |
544 | ulpi_data2_po3 { | |
545 | nvidia,pins = "ulpi_data2_po3"; | |
546 | nvidia,function = "ulpi"; | |
fb816641 SW |
547 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
548 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
549 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
550 | }; |
551 | ulpi_data3_po4 { | |
552 | nvidia,pins = "ulpi_data3_po4"; | |
fb816641 SW |
553 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
554 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
555 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
556 | }; | |
557 | ulpi_data4_po5 { | |
558 | nvidia,pins = "ulpi_data4_po5"; | |
559 | nvidia,function = "ulpi"; | |
fb816641 SW |
560 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
561 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
562 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
563 | }; |
564 | ulpi_data5_po6 { | |
565 | nvidia,pins = "ulpi_data5_po6"; | |
566 | nvidia,function = "ulpi"; | |
fb816641 SW |
567 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
568 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
569 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
570 | }; | |
571 | ulpi_data6_po7 { | |
572 | nvidia,pins = "ulpi_data6_po7"; | |
573 | nvidia,function = "ulpi"; | |
fb816641 SW |
574 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
575 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
576 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
577 | }; |
578 | dap3_fs_pp0 { | |
579 | nvidia,pins = "dap3_fs_pp0"; | |
580 | nvidia,function = "i2s2"; | |
fb816641 SW |
581 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
582 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
583 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
584 | }; | |
585 | dap3_din_pp1 { | |
586 | nvidia,pins = "dap3_din_pp1"; | |
587 | nvidia,function = "i2s2"; | |
fb816641 SW |
588 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
589 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
590 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
591 | }; | |
592 | dap3_dout_pp2 { | |
593 | nvidia,pins = "dap3_dout_pp2"; | |
15e524a4 SW |
594 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
595 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
596 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
597 | }; | |
598 | dap3_sclk_pp3 { | |
599 | nvidia,pins = "dap3_sclk_pp3"; | |
600 | nvidia,function = "rsvd3"; | |
601 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
602 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
603 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
604 | }; | |
605 | dap4_fs_pp4 { | |
606 | nvidia,pins = "dap4_fs_pp4"; | |
fb816641 | 607 | nvidia,function = "rsvd4"; |
15e524a4 | 608 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
609 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
610 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
611 | }; |
612 | dap4_din_pp5 { | |
613 | nvidia,pins = "dap4_din_pp5"; | |
fb816641 | 614 | nvidia,function = "rsvd3"; |
15e524a4 | 615 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
616 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
617 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
618 | }; |
619 | dap4_dout_pp6 { | |
620 | nvidia,pins = "dap4_dout_pp6"; | |
fb816641 | 621 | nvidia,function = "rsvd4"; |
15e524a4 | 622 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
623 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
624 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
625 | }; |
626 | dap4_sclk_pp7 { | |
627 | nvidia,pins = "dap4_sclk_pp7"; | |
fb816641 | 628 | nvidia,function = "rsvd3"; |
15e524a4 | 629 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
fb816641 SW |
630 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
631 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
632 | }; |
633 | kb_col0_pq0 { | |
634 | nvidia,pins = "kb_col0_pq0"; | |
15e524a4 | 635 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 636 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
637 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
638 | }; | |
639 | kb_col1_pq1 { | |
640 | nvidia,pins = "kb_col1_pq1"; | |
641 | nvidia,function = "rsvd2"; | |
fb816641 SW |
642 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
643 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
644 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
645 | }; |
646 | kb_col2_pq2 { | |
647 | nvidia,pins = "kb_col2_pq2"; | |
648 | nvidia,function = "rsvd2"; | |
fb816641 SW |
649 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
650 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
651 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
652 | }; |
653 | kb_col3_pq3 { | |
654 | nvidia,pins = "kb_col3_pq3"; | |
fb816641 | 655 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 | 656 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
fb816641 | 657 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
658 | }; |
659 | kb_col4_pq4 { | |
660 | nvidia,pins = "kb_col4_pq4"; | |
661 | nvidia,function = "sdmmc3"; | |
662 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 663 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
664 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
665 | }; | |
666 | kb_col5_pq5 { | |
667 | nvidia,pins = "kb_col5_pq5"; | |
fb816641 SW |
668 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
669 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
670 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
671 | }; | |
672 | kb_col6_pq6 { | |
673 | nvidia,pins = "kb_col6_pq6"; | |
674 | nvidia,function = "rsvd2"; | |
fb816641 SW |
675 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
676 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
677 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
678 | }; |
679 | kb_col7_pq7 { | |
680 | nvidia,pins = "kb_col7_pq7"; | |
fb816641 SW |
681 | nvidia,function = "rsvd2"; |
682 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
683 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
684 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
685 | }; |
686 | kb_row0_pr0 { | |
687 | nvidia,pins = "kb_row0_pr0"; | |
15e524a4 SW |
688 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
689 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
690 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
691 | }; | |
692 | kb_row1_pr1 { | |
693 | nvidia,pins = "kb_row1_pr1"; | |
694 | nvidia,function = "rsvd2"; | |
fb816641 SW |
695 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
696 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
697 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
698 | }; | |
699 | kb_row2_pr2 { | |
700 | nvidia,pins = "kb_row2_pr2"; | |
15e524a4 SW |
701 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
702 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
703 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
704 | }; | |
705 | kb_row3_pr3 { | |
706 | nvidia,pins = "kb_row3_pr3"; | |
fb816641 SW |
707 | nvidia,function = "kbc"; |
708 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
709 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
710 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
711 | }; | |
712 | kb_row4_pr4 { | |
713 | nvidia,pins = "kb_row4_pr4"; | |
fb816641 SW |
714 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
715 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
716 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
717 | }; | |
718 | kb_row5_pr5 { | |
719 | nvidia,pins = "kb_row5_pr5"; | |
720 | nvidia,function = "rsvd3"; | |
fb816641 SW |
721 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
722 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
723 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
724 | }; | |
725 | kb_row6_pr6 { | |
726 | nvidia,pins = "kb_row6_pr6"; | |
727 | nvidia,function = "displaya_alt"; | |
fb816641 SW |
728 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
729 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
730 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
731 | }; | |
732 | kb_row7_pr7 { | |
733 | nvidia,pins = "kb_row7_pr7"; | |
fb816641 SW |
734 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
735 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
736 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
737 | }; | |
738 | kb_row8_ps0 { | |
739 | nvidia,pins = "kb_row8_ps0"; | |
740 | nvidia,function = "rsvd2"; | |
fb816641 SW |
741 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
742 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
743 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
744 | }; |
745 | kb_row9_ps1 { | |
746 | nvidia,pins = "kb_row9_ps1"; | |
fb816641 | 747 | nvidia,function = "uarta"; |
15e524a4 SW |
748 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
749 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
750 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
751 | }; | |
752 | kb_row10_ps2 { | |
753 | nvidia,pins = "kb_row10_ps2"; | |
fb816641 | 754 | nvidia,function = "uarta"; |
15e524a4 | 755 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
fb816641 | 756 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
757 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
758 | }; | |
759 | kb_row11_ps3 { | |
760 | nvidia,pins = "kb_row11_ps3"; | |
761 | nvidia,function = "rsvd2"; | |
fb816641 SW |
762 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
763 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
764 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
765 | }; | |
766 | kb_row12_ps4 { | |
767 | nvidia,pins = "kb_row12_ps4"; | |
768 | nvidia,function = "rsvd2"; | |
fb816641 SW |
769 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
770 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
771 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
772 | }; | |
773 | kb_row13_ps5 { | |
774 | nvidia,pins = "kb_row13_ps5"; | |
775 | nvidia,function = "rsvd2"; | |
fb816641 SW |
776 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
777 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
778 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
779 | }; |
780 | kb_row14_ps6 { | |
781 | nvidia,pins = "kb_row14_ps6"; | |
782 | nvidia,function = "rsvd2"; | |
fb816641 SW |
783 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
784 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
785 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
786 | }; | |
787 | kb_row15_ps7 { | |
788 | nvidia,pins = "kb_row15_ps7"; | |
fb816641 SW |
789 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
790 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
791 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
792 | }; | |
793 | kb_row16_pt0 { | |
794 | nvidia,pins = "kb_row16_pt0"; | |
15e524a4 SW |
795 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
796 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
797 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
798 | }; | |
799 | kb_row17_pt1 { | |
800 | nvidia,pins = "kb_row17_pt1"; | |
15e524a4 | 801 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
802 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
803 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
804 | }; |
805 | gen2_i2c_scl_pt5 { | |
806 | nvidia,pins = "gen2_i2c_scl_pt5"; | |
807 | nvidia,function = "i2c2"; | |
808 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
809 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
810 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
811 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
812 | }; | |
813 | gen2_i2c_sda_pt6 { | |
814 | nvidia,pins = "gen2_i2c_sda_pt6"; | |
815 | nvidia,function = "i2c2"; | |
816 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
817 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
818 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
819 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
820 | }; | |
821 | sdmmc4_cmd_pt7 { | |
822 | nvidia,pins = "sdmmc4_cmd_pt7"; | |
823 | nvidia,function = "sdmmc4"; | |
824 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
825 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
826 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
827 | }; | |
828 | pu0 { | |
829 | nvidia,pins = "pu0"; | |
15e524a4 SW |
830 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
831 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 832 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
833 | }; |
834 | pu1 { | |
835 | nvidia,pins = "pu1"; | |
fb816641 | 836 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
837 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
838 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
839 | }; | |
840 | pu2 { | |
841 | nvidia,pins = "pu2"; | |
fb816641 | 842 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
843 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
844 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
845 | }; | |
846 | pu3 { | |
847 | nvidia,pins = "pu3"; | |
15e524a4 SW |
848 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
849 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 850 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
851 | }; |
852 | pu4 { | |
853 | nvidia,pins = "pu4"; | |
15e524a4 SW |
854 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
855 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 856 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
857 | }; |
858 | pu5 { | |
859 | nvidia,pins = "pu5"; | |
fb816641 | 860 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
861 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
862 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
863 | }; | |
864 | pu6 { | |
865 | nvidia,pins = "pu6"; | |
fb816641 | 866 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
867 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
868 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
869 | }; | |
870 | pv0 { | |
871 | nvidia,pins = "pv0"; | |
fb816641 SW |
872 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
873 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
874 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
875 | }; | |
876 | pv1 { | |
877 | nvidia,pins = "pv1"; | |
fb816641 SW |
878 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
879 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
880 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
881 | }; | |
882 | sdmmc3_cd_n_pv2 { | |
883 | nvidia,pins = "sdmmc3_cd_n_pv2"; | |
884 | nvidia,function = "sdmmc3"; | |
885 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 886 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
887 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
888 | }; | |
889 | sdmmc1_wp_n_pv3 { | |
890 | nvidia,pins = "sdmmc1_wp_n_pv3"; | |
891 | nvidia,function = "sdmmc1"; | |
892 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
893 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
894 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
895 | }; | |
896 | ddc_scl_pv4 { | |
897 | nvidia,pins = "ddc_scl_pv4"; | |
898 | nvidia,function = "i2c4"; | |
899 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
900 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
901 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
902 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
903 | }; | |
904 | ddc_sda_pv5 { | |
905 | nvidia,pins = "ddc_sda_pv5"; | |
906 | nvidia,function = "i2c4"; | |
907 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
908 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
909 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
910 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | |
911 | }; | |
912 | gpio_w2_aud_pw2 { | |
913 | nvidia,pins = "gpio_w2_aud_pw2"; | |
914 | nvidia,function = "rsvd2"; | |
fb816641 SW |
915 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
916 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
917 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
918 | }; |
919 | gpio_w3_aud_pw3 { | |
920 | nvidia,pins = "gpio_w3_aud_pw3"; | |
921 | nvidia,function = "spi6"; | |
fb816641 SW |
922 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
923 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
924 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
925 | }; |
926 | dap_mclk1_pw4 { | |
927 | nvidia,pins = "dap_mclk1_pw4"; | |
928 | nvidia,function = "extperiph1"; | |
929 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
930 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
931 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
932 | }; | |
933 | clk2_out_pw5 { | |
934 | nvidia,pins = "clk2_out_pw5"; | |
935 | nvidia,function = "extperiph2"; | |
936 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
937 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
938 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
939 | }; | |
940 | uart3_txd_pw6 { | |
941 | nvidia,pins = "uart3_txd_pw6"; | |
fb816641 SW |
942 | nvidia,function = "rsvd2"; |
943 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
944 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
945 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
946 | }; | |
947 | uart3_rxd_pw7 { | |
948 | nvidia,pins = "uart3_rxd_pw7"; | |
fb816641 SW |
949 | nvidia,function = "rsvd2"; |
950 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
951 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
952 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
953 | }; |
954 | dvfs_pwm_px0 { | |
955 | nvidia,pins = "dvfs_pwm_px0"; | |
956 | nvidia,function = "cldvfs"; | |
957 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
958 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
959 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
960 | }; | |
961 | gpio_x1_aud_px1 { | |
962 | nvidia,pins = "gpio_x1_aud_px1"; | |
15e524a4 | 963 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
964 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
965 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
966 | }; |
967 | dvfs_clk_px2 { | |
968 | nvidia,pins = "dvfs_clk_px2"; | |
969 | nvidia,function = "cldvfs"; | |
970 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
971 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
972 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
973 | }; | |
974 | gpio_x3_aud_px3 { | |
975 | nvidia,pins = "gpio_x3_aud_px3"; | |
976 | nvidia,function = "rsvd4"; | |
fb816641 SW |
977 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
978 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
979 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
980 | }; |
981 | gpio_x4_aud_px4 { | |
982 | nvidia,pins = "gpio_x4_aud_px4"; | |
15e524a4 | 983 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 SW |
984 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
985 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
986 | }; |
987 | gpio_x5_aud_px5 { | |
988 | nvidia,pins = "gpio_x5_aud_px5"; | |
989 | nvidia,function = "rsvd4"; | |
fb816641 SW |
990 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
991 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
992 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
993 | }; |
994 | gpio_x6_aud_px6 { | |
995 | nvidia,pins = "gpio_x6_aud_px6"; | |
996 | nvidia,function = "gmi"; | |
fb816641 SW |
997 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
998 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
999 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1000 | }; |
1001 | gpio_x7_aud_px7 { | |
1002 | nvidia,pins = "gpio_x7_aud_px7"; | |
15e524a4 SW |
1003 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1004 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1005 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1006 | }; | |
1007 | ulpi_clk_py0 { | |
1008 | nvidia,pins = "ulpi_clk_py0"; | |
1009 | nvidia,function = "spi1"; | |
1010 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1011 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1012 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1013 | }; | |
1014 | ulpi_dir_py1 { | |
1015 | nvidia,pins = "ulpi_dir_py1"; | |
1016 | nvidia,function = "spi1"; | |
fb816641 SW |
1017 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1018 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1019 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1020 | }; | |
1021 | ulpi_nxt_py2 { | |
1022 | nvidia,pins = "ulpi_nxt_py2"; | |
1023 | nvidia,function = "spi1"; | |
1024 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1025 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1026 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1027 | }; | |
1028 | ulpi_stp_py3 { | |
1029 | nvidia,pins = "ulpi_stp_py3"; | |
1030 | nvidia,function = "spi1"; | |
1031 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1032 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1033 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1034 | }; | |
1035 | sdmmc1_dat3_py4 { | |
1036 | nvidia,pins = "sdmmc1_dat3_py4"; | |
1037 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1038 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1039 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1040 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1041 | }; |
1042 | sdmmc1_dat2_py5 { | |
1043 | nvidia,pins = "sdmmc1_dat2_py5"; | |
1044 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1045 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1046 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1047 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1048 | }; |
1049 | sdmmc1_dat1_py6 { | |
1050 | nvidia,pins = "sdmmc1_dat1_py6"; | |
1051 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1052 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1053 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1054 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1055 | }; |
1056 | sdmmc1_dat0_py7 { | |
1057 | nvidia,pins = "sdmmc1_dat0_py7"; | |
fb816641 SW |
1058 | nvidia,function = "rsvd2"; |
1059 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1060 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1061 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1062 | }; |
1063 | sdmmc1_clk_pz0 { | |
1064 | nvidia,pins = "sdmmc1_clk_pz0"; | |
fb816641 SW |
1065 | nvidia,function = "rsvd3"; |
1066 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1067 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1068 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1069 | }; |
1070 | sdmmc1_cmd_pz1 { | |
1071 | nvidia,pins = "sdmmc1_cmd_pz1"; | |
1072 | nvidia,function = "sdmmc1"; | |
fb816641 SW |
1073 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1074 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1075 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1076 | }; |
1077 | pwr_i2c_scl_pz6 { | |
1078 | nvidia,pins = "pwr_i2c_scl_pz6"; | |
1079 | nvidia,function = "i2cpwr"; | |
1080 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1081 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1082 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1083 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1084 | }; | |
1085 | pwr_i2c_sda_pz7 { | |
1086 | nvidia,pins = "pwr_i2c_sda_pz7"; | |
1087 | nvidia,function = "i2cpwr"; | |
1088 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1089 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1090 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1091 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1092 | }; | |
1093 | sdmmc4_dat0_paa0 { | |
1094 | nvidia,pins = "sdmmc4_dat0_paa0"; | |
1095 | nvidia,function = "sdmmc4"; | |
1096 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1097 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1098 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1099 | }; | |
1100 | sdmmc4_dat1_paa1 { | |
1101 | nvidia,pins = "sdmmc4_dat1_paa1"; | |
1102 | nvidia,function = "sdmmc4"; | |
1103 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1105 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1106 | }; | |
1107 | sdmmc4_dat2_paa2 { | |
1108 | nvidia,pins = "sdmmc4_dat2_paa2"; | |
1109 | nvidia,function = "sdmmc4"; | |
1110 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1111 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1113 | }; | |
1114 | sdmmc4_dat3_paa3 { | |
1115 | nvidia,pins = "sdmmc4_dat3_paa3"; | |
1116 | nvidia,function = "sdmmc4"; | |
1117 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1118 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1119 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1120 | }; | |
1121 | sdmmc4_dat4_paa4 { | |
1122 | nvidia,pins = "sdmmc4_dat4_paa4"; | |
1123 | nvidia,function = "sdmmc4"; | |
1124 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1127 | }; | |
1128 | sdmmc4_dat5_paa5 { | |
1129 | nvidia,pins = "sdmmc4_dat5_paa5"; | |
1130 | nvidia,function = "sdmmc4"; | |
1131 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1132 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1133 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1134 | }; | |
1135 | sdmmc4_dat6_paa6 { | |
1136 | nvidia,pins = "sdmmc4_dat6_paa6"; | |
1137 | nvidia,function = "sdmmc4"; | |
1138 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1139 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1140 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1141 | }; | |
1142 | sdmmc4_dat7_paa7 { | |
1143 | nvidia,pins = "sdmmc4_dat7_paa7"; | |
1144 | nvidia,function = "sdmmc4"; | |
1145 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1147 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1148 | }; | |
1149 | pbb0 { | |
1150 | nvidia,pins = "pbb0"; | |
1151 | nvidia,function = "vimclk2_alt"; | |
1152 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1153 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1154 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1155 | }; | |
1156 | cam_i2c_scl_pbb1 { | |
1157 | nvidia,pins = "cam_i2c_scl_pbb1"; | |
1158 | nvidia,function = "i2c3"; | |
1159 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1160 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1161 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1162 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1163 | }; | |
1164 | cam_i2c_sda_pbb2 { | |
1165 | nvidia,pins = "cam_i2c_sda_pbb2"; | |
1166 | nvidia,function = "i2c3"; | |
1167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1169 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1170 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
1171 | }; | |
1172 | pbb3 { | |
1173 | nvidia,pins = "pbb3"; | |
15e524a4 SW |
1174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1176 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1177 | }; | |
1178 | pbb4 { | |
1179 | nvidia,pins = "pbb4"; | |
1180 | nvidia,function = "vgp4"; | |
1181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1184 | }; | |
1185 | pbb5 { | |
1186 | nvidia,pins = "pbb5"; | |
15e524a4 SW |
1187 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1188 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1189 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1190 | }; | |
1191 | pbb6 { | |
1192 | nvidia,pins = "pbb6"; | |
15e524a4 SW |
1193 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1194 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1195 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1196 | }; | |
1197 | pbb7 { | |
1198 | nvidia,pins = "pbb7"; | |
15e524a4 SW |
1199 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1200 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1201 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1202 | }; | |
1203 | cam_mclk_pcc0 { | |
1204 | nvidia,pins = "cam_mclk_pcc0"; | |
1205 | nvidia,function = "vi_alt3"; | |
1206 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1207 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1208 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1209 | }; | |
1210 | pcc1 { | |
1211 | nvidia,pins = "pcc1"; | |
fb816641 | 1212 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1213 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1214 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1215 | }; | |
1216 | pcc2 { | |
1217 | nvidia,pins = "pcc2"; | |
fb816641 | 1218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
15e524a4 SW |
1219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1220 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1221 | }; | |
1222 | sdmmc4_clk_pcc4 { | |
1223 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
1224 | nvidia,function = "sdmmc4"; | |
1225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1226 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1227 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1228 | }; | |
1229 | clk2_req_pcc5 { | |
1230 | nvidia,pins = "clk2_req_pcc5"; | |
1231 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1232 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1233 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1234 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1235 | }; | |
b0da12d5 SW |
1236 | pex_l0_rst_n_pdd1 { |
1237 | nvidia,pins = "pex_l0_rst_n_pdd1"; | |
1238 | nvidia,function = "pe0"; | |
1239 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1240 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1241 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1242 | }; | |
1243 | pex_l0_clkreq_n_pdd2 { | |
1244 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | |
1245 | nvidia,function = "pe0"; | |
fb816641 SW |
1246 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1247 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1248 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1249 | }; | |
1250 | pex_wake_n_pdd3 { | |
1251 | nvidia,pins = "pex_wake_n_pdd3"; | |
1252 | nvidia,function = "pe"; | |
fb816641 SW |
1253 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1254 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1255 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1256 | }; | |
1257 | pex_l1_rst_n_pdd5 { | |
1258 | nvidia,pins = "pex_l1_rst_n_pdd5"; | |
1259 | nvidia,function = "pe1"; | |
1260 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1261 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1262 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1263 | }; | |
1264 | pex_l1_clkreq_n_pdd6 { | |
1265 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | |
1266 | nvidia,function = "pe1"; | |
fb816641 SW |
1267 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1268 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
b0da12d5 SW |
1269 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1270 | }; | |
15e524a4 SW |
1271 | clk3_out_pee0 { |
1272 | nvidia,pins = "clk3_out_pee0"; | |
1273 | nvidia,function = "extperiph3"; | |
1274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1277 | }; | |
1278 | clk3_req_pee1 { | |
1279 | nvidia,pins = "clk3_req_pee1"; | |
1280 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1281 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1282 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1283 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1284 | }; | |
1285 | dap_mclk1_req_pee2 { | |
1286 | nvidia,pins = "dap_mclk1_req_pee2"; | |
15e524a4 SW |
1287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1288 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1289 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1290 | }; | |
1291 | hdmi_cec_pee3 { | |
1292 | nvidia,pins = "hdmi_cec_pee3"; | |
1293 | nvidia,function = "cec"; | |
1294 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1295 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1296 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
fb816641 | 1297 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
15e524a4 SW |
1298 | }; |
1299 | sdmmc3_clk_lb_out_pee4 { | |
1300 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | |
1301 | nvidia,function = "sdmmc3"; | |
1302 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1303 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1304 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1305 | }; | |
1306 | sdmmc3_clk_lb_in_pee5 { | |
1307 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; | |
1308 | nvidia,function = "sdmmc3"; | |
1309 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1310 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1311 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1312 | }; | |
1313 | dp_hpd_pff0 { | |
1314 | nvidia,pins = "dp_hpd_pff0"; | |
1315 | nvidia,function = "dp"; | |
fb816641 SW |
1316 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1317 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1318 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1319 | }; | |
1320 | usb_vbus_en2_pff1 { | |
1321 | nvidia,pins = "usb_vbus_en2_pff1"; | |
1322 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1323 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1324 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
15e524a4 SW |
1325 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
1326 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1327 | }; | |
1328 | pff2 { | |
1329 | nvidia,pins = "pff2"; | |
1330 | nvidia,function = "rsvd2"; | |
fb816641 SW |
1331 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1332 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1333 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
15e524a4 SW |
1334 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
1335 | }; | |
1336 | core_pwr_req { | |
1337 | nvidia,pins = "core_pwr_req"; | |
1338 | nvidia,function = "pwron"; | |
1339 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1341 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1342 | }; | |
1343 | cpu_pwr_req { | |
1344 | nvidia,pins = "cpu_pwr_req"; | |
fb816641 | 1345 | nvidia,function = "cpu"; |
15e524a4 SW |
1346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
1347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1349 | }; | |
1350 | pwr_int_n { | |
1351 | nvidia,pins = "pwr_int_n"; | |
1352 | nvidia,function = "pmi"; | |
1353 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
fb816641 | 1354 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1355 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1356 | }; | |
1357 | reset_out_n { | |
1358 | nvidia,pins = "reset_out_n"; | |
1359 | nvidia,function = "reset_out_n"; | |
1360 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1361 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
fb816641 | 1362 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
15e524a4 | 1363 | }; |
15e524a4 SW |
1364 | clk_32k_in { |
1365 | nvidia,pins = "clk_32k_in"; | |
fb816641 | 1366 | nvidia,function = "clk"; |
15e524a4 | 1367 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
fb816641 | 1368 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
15e524a4 SW |
1369 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1370 | }; | |
1371 | jtag_rtck { | |
1372 | nvidia,pins = "jtag_rtck"; | |
1373 | nvidia,function = "rtck"; | |
1374 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1375 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1376 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1377 | }; | |
aee7a747 SW |
1378 | dsi_b { |
1379 | nvidia,pins = "mipi_pad_ctrl_dsi_b"; | |
1380 | nvidia,function = "dsi_b"; | |
1381 | }; | |
15e524a4 SW |
1382 | }; |
1383 | }; | |
1384 | ||
c90bb7b9 RR |
1385 | /* |
1386 | * First high speed UART, exposed on the expansion connector J3A2 | |
1387 | * Pin 41: BR_UART1_TXD | |
1388 | * Pin 44: BR_UART1_RXD | |
1389 | */ | |
d8b795f5 | 1390 | serial@70006000 { |
c90bb7b9 RR |
1391 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
1392 | status = "okay"; | |
1393 | }; | |
1394 | ||
1395 | /* | |
1396 | * Second high speed UART, exposed on the expansion connector J3A2 | |
1397 | * Pin 65: UART2_RXD | |
1398 | * Pin 68: UART2_TXD | |
1399 | * Pin 71: UART2_CTS_L | |
1400 | * Pin 74: UART2_RTS_L | |
1401 | */ | |
d8b795f5 | 1402 | serial@70006040 { |
c90bb7b9 RR |
1403 | compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; |
1404 | status = "okay"; | |
1405 | }; | |
1406 | ||
15e524a4 | 1407 | /* DB9 serial port */ |
b5896f67 | 1408 | serial@70006300 { |
15e524a4 SW |
1409 | status = "okay"; |
1410 | }; | |
1411 | ||
1412 | /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */ | |
b5896f67 | 1413 | i2c@7000c000 { |
15e524a4 SW |
1414 | status = "okay"; |
1415 | clock-frequency = <100000>; | |
1416 | ||
98de744e SW |
1417 | rt5639: audio-codec@1c { |
1418 | compatible = "realtek,rt5639"; | |
15e524a4 SW |
1419 | reg = <0x1c>; |
1420 | interrupt-parent = <&gpio>; | |
b604ef9c | 1421 | interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>; |
15e524a4 SW |
1422 | realtek,ldo1-en-gpios = |
1423 | <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; | |
1424 | }; | |
1425 | ||
1426 | temperature-sensor@4c { | |
1427 | compatible = "ti,tmp451"; | |
1428 | reg = <0x4c>; | |
1429 | interrupt-parent = <&gpio>; | |
1430 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | |
1431 | }; | |
1432 | ||
1433 | eeprom@56 { | |
1434 | compatible = "atmel,24c02"; | |
1435 | reg = <0x56>; | |
1436 | pagesize = <8>; | |
1437 | }; | |
1438 | }; | |
1439 | ||
1440 | /* Expansion GEN2_I2C_* */ | |
b5896f67 | 1441 | i2c@7000c400 { |
15e524a4 SW |
1442 | status = "okay"; |
1443 | clock-frequency = <100000>; | |
1444 | }; | |
1445 | ||
1446 | /* Expansion CAM_I2C_* */ | |
b5896f67 | 1447 | i2c@7000c500 { |
15e524a4 SW |
1448 | status = "okay"; |
1449 | clock-frequency = <100000>; | |
1450 | }; | |
1451 | ||
1452 | /* HDMI DDC */ | |
b5896f67 | 1453 | hdmi_ddc: i2c@7000c700 { |
15e524a4 SW |
1454 | status = "okay"; |
1455 | clock-frequency = <100000>; | |
1456 | }; | |
1457 | ||
1458 | /* Expansion PWR_I2C_*, on-board components */ | |
b5896f67 | 1459 | i2c@7000d000 { |
15e524a4 SW |
1460 | status = "okay"; |
1461 | clock-frequency = <400000>; | |
1462 | ||
1463 | pmic: pmic@40 { | |
1464 | compatible = "ams,as3722"; | |
1465 | reg = <0x40>; | |
1466 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | |
1467 | ||
1468 | ams,system-power-controller; | |
1469 | ||
1470 | #interrupt-cells = <2>; | |
1471 | interrupt-controller; | |
1472 | ||
1473 | gpio-controller; | |
1474 | #gpio-cells = <2>; | |
1475 | ||
1476 | pinctrl-names = "default"; | |
1477 | pinctrl-0 = <&as3722_default>; | |
1478 | ||
1479 | as3722_default: pinmux { | |
1480 | gpio0 { | |
1481 | pins = "gpio0"; | |
1482 | function = "gpio"; | |
1483 | bias-pull-down; | |
1484 | }; | |
1485 | ||
1486 | gpio1_2_4_7 { | |
1487 | pins = "gpio1", "gpio2", "gpio4", "gpio7"; | |
1488 | function = "gpio"; | |
1489 | bias-pull-up; | |
1490 | }; | |
1491 | ||
1492 | gpio3_5_6 { | |
1493 | pins = "gpio3", "gpio5", "gpio6"; | |
1494 | bias-high-impedance; | |
1495 | }; | |
1496 | }; | |
22b35776 SW |
1497 | |
1498 | regulators { | |
1499 | vsup-sd2-supply = <&vdd_5v0_sys>; | |
1500 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
1501 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
1502 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
1503 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
1504 | vin-ldo1-6-supply = <&vdd_3v3_run>; | |
1505 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
1506 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
1507 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
1508 | vin-ldo11-supply = <&vdd_3v3_run>; | |
1509 | ||
9be1e477 | 1510 | vdd_cpu: sd0 { |
22b35776 SW |
1511 | regulator-name = "+VDD_CPU_AP"; |
1512 | regulator-min-microvolt = <700000>; | |
1513 | regulator-max-microvolt = <1400000>; | |
1514 | regulator-min-microamp = <3500000>; | |
1515 | regulator-max-microamp = <3500000>; | |
1516 | regulator-always-on; | |
1517 | regulator-boot-on; | |
ee913f7a | 1518 | ams,ext-control = <2>; |
22b35776 SW |
1519 | }; |
1520 | ||
1521 | sd1 { | |
1522 | regulator-name = "+VDD_CORE"; | |
1523 | regulator-min-microvolt = <700000>; | |
1524 | regulator-max-microvolt = <1350000>; | |
1525 | regulator-min-microamp = <2500000>; | |
1526 | regulator-max-microamp = <2500000>; | |
1527 | regulator-always-on; | |
1528 | regulator-boot-on; | |
ee913f7a | 1529 | ams,ext-control = <1>; |
22b35776 SW |
1530 | }; |
1531 | ||
1532 | vdd_1v35_lp0: sd2 { | |
1533 | regulator-name = "+1.35V_LP0(sd2)"; | |
1534 | regulator-min-microvolt = <1350000>; | |
1535 | regulator-max-microvolt = <1350000>; | |
1536 | regulator-always-on; | |
1537 | regulator-boot-on; | |
1538 | }; | |
1539 | ||
1540 | sd3 { | |
1541 | regulator-name = "+1.35V_LP0(sd3)"; | |
1542 | regulator-min-microvolt = <1350000>; | |
1543 | regulator-max-microvolt = <1350000>; | |
1544 | regulator-always-on; | |
1545 | regulator-boot-on; | |
1546 | }; | |
1547 | ||
6054dd39 | 1548 | vdd_1v05_run: sd4 { |
22b35776 SW |
1549 | regulator-name = "+1.05V_RUN"; |
1550 | regulator-min-microvolt = <1050000>; | |
1551 | regulator-max-microvolt = <1050000>; | |
1552 | }; | |
1553 | ||
1554 | vddio_1v8: sd5 { | |
1555 | regulator-name = "+1.8V_VDDIO"; | |
1556 | regulator-min-microvolt = <1800000>; | |
1557 | regulator-max-microvolt = <1800000>; | |
1558 | regulator-boot-on; | |
1559 | regulator-always-on; | |
1560 | }; | |
1561 | ||
21fa196f | 1562 | vdd_gpu: sd6 { |
22b35776 SW |
1563 | regulator-name = "+VDD_GPU_AP"; |
1564 | regulator-min-microvolt = <650000>; | |
1565 | regulator-max-microvolt = <1200000>; | |
1566 | regulator-min-microamp = <3500000>; | |
1567 | regulator-max-microamp = <3500000>; | |
1568 | regulator-boot-on; | |
1569 | regulator-always-on; | |
1570 | }; | |
1571 | ||
8e2b9e4d | 1572 | avdd_1v05_run: ldo0 { |
22b35776 SW |
1573 | regulator-name = "+1.05V_RUN_AVDD"; |
1574 | regulator-min-microvolt = <1050000>; | |
1575 | regulator-max-microvolt = <1050000>; | |
1576 | regulator-boot-on; | |
1577 | regulator-always-on; | |
ee913f7a | 1578 | ams,ext-control = <1>; |
22b35776 SW |
1579 | }; |
1580 | ||
1581 | ldo1 { | |
1582 | regulator-name = "+1.8V_RUN_CAM"; | |
1583 | regulator-min-microvolt = <1800000>; | |
1584 | regulator-max-microvolt = <1800000>; | |
1585 | }; | |
1586 | ||
1587 | ldo2 { | |
1588 | regulator-name = "+1.2V_GEN_AVDD"; | |
1589 | regulator-min-microvolt = <1200000>; | |
1590 | regulator-max-microvolt = <1200000>; | |
1591 | regulator-boot-on; | |
1592 | regulator-always-on; | |
1593 | }; | |
1594 | ||
1595 | ldo3 { | |
1596 | regulator-name = "+1.05V_LP0_VDD_RTC"; | |
1597 | regulator-min-microvolt = <1000000>; | |
1598 | regulator-max-microvolt = <1000000>; | |
1599 | regulator-boot-on; | |
1600 | regulator-always-on; | |
1601 | ams,enable-tracking; | |
1602 | }; | |
1603 | ||
1604 | ldo4 { | |
1605 | regulator-name = "+2.8V_RUN_CAM"; | |
1606 | regulator-min-microvolt = <2800000>; | |
1607 | regulator-max-microvolt = <2800000>; | |
1608 | }; | |
1609 | ||
1610 | ldo5 { | |
1611 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | |
1612 | regulator-min-microvolt = <1200000>; | |
1613 | regulator-max-microvolt = <1200000>; | |
1614 | }; | |
1615 | ||
1616 | vddio_sdmmc3: ldo6 { | |
1617 | regulator-name = "+VDDIO_SDMMC3"; | |
1618 | regulator-min-microvolt = <1800000>; | |
1619 | regulator-max-microvolt = <3300000>; | |
1620 | }; | |
1621 | ||
1622 | ldo7 { | |
1623 | regulator-name = "+1.05V_RUN_CAM_REAR"; | |
1624 | regulator-min-microvolt = <1050000>; | |
1625 | regulator-max-microvolt = <1050000>; | |
1626 | }; | |
1627 | ||
1628 | ldo9 { | |
1629 | regulator-name = "+3.3V_RUN_TOUCH"; | |
1630 | regulator-min-microvolt = <2800000>; | |
1631 | regulator-max-microvolt = <2800000>; | |
1632 | }; | |
1633 | ||
1634 | ldo10 { | |
1635 | regulator-name = "+2.8V_RUN_CAM_AF"; | |
1636 | regulator-min-microvolt = <2800000>; | |
1637 | regulator-max-microvolt = <2800000>; | |
1638 | }; | |
1639 | ||
1640 | ldo11 { | |
1641 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | |
1642 | regulator-min-microvolt = <1800000>; | |
1643 | regulator-max-microvolt = <1800000>; | |
1644 | }; | |
1645 | }; | |
15e524a4 SW |
1646 | }; |
1647 | }; | |
1648 | ||
1649 | /* Expansion TS_SPI_* */ | |
b5896f67 | 1650 | spi@7000d400 { |
15e524a4 SW |
1651 | status = "okay"; |
1652 | }; | |
1653 | ||
1654 | /* Internal SPI */ | |
b5896f67 | 1655 | spi@7000da00 { |
15e524a4 SW |
1656 | status = "okay"; |
1657 | spi-max-frequency = <25000000>; | |
1658 | spi-flash@0 { | |
de45b787 | 1659 | compatible = "winbond,w25q32dw", "jedec,spi-nor"; |
15e524a4 SW |
1660 | reg = <0>; |
1661 | spi-max-frequency = <20000000>; | |
1662 | }; | |
1663 | }; | |
1664 | ||
b5896f67 | 1665 | pmc@7000e400 { |
15e524a4 SW |
1666 | nvidia,invert-interrupt; |
1667 | nvidia,suspend-mode = <1>; | |
1668 | nvidia,cpu-pwr-good-time = <500>; | |
1669 | nvidia,cpu-pwr-off-time = <300>; | |
1670 | nvidia,core-pwr-good-time = <641 3845>; | |
1671 | nvidia,core-pwr-off-time = <61036>; | |
1672 | nvidia,core-power-req-active-high; | |
1673 | nvidia,sys-clock-req-active-high; | |
9c963301 MP |
1674 | |
1675 | i2c-thermtrip { | |
1676 | nvidia,i2c-controller-id = <4>; | |
1677 | nvidia,bus-addr = <0x40>; | |
1678 | nvidia,reg-addr = <0x36>; | |
1679 | nvidia,reg-data = <0x2>; | |
1680 | }; | |
15e524a4 SW |
1681 | }; |
1682 | ||
1b3ce99f | 1683 | /* Serial ATA */ |
b5896f67 | 1684 | sata@70020000 { |
1b3ce99f MP |
1685 | status = "okay"; |
1686 | ||
b5896f67 | 1687 | phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; |
87c68119 TR |
1688 | phy-names = "sata-0"; |
1689 | ||
1b3ce99f MP |
1690 | hvdd-supply = <&vdd_3v3_lp0>; |
1691 | vddio-supply = <&vdd_1v05_run>; | |
1692 | avdd-supply = <&vdd_1v05_run>; | |
1693 | ||
1694 | target-5v-supply = <&vdd_5v0_sata>; | |
1695 | target-12v-supply = <&vdd_12v0_sata>; | |
1696 | }; | |
1697 | ||
b5896f67 | 1698 | hda@70030000 { |
4c84472e TR |
1699 | status = "okay"; |
1700 | }; | |
1701 | ||
b5896f67 MZ |
1702 | usb@70090000 { |
1703 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */ | |
1704 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */ | |
1705 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */ | |
1706 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */ | |
87c68119 TR |
1707 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0"; |
1708 | ||
1709 | avddio-pex-supply = <&vdd_1v05_run>; | |
1710 | dvddio-pex-supply = <&vdd_1v05_run>; | |
1711 | avdd-usb-supply = <&vdd_3v3_lp0>; | |
1712 | avdd-pll-utmip-supply = <&vddio_1v8>; | |
1713 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
1714 | avdd-usb-ss-pll-supply = <&vdd_1v05_run>; | |
1715 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; | |
1716 | hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>; | |
1717 | ||
1718 | status = "okay"; | |
1719 | }; | |
1720 | ||
b5896f67 | 1721 | padctl@7009f000 { |
87c68119 | 1722 | status = "okay"; |
62b8db08 | 1723 | |
cbfe6d03 TR |
1724 | avdd-pll-utmip-supply = <&vddio_1v8>; |
1725 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
1726 | avdd-pex-pll-supply = <&vdd_1v05_run>; | |
1727 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; | |
1728 | ||
87c68119 TR |
1729 | pads { |
1730 | usb2 { | |
1731 | status = "okay"; | |
1732 | ||
1733 | lanes { | |
1734 | usb2-0 { | |
96f1abf0 | 1735 | nvidia,function = "snps"; |
87c68119 TR |
1736 | status = "okay"; |
1737 | }; | |
1738 | ||
1739 | usb2-1 { | |
1740 | nvidia,function = "xusb"; | |
1741 | status = "okay"; | |
1742 | }; | |
1743 | ||
1744 | usb2-2 { | |
1745 | nvidia,function = "xusb"; | |
1746 | status = "okay"; | |
1747 | }; | |
1748 | }; | |
62b8db08 TR |
1749 | }; |
1750 | ||
1751 | pcie { | |
87c68119 TR |
1752 | status = "okay"; |
1753 | ||
1754 | lanes { | |
1755 | pcie-0 { | |
1756 | nvidia,function = "usb3-ss"; | |
1757 | status = "okay"; | |
1758 | }; | |
1759 | ||
1760 | pcie-2 { | |
1761 | nvidia,function = "pcie"; | |
1762 | status = "okay"; | |
1763 | }; | |
1764 | ||
1765 | pcie-4 { | |
1766 | nvidia,function = "pcie"; | |
1767 | status = "okay"; | |
1768 | }; | |
1769 | }; | |
62b8db08 TR |
1770 | }; |
1771 | ||
1772 | sata { | |
87c68119 TR |
1773 | status = "okay"; |
1774 | ||
1775 | lanes { | |
1776 | sata-0 { | |
1777 | nvidia,function = "sata"; | |
1778 | status = "okay"; | |
1779 | }; | |
1780 | }; | |
1781 | }; | |
1782 | }; | |
1783 | ||
1784 | ports { | |
839d9bda TR |
1785 | /* Micro A/B */ |
1786 | usb2-0 { | |
1787 | status = "okay"; | |
1788 | mode = "host"; | |
1789 | }; | |
1790 | ||
87c68119 TR |
1791 | /* Mini PCIe */ |
1792 | usb2-1 { | |
1793 | status = "okay"; | |
1794 | mode = "host"; | |
1795 | }; | |
1796 | ||
1797 | /* USB3 */ | |
1798 | usb2-2 { | |
1799 | status = "okay"; | |
1800 | mode = "host"; | |
1801 | ||
1802 | vbus-supply = <&vdd_usb3_vbus>; | |
1803 | }; | |
1804 | ||
1805 | usb3-0 { | |
1806 | nvidia,usb2-companion = <2>; | |
1807 | status = "okay"; | |
62b8db08 TR |
1808 | }; |
1809 | }; | |
1810 | }; | |
1811 | ||
15e524a4 | 1812 | /* SD card */ |
32c096c2 | 1813 | mmc@700b0400 { |
15e524a4 SW |
1814 | status = "okay"; |
1815 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | |
1816 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
215f21c9 | 1817 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; |
15e524a4 | 1818 | bus-width = <4>; |
9260764c | 1819 | vqmmc-supply = <&vddio_sdmmc3>; |
15e524a4 SW |
1820 | }; |
1821 | ||
1822 | /* eMMC */ | |
32c096c2 | 1823 | mmc@700b0600 { |
15e524a4 SW |
1824 | status = "okay"; |
1825 | bus-width = <8>; | |
33f34f0c | 1826 | non-removable; |
15e524a4 SW |
1827 | }; |
1828 | ||
9be1e477 | 1829 | /* CPU DFLL clock */ |
b5896f67 | 1830 | clock@70110000 { |
9be1e477 TT |
1831 | status = "okay"; |
1832 | vdd-cpu-supply = <&vdd_cpu>; | |
1833 | nvidia,i2c-fs-rate = <400000>; | |
1834 | }; | |
1835 | ||
b5896f67 MZ |
1836 | ahub@70300000 { |
1837 | i2s@70301100 { | |
15e524a4 SW |
1838 | status = "okay"; |
1839 | }; | |
1840 | }; | |
1841 | ||
96f1abf0 TR |
1842 | usb@7d000000 { |
1843 | compatible = "nvidia,tegra124-udc"; | |
1844 | status = "okay"; | |
1845 | dr_mode = "peripheral"; | |
1846 | }; | |
1847 | ||
1848 | usb-phy@7d000000 { | |
1849 | status = "okay"; | |
1850 | }; | |
1851 | ||
15e524a4 | 1852 | /* mini-PCIe USB */ |
b5896f67 | 1853 | usb@7d004000 { |
15e524a4 SW |
1854 | status = "okay"; |
1855 | }; | |
1856 | ||
b5896f67 | 1857 | usb-phy@7d004000 { |
15e524a4 SW |
1858 | status = "okay"; |
1859 | }; | |
1860 | ||
1861 | /* USB A connector */ | |
b5896f67 | 1862 | usb@7d008000 { |
15e524a4 SW |
1863 | status = "okay"; |
1864 | }; | |
1865 | ||
b5896f67 | 1866 | usb-phy@7d008000 { |
15e524a4 SW |
1867 | status = "okay"; |
1868 | vbus-supply = <&vdd_usb3_vbus>; | |
1869 | }; | |
1870 | ||
901c8653 TR |
1871 | clk32k_in: clock@0 { |
1872 | compatible = "fixed-clock"; | |
1873 | clock-frequency = <32768>; | |
1874 | #clock-cells = <0>; | |
15e524a4 SW |
1875 | }; |
1876 | ||
ee9f106f MP |
1877 | cpus { |
1878 | cpu@0 { | |
1879 | vdd-cpu-supply = <&vdd_cpu>; | |
1880 | }; | |
1881 | }; | |
1882 | ||
15e524a4 SW |
1883 | gpio-keys { |
1884 | compatible = "gpio-keys"; | |
1885 | ||
1886 | power { | |
1887 | label = "Power"; | |
1888 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1889 | linux,code = <KEY_POWER>; | |
1890 | debounce-interval = <10>; | |
d1c04d30 | 1891 | wakeup-source; |
15e524a4 SW |
1892 | }; |
1893 | }; | |
1894 | ||
1cf17aa6 TR |
1895 | vdd_mux: regulator@0 { |
1896 | compatible = "regulator-fixed"; | |
1897 | regulator-name = "+VDD_MUX"; | |
1898 | regulator-min-microvolt = <12000000>; | |
1899 | regulator-max-microvolt = <12000000>; | |
1900 | regulator-always-on; | |
1901 | regulator-boot-on; | |
1902 | }; | |
22b35776 | 1903 | |
1cf17aa6 TR |
1904 | vdd_5v0_sys: regulator@1 { |
1905 | compatible = "regulator-fixed"; | |
1906 | regulator-name = "+5V_SYS"; | |
1907 | regulator-min-microvolt = <5000000>; | |
1908 | regulator-max-microvolt = <5000000>; | |
1909 | regulator-always-on; | |
1910 | regulator-boot-on; | |
1911 | vin-supply = <&vdd_mux>; | |
1912 | }; | |
22b35776 | 1913 | |
1cf17aa6 TR |
1914 | vdd_3v3_sys: regulator@2 { |
1915 | compatible = "regulator-fixed"; | |
1916 | regulator-name = "+3.3V_SYS"; | |
1917 | regulator-min-microvolt = <3300000>; | |
1918 | regulator-max-microvolt = <3300000>; | |
1919 | regulator-always-on; | |
1920 | regulator-boot-on; | |
1921 | vin-supply = <&vdd_mux>; | |
1922 | }; | |
22b35776 | 1923 | |
1cf17aa6 TR |
1924 | vdd_3v3_run: regulator@3 { |
1925 | compatible = "regulator-fixed"; | |
1926 | regulator-name = "+3.3V_RUN"; | |
1927 | regulator-min-microvolt = <3300000>; | |
1928 | regulator-max-microvolt = <3300000>; | |
1929 | regulator-always-on; | |
1930 | regulator-boot-on; | |
1931 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | |
1932 | enable-active-high; | |
1933 | vin-supply = <&vdd_3v3_sys>; | |
1934 | }; | |
22b35776 | 1935 | |
1cf17aa6 TR |
1936 | vdd_3v3_hdmi: regulator@4 { |
1937 | compatible = "regulator-fixed"; | |
1938 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | |
1939 | regulator-min-microvolt = <3300000>; | |
1940 | regulator-max-microvolt = <3300000>; | |
1941 | vin-supply = <&vdd_3v3_run>; | |
1942 | }; | |
22b35776 | 1943 | |
1cf17aa6 TR |
1944 | vdd_usb1_vbus: regulator@5 { |
1945 | compatible = "regulator-fixed"; | |
1946 | regulator-name = "+USB0_VBUS_SW"; | |
1947 | regulator-min-microvolt = <5000000>; | |
1948 | regulator-max-microvolt = <5000000>; | |
1949 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
1950 | enable-active-high; | |
1951 | gpio-open-drain; | |
1952 | vin-supply = <&vdd_5v0_sys>; | |
1953 | }; | |
22b35776 | 1954 | |
1cf17aa6 TR |
1955 | vdd_usb3_vbus: regulator@6 { |
1956 | compatible = "regulator-fixed"; | |
1957 | regulator-name = "+5V_USB_HS"; | |
1958 | regulator-min-microvolt = <5000000>; | |
1959 | regulator-max-microvolt = <5000000>; | |
1960 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1961 | enable-active-high; | |
1962 | gpio-open-drain; | |
1963 | vin-supply = <&vdd_5v0_sys>; | |
1964 | }; | |
22b35776 | 1965 | |
1cf17aa6 TR |
1966 | vdd_3v3_lp0: regulator@7 { |
1967 | compatible = "regulator-fixed"; | |
1968 | regulator-name = "+3.3V_LP0"; | |
1969 | regulator-min-microvolt = <3300000>; | |
1970 | regulator-max-microvolt = <3300000>; | |
1971 | regulator-always-on; | |
1972 | regulator-boot-on; | |
1973 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | |
1974 | enable-active-high; | |
1975 | vin-supply = <&vdd_3v3_sys>; | |
1976 | }; | |
6054dd39 | 1977 | |
1cf17aa6 TR |
1978 | vdd_hdmi_pll: regulator@8 { |
1979 | compatible = "regulator-fixed"; | |
1980 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | |
1981 | regulator-min-microvolt = <1050000>; | |
1982 | regulator-max-microvolt = <1050000>; | |
1983 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1984 | vin-supply = <&vdd_1v05_run>; | |
1985 | }; | |
6054dd39 | 1986 | |
1cf17aa6 TR |
1987 | vdd_5v0_hdmi: regulator@9 { |
1988 | compatible = "regulator-fixed"; | |
1989 | regulator-name = "+5V_HDMI_CON"; | |
1990 | regulator-min-microvolt = <5000000>; | |
1991 | regulator-max-microvolt = <5000000>; | |
1992 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1993 | enable-active-high; | |
1994 | vin-supply = <&vdd_5v0_sys>; | |
1995 | }; | |
1b3ce99f | 1996 | |
1cf17aa6 TR |
1997 | /* Molex power connector */ |
1998 | vdd_5v0_sata: regulator@10 { | |
1999 | compatible = "regulator-fixed"; | |
2000 | regulator-name = "+5V_SATA"; | |
2001 | regulator-min-microvolt = <5000000>; | |
2002 | regulator-max-microvolt = <5000000>; | |
2003 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
2004 | enable-active-high; | |
2005 | vin-supply = <&vdd_5v0_sys>; | |
2006 | }; | |
1b3ce99f | 2007 | |
1cf17aa6 TR |
2008 | vdd_12v0_sata: regulator@11 { |
2009 | compatible = "regulator-fixed"; | |
2010 | regulator-name = "+12V_SATA"; | |
2011 | regulator-min-microvolt = <12000000>; | |
2012 | regulator-max-microvolt = <12000000>; | |
2013 | gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; | |
2014 | enable-active-high; | |
2015 | vin-supply = <&vdd_mux>; | |
15e524a4 SW |
2016 | }; |
2017 | ||
2018 | sound { | |
2019 | compatible = "nvidia,tegra-audio-rt5640-jetson-tk1", | |
2020 | "nvidia,tegra-audio-rt5640"; | |
2021 | nvidia,model = "NVIDIA Tegra Jetson TK1"; | |
2022 | ||
2023 | nvidia,audio-routing = | |
2024 | "Headphones", "HPOR", | |
2025 | "Headphones", "HPOL", | |
2026 | "Mic Jack", "MICBIAS1", | |
2027 | "IN2P", "Mic Jack"; | |
2028 | ||
2029 | nvidia,i2s-controller = <&tegra_i2s1>; | |
98de744e | 2030 | nvidia,audio-codec = <&rt5639>; |
15e524a4 SW |
2031 | |
2032 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; | |
2033 | ||
2034 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | |
2035 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
bdb2c52a | 2036 | <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
15e524a4 | 2037 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
bdb2c52a SK |
2038 | |
2039 | assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, | |
2040 | <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; | |
2041 | ||
2042 | assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | |
2043 | <&tegra_car TEGRA124_CLK_EXTERN1>; | |
15e524a4 | 2044 | }; |
ed7eac33 MP |
2045 | |
2046 | thermal-zones { | |
2047 | cpu { | |
2048 | trips { | |
40823f8e | 2049 | cpu-shutdown-trip { |
ed7eac33 MP |
2050 | temperature = <101000>; |
2051 | hysteresis = <0>; | |
2052 | type = "critical"; | |
2053 | }; | |
2054 | }; | |
ed7eac33 MP |
2055 | }; |
2056 | ||
2057 | mem { | |
2058 | trips { | |
40823f8e | 2059 | mem-shutdown-trip { |
ed7eac33 MP |
2060 | temperature = <101000>; |
2061 | hysteresis = <0>; | |
2062 | type = "critical"; | |
2063 | }; | |
2064 | }; | |
ed7eac33 MP |
2065 | }; |
2066 | ||
2067 | gpu { | |
2068 | trips { | |
40823f8e | 2069 | gpu-shutdown-trip { |
ed7eac33 MP |
2070 | temperature = <101000>; |
2071 | hysteresis = <0>; | |
2072 | type = "critical"; | |
2073 | }; | |
2074 | }; | |
ed7eac33 MP |
2075 | }; |
2076 | }; | |
15e524a4 | 2077 | }; |