[thirdparty/linux.git] / arch / arm / common / vic.c

/*
 *  linux/arch/arm/common/vic.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/export.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/syscore_ops.h>
#include <linux/device.h>
#include <linux/amba/bus.h>

#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>

/**
 * struct vic_device - VIC PM device
 * @irq: The IRQ number for the base of the VIC.
 * @base: The register base for the VIC.
 * @resume_sources: A bitmask of interrupts for resume.
 * @resume_irqs: The IRQs enabled for resume.
 * @int_select: Save for VIC_INT_SELECT.
 * @int_enable: Save for VIC_INT_ENABLE.
 * @soft_int: Save for VIC_INT_SOFT.
 * @protect: Save for VIC_PROTECT.
 * @domain: The IRQ domain for the VIC.
 */
struct vic_device {
	void __iomem	*base;
	int		irq;
	u32		resume_sources;
	u32		resume_irqs;
	u32		int_select;
	u32		int_enable;
	u32		soft_int;
	u32		protect;
	struct irq_domain *domain;
};

/* we cannot allocate memory when VICs are initially registered */
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];

static int vic_id;

/**
 * vic_init2 - common initialisation code
 * @base: Base of the VIC.
 *
 * Common initialisation code for registration
 * and resume.
*/
static void vic_init2(void __iomem *base)
{
	int i;

	for (i = 0; i < 16; i++) {
		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
		writel(VIC_VECT_CNTL_ENABLE | i, reg);
	}

	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
}

#ifdef CONFIG_PM
static void resume_one_vic(struct vic_device *vic)
{
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);

	/* re-initialise static settings */
	vic_init2(base);

	writel(vic->int_select, base + VIC_INT_SELECT);
	writel(vic->protect, base + VIC_PROTECT);

	/* set the enabled ints and then clear the non-enabled */
	writel(vic->int_enable, base + VIC_INT_ENABLE);
	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);

	/* and the same for the soft-int register */

	writel(vic->soft_int, base + VIC_INT_SOFT);
	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
}

static void vic_resume(void)
{
	int id;

	for (id = vic_id - 1; id >= 0; id--)
		resume_one_vic(vic_devices + id);
}

static void suspend_one_vic(struct vic_device *vic)
{
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);

	vic->int_select = readl(base + VIC_INT_SELECT);
	vic->int_enable = readl(base + VIC_INT_ENABLE);
	vic->soft_int = readl(base + VIC_INT_SOFT);
	vic->protect = readl(base + VIC_PROTECT);

	/* set the interrupts (if any) that are used for
	 * resuming the system */

	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
}

static int vic_suspend(void)
{
	int id;

	for (id = 0; id < vic_id; id++)
		suspend_one_vic(vic_devices + id);

	return 0;
}

struct syscore_ops vic_syscore_ops = {
	.suspend	= vic_suspend,
	.resume		= vic_resume,
};

/**
 * vic_pm_init - initicall to register VIC pm
 *
 * This is called via late_initcall() to register
 * the resources for the VICs due to the early
 * nature of the VIC's registration.
*/
static int __init vic_pm_init(void)
{
	if (vic_id > 0)
		register_syscore_ops(&vic_syscore_ops);

	return 0;
}
late_initcall(vic_pm_init);
#endif /* CONFIG_PM */

/**
 * vic_register() - Register a VIC.
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
 * @resume_sources: bitmask of interrupts allowed for resume sources.
 * @node: The device tree node associated with the VIC.
 *
 * Register the VIC with the system device tree so that it can be notified
 * of suspend and resume requests and ensure that the correct actions are
 * taken to re-instate the settings on resume.
 *
 * This also configures the IRQ domain for the VIC.
 */
static void __init vic_register(void __iomem *base, unsigned int irq,
				u32 resume_sources, struct device_node *node)
{
	struct vic_device *v;

	if (vic_id >= ARRAY_SIZE(vic_devices)) {
		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
		return;
	}

	v = &vic_devices[vic_id];
	v->base = base;
	v->resume_sources = resume_sources;
	v->irq = irq;
	vic_id++;
	v->domain = irq_domain_add_legacy(node, 32, irq, 0,
					  &irq_domain_simple_ops, v);
}

static void vic_ack_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	/* moreover, clear the soft-triggered, in case it was the reason */
	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
}

static void vic_mask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}

static void vic_unmask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE);
}

#if defined(CONFIG_PM)
static struct vic_device *vic_from_irq(unsigned int irq)
{
        struct vic_device *v = vic_devices;
	unsigned int base_irq = irq & ~31;
	int id;

	for (id = 0; id < vic_id; id++, v++) {
		if (v->irq == base_irq)
			return v;
	}

	return NULL;
}

static int vic_set_wake(struct irq_data *d, unsigned int on)
{
	struct vic_device *v = vic_from_irq(d->irq);
	unsigned int off = d->hwirq;
	u32 bit = 1 << off;

	if (!v)
		return -EINVAL;

	if (!(bit & v->resume_sources))
		return -EINVAL;

	if (on)
		v->resume_irqs |= bit;
	else
		v->resume_irqs &= ~bit;

	return 0;
}
#else
#define vic_set_wake NULL
#endif /* CONFIG_PM */

static struct irq_chip vic_chip = {
	.name		= "VIC",
	.irq_ack	= vic_ack_irq,
	.irq_mask	= vic_mask_irq,
	.irq_unmask	= vic_unmask_irq,
	.irq_set_wake	= vic_set_wake,
};

static void __init vic_disable(void __iomem *base)
{
	writel(0, base + VIC_INT_SELECT);
	writel(0, base + VIC_INT_ENABLE);
	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	writel(0, base + VIC_ITCR);
	writel(~0, base + VIC_INT_SOFT_CLEAR);
}

static void __init vic_clear_interrupts(void __iomem *base)
{
	unsigned int i;

	writel(0, base + VIC_PL190_VECT_ADDR);
	for (i = 0; i < 19; i++) {
		unsigned int value;

		value = readl(base + VIC_PL190_VECT_ADDR);
		writel(value, base + VIC_PL190_VECT_ADDR);
	}
}

static void __init vic_set_irq_sources(void __iomem *base,
				unsigned int irq_start, u32 vic_sources)
{
	unsigned int i;

	for (i = 0; i < 32; i++) {
		if (vic_sources & (1 << i)) {
			unsigned int irq = irq_start + i;

			irq_set_chip_and_handler(irq, &vic_chip,
						 handle_level_irq);
			irq_set_chip_data(irq, base);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}
}

/*
 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 * The original cell has 32 interrupts, while the modified one has 64,
 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 * the probe function is called twice, with base set to offset 000
 *  and 020 within the page. We call this "second block".
 */
static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
			       u32 vic_sources, struct device_node *node)
{
	unsigned int i;
	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;

	/* Disable all interrupts initially. */
	vic_disable(base);

	/*
	 * Make sure we clear all existing interrupts. The vector registers
	 * in this cell are after the second block of general registers,
	 * so we can address them using standard offsets, but only from
	 * the second base address, which is 0x20 in the page
	 */
	if (vic_2nd_block) {
		vic_clear_interrupts(base);

		/* ST has 16 vectors as well, but we don't enable them by now */
		for (i = 0; i < 16; i++) {
			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
			writel(0, reg);
		}

		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	}

	vic_set_irq_sources(base, irq_start, vic_sources);
	vic_register(base, irq_start, 0, node);
}

void __init __vic_init(void __iomem *base, unsigned int irq_start,
			      u32 vic_sources, u32 resume_sources,
			      struct device_node *node)
{
	unsigned int i;
	u32 cellid = 0;
	enum amba_vendor vendor;

	/* Identify which VIC cell this one is, by reading the ID */
	for (i = 0; i < 4; i++) {
		void __iomem *addr;
		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
		cellid |= (readl(addr) & 0xff) << (8 * i);
	}
	vendor = (cellid >> 12) & 0xff;
	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	       base, cellid, vendor);

	switch(vendor) {
	case AMBA_VENDOR_ST:
		vic_init_st(base, irq_start, vic_sources, node);
		return;
	default:
		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
		/* fall through */
	case AMBA_VENDOR_ARM:
		break;
	}

	/* Disable all interrupts initially. */
	vic_disable(base);

	/* Make sure we clear all existing interrupts */
	vic_clear_interrupts(base);

	vic_init2(base);

	vic_set_irq_sources(base, irq_start, vic_sources);

	vic_register(base, irq_start, resume_sources, node);
}

/**
 * vic_init() - initialise a vectored interrupt controller
 * @base: iomem base address
 * @irq_start: starting interrupt number, must be muliple of 32
 * @vic_sources: bitmask of interrupt sources to allow
 * @resume_sources: bitmask of interrupt sources to allow for resume
 */
void __init vic_init(void __iomem *base, unsigned int irq_start,
		     u32 vic_sources, u32 resume_sources)
{
	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
}

#ifdef CONFIG_OF
int __init vic_of_init(struct device_node *node, struct device_node *parent)
{
	void __iomem *regs;
	int irq_base;

	if (WARN(parent, "non-root VICs are not supported"))
		return -EINVAL;

	regs = of_iomap(node, 0);
	if (WARN_ON(!regs))
		return -EIO;

	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	if (WARN_ON(irq_base < 0))
		goto out_unmap;

	__vic_init(regs, irq_base, ~0, ~0, node);

	return 0;

 out_unmap:
	iounmap(regs);

	return -EIO;
}
#endif /* CONFIG OF */

/*
 * Handle each interrupt in a single VIC.  Returns non-zero if we've
 * handled at least one interrupt.  This reads the status register
 * before handling each interrupt, which is necessary given that
 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 */
static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
{
	u32 stat, irq;
	int handled = 0;

	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
		irq = ffs(stat) - 1;
		handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
		handled = 1;
	}

	return handled;
}

/*
 * Keep iterating over all registered VIC's until there are no pending
 * interrupts.
 */
asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
{
	int i, handled;

	do {
		for (i = 0, handled = 0; i < vic_id; ++i)
			handled |= handle_one_vic(&vic_devices[i], regs);
	} while (handled);
}
Commit	Line	Data
fa0fe48f RK	1	/*
	2	* linux/arch/arm/common/vic.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
bb06b737	21
f9b28ccb	22	#include <linux/export.h>
fa0fe48f RK	23	#include <linux/init.h>
fa0fe48f RK	24	#include <linux/list.h>
fced80c7	25	#include <linux/io.h>
f9b28ccb JI	26	#include <linux/irqdomain.h>
	27	#include <linux/of.h>
	28	#include <linux/of_address.h>
	29	#include <linux/of_irq.h>
328f5cc3	30	#include <linux/syscore_ops.h>
59fcf48f	31	#include <linux/device.h>
f17a1f06	32	#include <linux/amba/bus.h>
fa0fe48f	33
1558368e	34	#include <asm/exception.h>
fa0fe48f RK	35	#include <asm/mach/irq.h>
	36	#include <asm/hardware/vic.h>
	37
c07f87f2 BD	38	/**
c07f87f2 BD	39	* struct vic_device - VIC PM device
c07f87f2 BD	40	* @irq: The IRQ number for the base of the VIC.
	41	* @base: The register base for the VIC.
	42	* @resume_sources: A bitmask of interrupts for resume.
	43	* @resume_irqs: The IRQs enabled for resume.
	44	* @int_select: Save for VIC_INT_SELECT.
	45	* @int_enable: Save for VIC_INT_ENABLE.
	46	* @soft_int: Save for VIC_INT_SOFT.
	47	* @protect: Save for VIC_PROTECT.
f9b28ccb	48	* @domain: The IRQ domain for the VIC.
c07f87f2 BD	49	*/
c07f87f2 BD	50	struct vic_device {
c07f87f2 BD	51	void __iomem *base;
	52	int irq;
	53	u32 resume_sources;
	54	u32 resume_irqs;
	55	u32 int_select;
	56	u32 int_enable;
	57	u32 soft_int;
	58	u32 protect;
75294957	59	struct irq_domain *domain;
c07f87f2 BD	60	};
	61
	62	/* we cannot allocate memory when VICs are initially registered */
	63	static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
	64
bb06b737	65	static int vic_id;
c07f87f2	66
bb06b737 HS	67	/**
	68	* vic_init2 - common initialisation code
	69	* @base: Base of the VIC.
	70	*
b595076a	71	* Common initialisation code for registration
bb06b737 HS	72	* and resume.
	73	*/
	74	static void vic_init2(void __iomem *base)
	75	{
	76	int i;
	77
	78	for (i = 0; i < 16; i++) {
	79	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	80	writel(VIC_VECT_CNTL_ENABLE \| i, reg);
	81	}
	82
	83	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	84	}
c07f87f2	85
328f5cc3 RW	86	#ifdef CONFIG_PM
328f5cc3 RW	87	static void resume_one_vic(struct vic_device *vic)
c07f87f2	88	{
c07f87f2 BD	89	void __iomem *base = vic->base;
	90
	91	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
	92
	93	/* re-initialise static settings */
	94	vic_init2(base);
	95
	96	writel(vic->int_select, base + VIC_INT_SELECT);
	97	writel(vic->protect, base + VIC_PROTECT);
	98
	99	/* set the enabled ints and then clear the non-enabled */
	100	writel(vic->int_enable, base + VIC_INT_ENABLE);
	101	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
	102
	103	/* and the same for the soft-int register */
	104
	105	writel(vic->soft_int, base + VIC_INT_SOFT);
	106	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
328f5cc3	107	}
c07f87f2	108
328f5cc3 RW	109	static void vic_resume(void)
	110	{
	111	int id;
	112
	113	for (id = vic_id - 1; id >= 0; id--)
	114	resume_one_vic(vic_devices + id);
c07f87f2 BD	115	}
c07f87f2 BD	116
328f5cc3	117	static void suspend_one_vic(struct vic_device *vic)
c07f87f2	118	{
c07f87f2 BD	119	void __iomem *base = vic->base;
	120
	121	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
	122
	123	vic->int_select = readl(base + VIC_INT_SELECT);
	124	vic->int_enable = readl(base + VIC_INT_ENABLE);
	125	vic->soft_int = readl(base + VIC_INT_SOFT);
	126	vic->protect = readl(base + VIC_PROTECT);
	127
	128	/* set the interrupts (if any) that are used for
	129	* resuming the system */
	130
	131	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
	132	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
328f5cc3 RW	133	}
	134
	135	static int vic_suspend(void)
	136	{
	137	int id;
	138
	139	for (id = 0; id < vic_id; id++)
	140	suspend_one_vic(vic_devices + id);
c07f87f2 BD	141
	142	return 0;
	143	}
	144
328f5cc3 RW	145	struct syscore_ops vic_syscore_ops = {
	146	.suspend = vic_suspend,
	147	.resume = vic_resume,
c07f87f2 BD	148	};
c07f87f2 BD	149
c07f87f2 BD	150	/**
	151	* vic_pm_init - initicall to register VIC pm
	152	*
	153	* This is called via late_initcall() to register
	154	* the resources for the VICs due to the early
	155	* nature of the VIC's registration.
	156	*/
	157	static int __init vic_pm_init(void)
	158	{
328f5cc3 RW	159	if (vic_id > 0)
328f5cc3 RW	160	register_syscore_ops(&vic_syscore_ops);
c07f87f2 BD	161
	162	return 0;
	163	}
c07f87f2	164	late_initcall(vic_pm_init);
f9b28ccb	165	#endif /* CONFIG_PM */
c07f87f2	166
bb06b737	167	/**
f9b28ccb	168	* vic_register() - Register a VIC.
bb06b737 HS	169	* @base: The base address of the VIC.
	170	* @irq: The base IRQ for the VIC.
	171	* @resume_sources: bitmask of interrupts allowed for resume sources.
f9b28ccb	172	* @node: The device tree node associated with the VIC.
bb06b737 HS	173	*
	174	* Register the VIC with the system device tree so that it can be notified
	175	* of suspend and resume requests and ensure that the correct actions are
	176	* taken to re-instate the settings on resume.
f9b28ccb JI	177	*
f9b28ccb JI	178	* This also configures the IRQ domain for the VIC.
bb06b737	179	*/
f9b28ccb JI	180	static void __init vic_register(void __iomem *base, unsigned int irq,
f9b28ccb JI	181	u32 resume_sources, struct device_node *node)
bb06b737 HS	182	{
	183	struct vic_device *v;
	184
f9b28ccb	185	if (vic_id >= ARRAY_SIZE(vic_devices)) {
bb06b737	186	printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
f9b28ccb	187	return;
bb06b737	188	}
f9b28ccb JI	189
	190	v = &vic_devices[vic_id];
	191	v->base = base;
	192	v->resume_sources = resume_sources;
	193	v->irq = irq;
	194	vic_id++;
75294957 GL	195	v->domain = irq_domain_add_legacy(node, 32, irq, 0,
75294957 GL	196	&irq_domain_simple_ops, v);
bb06b737	197	}
bb06b737	198
f013c98d	199	static void vic_ack_irq(struct irq_data *d)
bb06b737	200	{
f013c98d	201	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	202	unsigned int irq = d->hwirq;
bb06b737 HS	203	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	204	/* moreover, clear the soft-triggered, in case it was the reason */
	205	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
	206	}
	207
f013c98d	208	static void vic_mask_irq(struct irq_data *d)
bb06b737	209	{
f013c98d	210	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	211	unsigned int irq = d->hwirq;
bb06b737 HS	212	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	213	}
	214
f013c98d	215	static void vic_unmask_irq(struct irq_data *d)
bb06b737	216	{
f013c98d	217	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	218	unsigned int irq = d->hwirq;
bb06b737 HS	219	writel(1 << irq, base + VIC_INT_ENABLE);
	220	}
	221
	222	#if defined(CONFIG_PM)
c07f87f2 BD	223	static struct vic_device *vic_from_irq(unsigned int irq)
	224	{
	225	struct vic_device *v = vic_devices;
	226	unsigned int base_irq = irq & ~31;
	227	int id;
	228
	229	for (id = 0; id < vic_id; id++, v++) {
	230	if (v->irq == base_irq)
	231	return v;
	232	}
	233
	234	return NULL;
	235	}
	236
f013c98d	237	static int vic_set_wake(struct irq_data *d, unsigned int on)
c07f87f2	238	{
f013c98d	239	struct vic_device *v = vic_from_irq(d->irq);
f9b28ccb	240	unsigned int off = d->hwirq;
3f1a567d	241	u32 bit = 1 << off;
c07f87f2 BD	242
	243	if (!v)
	244	return -EINVAL;
	245
3f1a567d BD	246	if (!(bit & v->resume_sources))
	247	return -EINVAL;
	248
c07f87f2	249	if (on)
3f1a567d	250	v->resume_irqs \|= bit;
c07f87f2	251	else
3f1a567d	252	v->resume_irqs &= ~bit;
c07f87f2 BD	253
	254	return 0;
	255	}
c07f87f2	256	#else
c07f87f2 BD	257	#define vic_set_wake NULL
	258	#endif /* CONFIG_PM */
	259
38c677cb	260	static struct irq_chip vic_chip = {
b0c4c898	261	.name = "VIC",
f013c98d LB	262	.irq_ack = vic_ack_irq,
	263	.irq_mask = vic_mask_irq,
	264	.irq_unmask = vic_unmask_irq,
	265	.irq_set_wake = vic_set_wake,
fa0fe48f RK	266	};
fa0fe48f RK	267
b0c4c898 HS	268	static void __init vic_disable(void __iomem *base)
	269	{
	270	writel(0, base + VIC_INT_SELECT);
	271	writel(0, base + VIC_INT_ENABLE);
	272	writel(~0, base + VIC_INT_ENABLE_CLEAR);
b0c4c898 HS	273	writel(0, base + VIC_ITCR);
	274	writel(~0, base + VIC_INT_SOFT_CLEAR);
	275	}
	276
	277	static void __init vic_clear_interrupts(void __iomem *base)
	278	{
	279	unsigned int i;
	280
	281	writel(0, base + VIC_PL190_VECT_ADDR);
	282	for (i = 0; i < 19; i++) {
	283	unsigned int value;
	284
	285	value = readl(base + VIC_PL190_VECT_ADDR);
	286	writel(value, base + VIC_PL190_VECT_ADDR);
	287	}
	288	}
	289
	290	static void __init vic_set_irq_sources(void __iomem *base,
	291	unsigned int irq_start, u32 vic_sources)
	292	{
	293	unsigned int i;
	294
	295	for (i = 0; i < 32; i++) {
	296	if (vic_sources & (1 << i)) {
	297	unsigned int irq = irq_start + i;
	298
f38c02f3 TG	299	irq_set_chip_and_handler(irq, &vic_chip,
f38c02f3 TG	300	handle_level_irq);
9323f261	301	irq_set_chip_data(irq, base);
b0c4c898 HS	302	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	303	}
	304	}
	305	}
	306
bb06b737 HS	307	/*
	308	* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
	309	* The original cell has 32 interrupts, while the modified one has 64,
	310	* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
	311	* the probe function is called twice, with base set to offset 000
	312	* and 020 within the page. We call this "second block".
	313	*/
	314	static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
ad622671	315	u32 vic_sources, struct device_node *node)
bb06b737 HS	316	{
	317	unsigned int i;
	318	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
	319
	320	/* Disable all interrupts initially. */
b0c4c898	321	vic_disable(base);
bb06b737 HS	322
	323	/*
	324	* Make sure we clear all existing interrupts. The vector registers
	325	* in this cell are after the second block of general registers,
	326	* so we can address them using standard offsets, but only from
	327	* the second base address, which is 0x20 in the page
	328	*/
	329	if (vic_2nd_block) {
b0c4c898	330	vic_clear_interrupts(base);
bb06b737	331
bb06b737 HS	332	/* ST has 16 vectors as well, but we don't enable them by now */
	333	for (i = 0; i < 16; i++) {
	334	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	335	writel(0, reg);
	336	}
	337
	338	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	339	}
	340
b0c4c898	341	vic_set_irq_sources(base, irq_start, vic_sources);
ad622671	342	vic_register(base, irq_start, 0, node);
bb06b737	343	}
87e8824b	344
75294957	345	void __init __vic_init(void __iomem *base, unsigned int irq_start,
f9b28ccb JI	346	u32 vic_sources, u32 resume_sources,
f9b28ccb JI	347	struct device_node *node)
fa0fe48f RK	348	{
fa0fe48f RK	349	unsigned int i;
87e8824b	350	u32 cellid = 0;
f17a1f06	351	enum amba_vendor vendor;
87e8824b AR	352
	353	/* Identify which VIC cell this one is, by reading the ID */
	354	for (i = 0; i < 4; i++) {
d4f3add2 AB	355	void __iomem *addr;
d4f3add2 AB	356	addr = (void __iomem )((u32)base & PAGE_MASK) + 0xfe0 + (i 4);
87e8824b AR	357	cellid \|= (readl(addr) & 0xff) << (8 * i);
	358	}
	359	vendor = (cellid >> 12) & 0xff;
	360	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	361	base, cellid, vendor);
	362
	363	switch(vendor) {
f17a1f06	364	case AMBA_VENDOR_ST:
ad622671	365	vic_init_st(base, irq_start, vic_sources, node);
87e8824b AR	366	return;
	367	default:
	368	printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
	369	/* fall through */
f17a1f06	370	case AMBA_VENDOR_ARM:
87e8824b AR	371	break;
87e8824b AR	372	}
fa0fe48f	373
fa0fe48f	374	/* Disable all interrupts initially. */
b0c4c898	375	vic_disable(base);
fa0fe48f	376
b0c4c898 HS	377	/* Make sure we clear all existing interrupts */
b0c4c898 HS	378	vic_clear_interrupts(base);
fa0fe48f	379
c07f87f2	380	vic_init2(base);
fa0fe48f	381
b0c4c898	382	vic_set_irq_sources(base, irq_start, vic_sources);
c07f87f2	383
f9b28ccb JI	384	vic_register(base, irq_start, resume_sources, node);
	385	}
	386
	387	/**
	388	* vic_init() - initialise a vectored interrupt controller
	389	* @base: iomem base address
	390	* @irq_start: starting interrupt number, must be muliple of 32
	391	* @vic_sources: bitmask of interrupt sources to allow
	392	* @resume_sources: bitmask of interrupt sources to allow for resume
	393	*/
	394	void __init vic_init(void __iomem *base, unsigned int irq_start,
	395	u32 vic_sources, u32 resume_sources)
	396	{
	397	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
	398	}
	399
	400	#ifdef CONFIG_OF
	401	int __init vic_of_init(struct device_node node, struct device_node parent)
	402	{
	403	void __iomem *regs;
	404	int irq_base;
	405
	406	if (WARN(parent, "non-root VICs are not supported"))
	407	return -EINVAL;
	408
	409	regs = of_iomap(node, 0);
	410	if (WARN_ON(!regs))
	411	return -EIO;
	412
	413	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	414	if (WARN_ON(irq_base < 0))
	415	goto out_unmap;
	416
	417	__vic_init(regs, irq_base, ~0, ~0, node);
	418
	419	return 0;
	420
	421	out_unmap:
	422	iounmap(regs);
	423
	424	return -EIO;
fa0fe48f	425	}
f9b28ccb	426	#endif /* CONFIG OF */
1558368e	427
1558368e JI	428	/*
1558368e JI	429	* Handle each interrupt in a single VIC. Returns non-zero if we've
34af6579 WD	430	* handled at least one interrupt. This reads the status register
	431	* before handling each interrupt, which is necessary given that
	432	* handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
1558368e JI	433	*/
	434	static int handle_one_vic(struct vic_device vic, struct pt_regs regs)
	435	{
	436	u32 stat, irq;
	437	int handled = 0;
	438
34af6579	439	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
1558368e	440	irq = ffs(stat) - 1;
75294957	441	handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
1558368e JI	442	handled = 1;
	443	}
	444
	445	return handled;
	446	}
	447
	448	/*
	449	* Keep iterating over all registered VIC's until there are no pending
	450	* interrupts.
	451	*/
	452	asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
	453	{
	454	int i, handled;
	455
	456	do {
	457	for (i = 0, handled = 0; i < vic_id; ++i)
	458	handled \|= handle_one_vic(&vic_devices[i], regs);
	459	} while (handled);
	460	}