[thirdparty/linux.git] / arch / arm / common / vic.c

/*
 *  linux/arch/arm/common/vic.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>

#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>

static void vic_mask_irq(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);
	irq &= 31;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}

static void vic_unmask_irq(unsigned int irq)
{
	void __iomem *base = get_irq_chip_data(irq);
	irq &= 31;
	writel(1 << irq, base + VIC_INT_ENABLE);
}

static struct irq_chip vic_chip = {
	.name	= "VIC",
	.ack	= vic_mask_irq,
	.mask	= vic_mask_irq,
	.unmask	= vic_unmask_irq,
};

/**
 * vic_init - initialise a vectored interrupt controller
 * @base: iomem base address
 * @irq_start: starting interrupt number, must be muliple of 32
 * @vic_sources: bitmask of interrupt sources to allow
 */
void __init vic_init(void __iomem *base, unsigned int irq_start,
		     u32 vic_sources)
{
	unsigned int i;

	/* Disable all interrupts initially. */

	writel(0, base + VIC_INT_SELECT);
	writel(0, base + VIC_INT_ENABLE);
	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	writel(0, base + VIC_IRQ_STATUS);
	writel(0, base + VIC_ITCR);
	writel(~0, base + VIC_INT_SOFT_CLEAR);

	/*
	 * Make sure we clear all existing interrupts
	 */
	writel(0, base + VIC_VECT_ADDR);
	for (i = 0; i < 19; i++) {
		unsigned int value;

		value = readl(base + VIC_VECT_ADDR);
		writel(value, base + VIC_VECT_ADDR);
	}

	for (i = 0; i < 16; i++) {
		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
		writel(VIC_VECT_CNTL_ENABLE | i, reg);
	}

	writel(32, base + VIC_DEF_VECT_ADDR);

	for (i = 0; i < 32; i++) {
		unsigned int irq = irq_start + i;

		set_irq_chip(irq, &vic_chip);
		set_irq_chip_data(irq, base);

		if (vic_sources & (1 << i)) {
			set_irq_handler(irq, handle_level_irq);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}
}
Commit	Line	Data
fa0fe48f RK	1	/*
	2	* linux/arch/arm/common/vic.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <linux/init.h>
	22	#include <linux/list.h>
fced80c7	23	#include <linux/io.h>
fa0fe48f	24
fa0fe48f RK	25	#include <asm/mach/irq.h>
	26	#include <asm/hardware/vic.h>
	27
fa0fe48f RK	28	static void vic_mask_irq(unsigned int irq)
fa0fe48f RK	29	{
10dd5ce2	30	void __iomem *base = get_irq_chip_data(irq);
824b5b5e RK	31	irq &= 31;
824b5b5e RK	32	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
fa0fe48f RK	33	}
	34
	35	static void vic_unmask_irq(unsigned int irq)
	36	{
10dd5ce2	37	void __iomem *base = get_irq_chip_data(irq);
824b5b5e RK	38	irq &= 31;
824b5b5e RK	39	writel(1 << irq, base + VIC_INT_ENABLE);
fa0fe48f RK	40	}
fa0fe48f RK	41
38c677cb DB	42	static struct irq_chip vic_chip = {
38c677cb DB	43	.name = "VIC",
fa0fe48f RK	44	.ack = vic_mask_irq,
	45	.mask = vic_mask_irq,
	46	.unmask = vic_unmask_irq,
	47	};
	48
824b5b5e RK	49	/**
	50	* vic_init - initialise a vectored interrupt controller
	51	* @base: iomem base address
	52	* @irq_start: starting interrupt number, must be muliple of 32
	53	* @vic_sources: bitmask of interrupt sources to allow
	54	*/
	55	void __init vic_init(void __iomem *base, unsigned int irq_start,
	56	u32 vic_sources)
fa0fe48f RK	57	{
	58	unsigned int i;
	59
fa0fe48f RK	60	/* Disable all interrupts initially. */
fa0fe48f RK	61
824b5b5e RK	62	writel(0, base + VIC_INT_SELECT);
	63	writel(0, base + VIC_INT_ENABLE);
	64	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	65	writel(0, base + VIC_IRQ_STATUS);
	66	writel(0, base + VIC_ITCR);
	67	writel(~0, base + VIC_INT_SOFT_CLEAR);
fa0fe48f RK	68
	69	/*
	70	* Make sure we clear all existing interrupts
	71	*/
824b5b5e	72	writel(0, base + VIC_VECT_ADDR);
fa0fe48f RK	73	for (i = 0; i < 19; i++) {
	74	unsigned int value;
	75
824b5b5e RK	76	value = readl(base + VIC_VECT_ADDR);
824b5b5e RK	77	writel(value, base + VIC_VECT_ADDR);
fa0fe48f RK	78	}
	79
	80	for (i = 0; i < 16; i++) {
824b5b5e	81	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
fa0fe48f RK	82	writel(VIC_VECT_CNTL_ENABLE \| i, reg);
	83	}
	84
824b5b5e	85	writel(32, base + VIC_DEF_VECT_ADDR);
fa0fe48f RK	86
fa0fe48f RK	87	for (i = 0; i < 32; i++) {
824b5b5e	88	unsigned int irq = irq_start + i;
fa0fe48f RK	89
fa0fe48f RK	90	set_irq_chip(irq, &vic_chip);
10dd5ce2	91	set_irq_chip_data(irq, base);
fa0fe48f RK	92
fa0fe48f RK	93	if (vic_sources & (1 << i)) {
10dd5ce2	94	set_irq_handler(irq, handle_level_irq);
fa0fe48f RK	95	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	96	}
	97	}
	98	}