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Commit | Line | Data |
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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
8ed96046 WD |
2 | /* |
3 | * (C) Copyright 2004 Texas Insturments | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * (C) Copyright 2002 | |
792a09eb | 10 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
8ed96046 WD |
11 | */ |
12 | ||
13 | /* | |
14 | * CPU specific code | |
15 | */ | |
16 | ||
17 | #include <common.h> | |
18 | #include <command.h> | |
9edefc27 | 19 | #include <cpu_func.h> |
36bf446b | 20 | #include <irq_func.h> |
90526e9f | 21 | #include <asm/cache.h> |
677e62f4 | 22 | #include <asm/system.h> |
8ed96046 | 23 | |
b3acb6cd | 24 | static void cache_flush(void); |
8ed96046 | 25 | |
8ed96046 WD |
26 | int cleanup_before_linux (void) |
27 | { | |
28 | /* | |
29 | * this function is called just before we call linux | |
30 | * it prepares the processor for linux | |
31 | * | |
32 | * we turn off caches etc ... | |
33 | */ | |
34 | ||
9d3915b2 | 35 | disable_interrupts(); |
8ed96046 | 36 | |
8ed96046 | 37 | /* turn off I/D-cache */ |
b3acb6cd JCPV |
38 | icache_disable(); |
39 | dcache_disable(); | |
8ed96046 | 40 | /* flush I/D-cache */ |
b3acb6cd JCPV |
41 | cache_flush(); |
42 | ||
43 | return 0; | |
8ed96046 WD |
44 | } |
45 | ||
b3acb6cd | 46 | static void cache_flush(void) |
8ed96046 | 47 | { |
b3acb6cd | 48 | unsigned long i = 0; |
fbf4a074 SB |
49 | /* clean entire data cache */ |
50 | asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); | |
51 | /* invalidate both caches and flush btb */ | |
52 | asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); | |
53 | /* mem barrier to sync things */ | |
54 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); | |
8ed96046 | 55 | } |
219872c8 | 56 | |
10015025 | 57 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
219872c8 AG |
58 | void invalidate_dcache_all(void) |
59 | { | |
fbf4a074 | 60 | asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); |
219872c8 AG |
61 | } |
62 | ||
63 | void flush_dcache_all(void) | |
64 | { | |
fbf4a074 SB |
65 | asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); |
66 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); | |
219872c8 AG |
67 | } |
68 | ||
219872c8 AG |
69 | void invalidate_dcache_range(unsigned long start, unsigned long stop) |
70 | { | |
f8f09dd4 | 71 | if (!check_cache_range(start, stop)) |
219872c8 AG |
72 | return; |
73 | ||
74 | while (start < stop) { | |
fbf4a074 | 75 | asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); |
219872c8 AG |
76 | start += CONFIG_SYS_CACHELINE_SIZE; |
77 | } | |
78 | } | |
79 | ||
80 | void flush_dcache_range(unsigned long start, unsigned long stop) | |
81 | { | |
f8f09dd4 | 82 | if (!check_cache_range(start, stop)) |
219872c8 AG |
83 | return; |
84 | ||
85 | while (start < stop) { | |
fbf4a074 | 86 | asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); |
219872c8 AG |
87 | start += CONFIG_SYS_CACHELINE_SIZE; |
88 | } | |
89 | ||
fbf4a074 | 90 | asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
219872c8 AG |
91 | } |
92 | ||
10015025 | 93 | #else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
219872c8 AG |
94 | void invalidate_dcache_all(void) |
95 | { | |
96 | } | |
97 | ||
98 | void flush_dcache_all(void) | |
99 | { | |
100 | } | |
10015025 | 101 | #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ |
ccfa3985 | 102 | |
10015025 | 103 | #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) |
ccfa3985 BT |
104 | void enable_caches(void) |
105 | { | |
10015025 | 106 | #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) |
ccfa3985 BT |
107 | icache_enable(); |
108 | #endif | |
10015025 | 109 | #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) |
ccfa3985 BT |
110 | dcache_enable(); |
111 | #endif | |
112 | } | |
113 | #endif |