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dd2f6965 ML |
1 | /* |
2 | * | |
3 | * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> | |
4 | * | |
5 | * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
86271115 SB |
27 | #include <asm/arch/imx-regs.h> |
28 | #include <asm/arch/clock.h> | |
dd2f6965 | 29 | |
dd2f6965 ML |
30 | void mx31_uart1_hw_init(void) |
31 | { | |
32 | /* setup pins for UART1 */ | |
33 | mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); | |
34 | mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); | |
35 | mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); | |
36 | mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); | |
37 | } | |
dd2f6965 | 38 | |
d121d201 HR |
39 | void mx31_uart2_hw_init(void) |
40 | { | |
41 | /* setup pins for UART2 */ | |
42 | mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); | |
43 | mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); | |
44 | mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); | |
45 | mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); | |
46 | } | |
d121d201 | 47 | |
dd2f6965 | 48 | #ifdef CONFIG_MXC_SPI |
d121d201 HR |
49 | /* |
50 | * Note: putting several spi setups here makes no sense as they may differ | |
51 | * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) | |
52 | */ | |
dd2f6965 ML |
53 | void mx31_spi2_hw_init(void) |
54 | { | |
55 | /* SPI2 */ | |
56 | mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); | |
57 | mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); | |
58 | mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); | |
59 | mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); | |
60 | mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); | |
61 | mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); | |
62 | mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); | |
63 | ||
64 | /* start SPI2 clock */ | |
65 | __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); | |
66 | } | |
67 | #endif |