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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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7 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/imx-regs.h>
543d2479 12#include <asm/arch/crm_regs.h>
31bb50f8 13
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14/* General purpose timers bitfields */
15#define GPTCR_SWR (1<<15) /* Software reset */
16#define GPTCR_FRR (1<<9) /* Freerun / restart */
543d2479 17#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
b9bb0531 18#define GPTCR_TEN (1) /* Timer enable */
31bb50f8 19
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20/*
21 * nothing really to do with interrupts, just starts up a counter.
22 * The 32KHz 32-bit timer overruns in 134217 seconds
23 */
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24int timer_init(void)
25{
26 int i;
27 struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
543d2479 28 struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
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29
30 /* setup GP Timer 1 */
31 writel(GPTCR_SWR, &gpt->ctrl);
b9bb0531 32
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33 writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
34
35 for (i = 0; i < 100; i++)
36 writel(0, &gpt->ctrl); /* We have no udelay by now */
37 writel(0, &gpt->pre); /* prescaler = 1 */
38 /* Freerun Mode, 32KHz input */
39 writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
40 &gpt->ctrl);
41 writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
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42
43 return 0;
44}