]>
Commit | Line | Data |
---|---|---|
9b07773f | 1 | /* |
678e008c | 2 | * armboot - Startup Code for ARM1176 CPU-core |
9b07773f GL |
3 | * |
4 | * Copyright (c) 2007 Samsung Electronics | |
5 | * | |
6 | * Copyright (C) 2008 | |
7 | * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | * | |
27 | * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) | |
28 | * 2007-09-21 - Added MoviNAND and OneNAND boot codes by | |
29 | * jsgood (jsgood.yang@samsung.com) | |
30 | * Base codes by scsuh (sc.suh) | |
31 | */ | |
32 | ||
25ddd1fb | 33 | #include <asm-offsets.h> |
9b07773f GL |
34 | #include <config.h> |
35 | #include <version.h> | |
36 | #ifdef CONFIG_ENABLE_MMU | |
37 | #include <asm/proc/domain.h> | |
38 | #endif | |
9b07773f | 39 | |
6d0f6bcf JCPV |
40 | #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) |
41 | #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE | |
9b07773f GL |
42 | #endif |
43 | ||
44 | /* | |
45 | ************************************************************************* | |
46 | * | |
47 | * Jump vector table as in table 3.1 in [1] | |
48 | * | |
49 | ************************************************************************* | |
50 | */ | |
51 | ||
52 | .globl _start | |
53 | _start: b reset | |
54 | #ifndef CONFIG_NAND_SPL | |
55 | ldr pc, _undefined_instruction | |
56 | ldr pc, _software_interrupt | |
57 | ldr pc, _prefetch_abort | |
58 | ldr pc, _data_abort | |
59 | ldr pc, _not_used | |
60 | ldr pc, _irq | |
61 | ldr pc, _fiq | |
62 | ||
63 | _undefined_instruction: | |
64 | .word undefined_instruction | |
65 | _software_interrupt: | |
66 | .word software_interrupt | |
67 | _prefetch_abort: | |
68 | .word prefetch_abort | |
69 | _data_abort: | |
70 | .word data_abort | |
71 | _not_used: | |
72 | .word not_used | |
73 | _irq: | |
74 | .word irq | |
75 | _fiq: | |
76 | .word fiq | |
77 | _pad: | |
78 | .word 0x12345678 /* now 16*4=64 */ | |
79 | #else | |
80 | . = _start + 64 | |
81 | #endif | |
82 | ||
83 | .global _end_vect | |
84 | _end_vect: | |
85 | .balignl 16,0xdeadbeef | |
86 | /* | |
87 | ************************************************************************* | |
88 | * | |
89 | * Startup Code (reset vector) | |
90 | * | |
91 | * do important init only if we don't start from memory! | |
92 | * setup Memory and board specific bits prior to relocation. | |
93 | * relocate armboot to ram | |
94 | * setup stack | |
95 | * | |
96 | ************************************************************************* | |
97 | */ | |
98 | ||
a51dd67a | 99 | .globl _TEXT_BASE |
9b07773f | 100 | _TEXT_BASE: |
14d0a02a | 101 | .word CONFIG_SYS_TEXT_BASE |
9b07773f GL |
102 | |
103 | /* | |
104 | * Below variable is very important because we use MMU in U-Boot. | |
105 | * Without it, we cannot run code correctly before MMU is ON. | |
106 | * by scsuh. | |
107 | */ | |
108 | _TEXT_PHY_BASE: | |
6d0f6bcf | 109 | .word CONFIG_SYS_PHY_UBOOT_BASE |
9b07773f | 110 | |
9b07773f GL |
111 | /* |
112 | * These are defined in the board-specific linker script. | |
ea34c9d6 DA |
113 | * Subtracting _start from them lets the linker put their |
114 | * relative position in the executable instead of leaving | |
115 | * them null. | |
9b07773f | 116 | */ |
9b07773f | 117 | |
ea34c9d6 DA |
118 | .globl _bss_start_ofs |
119 | _bss_start_ofs: | |
120 | .word __bss_start - _start | |
9b07773f | 121 | |
ea34c9d6 DA |
122 | .globl _bss_end_ofs |
123 | _bss_end_ofs: | |
44c6e659 | 124 | .word __bss_end__ - _start |
a51dd67a | 125 | |
ea34c9d6 DA |
126 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ |
127 | .globl IRQ_STACK_START_IN | |
128 | IRQ_STACK_START_IN: | |
129 | .word 0x0badc0de | |
a51dd67a HS |
130 | |
131 | /* | |
132 | * the actual reset code | |
133 | */ | |
134 | ||
135 | reset: | |
136 | /* | |
137 | * set the cpu to SVC32 mode | |
138 | */ | |
139 | mrs r0, cpsr | |
140 | bic r0, r0, #0x3f | |
141 | orr r0, r0, #0xd3 | |
142 | msr cpsr, r0 | |
143 | ||
144 | /* | |
145 | ************************************************************************* | |
146 | * | |
147 | * CPU_init_critical registers | |
148 | * | |
149 | * setup important registers | |
150 | * setup memory timing | |
151 | * | |
152 | ************************************************************************* | |
153 | */ | |
154 | /* | |
155 | * we do sys-critical inits only at reboot, | |
156 | * not when booting from ram! | |
157 | */ | |
158 | cpu_init_crit: | |
159 | /* | |
160 | * When booting from NAND - it has definitely been a reset, so, no need | |
161 | * to flush caches and disable the MMU | |
162 | */ | |
163 | #ifndef CONFIG_NAND_SPL | |
164 | /* | |
165 | * flush v4 I/D caches | |
166 | */ | |
167 | mov r0, #0 | |
168 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ | |
169 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ | |
170 | ||
171 | /* | |
172 | * disable MMU stuff and caches | |
173 | */ | |
174 | mrc p15, 0, r0, c1, c0, 0 | |
175 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) | |
176 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) | |
177 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align | |
178 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache | |
179 | ||
180 | /* Prepare to disable the MMU */ | |
181 | adr r2, mmu_disable_phys | |
14d0a02a | 182 | sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) |
a51dd67a HS |
183 | b mmu_disable |
184 | ||
185 | .align 5 | |
186 | /* Run in a single cache-line */ | |
187 | mmu_disable: | |
188 | mcr p15, 0, r0, c1, c0, 0 | |
189 | nop | |
190 | nop | |
191 | mov pc, r2 | |
192 | mmu_disable_phys: | |
193 | ||
194 | #ifdef CONFIG_DISABLE_TCM | |
195 | /* | |
196 | * Disable the TCMs | |
197 | */ | |
198 | mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ | |
199 | cmp r0, #0 | |
200 | beq skip_tcmdisable | |
201 | mov r1, #0 | |
202 | mov r2, #1 | |
203 | tst r0, r2 | |
204 | mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ | |
205 | tst r0, r2, LSL #16 | |
206 | mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ | |
207 | skip_tcmdisable: | |
208 | #endif | |
209 | #endif | |
210 | ||
211 | #ifdef CONFIG_PERIPORT_REMAP | |
212 | /* Peri port setup */ | |
213 | ldr r0, =CONFIG_PERIPORT_BASE | |
214 | orr r0, r0, #CONFIG_PERIPORT_SIZE | |
215 | mcr p15,0,r0,c15,c2,4 | |
216 | #endif | |
217 | ||
218 | /* | |
219 | * Go setup Memory and board specific bits prior to relocation. | |
220 | */ | |
221 | bl lowlevel_init /* go setup pll,mux,memory */ | |
222 | ||
223 | /* Set stackpointer in internal RAM to call board_init_f */ | |
224 | call_board_init_f: | |
225 | ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) | |
296cae73 | 226 | bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ |
a51dd67a HS |
227 | ldr r0,=0x00000000 |
228 | bl board_init_f | |
229 | ||
230 | /*------------------------------------------------------------------------------*/ | |
231 | ||
232 | /* | |
233 | * void relocate_code (addr_sp, gd, addr_moni) | |
234 | * | |
235 | * This "function" does not return, instead it continues in RAM | |
236 | * after relocating the monitor code. | |
237 | * | |
238 | */ | |
239 | .globl relocate_code | |
240 | relocate_code: | |
241 | mov r4, r0 /* save addr_sp */ | |
242 | mov r5, r1 /* save addr of gd */ | |
243 | mov r6, r2 /* save addr of destination */ | |
a51dd67a HS |
244 | |
245 | /* Set up the stack */ | |
246 | stack_setup: | |
247 | mov sp, r4 | |
248 | ||
249 | adr r0, _start | |
a1a47d3c AB |
250 | cmp r0, r6 |
251 | beq clear_bss /* skip relocation */ | |
a78fb68f | 252 | mov r1, r6 /* r1 <- scratch for copy_loop */ |
ea34c9d6 DA |
253 | ldr r3, _bss_start_ofs |
254 | add r2, r0, r3 /* r2 <- source end address */ | |
a51dd67a | 255 | |
a51dd67a HS |
256 | copy_loop: |
257 | ldmia r0!, {r9-r10} /* copy from source address [r0] */ | |
a78fb68f | 258 | stmia r1!, {r9-r10} /* copy to target address [r1] */ |
da90d4ce AA |
259 | cmp r0, r2 /* until source end address [r2] */ |
260 | blo copy_loop | |
a51dd67a HS |
261 | |
262 | #ifndef CONFIG_PRELOADER | |
ea34c9d6 DA |
263 | /* |
264 | * fix .rel.dyn relocations | |
265 | */ | |
266 | ldr r0, _TEXT_BASE /* r0 <- Text base */ | |
a78fb68f | 267 | sub r9, r6, r0 /* r9 <- relocation offset */ |
ea34c9d6 DA |
268 | ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ |
269 | add r10, r10, r0 /* r10 <- sym table in FLASH */ | |
270 | ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ | |
271 | add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ | |
272 | ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ | |
273 | add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ | |
a51dd67a | 274 | fixloop: |
e42a7dff AA |
275 | ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ |
276 | add r0, r0, r9 /* r0 <- location to fix up in RAM */ | |
ea34c9d6 | 277 | ldr r1, [r2, #4] |
1f52d89f AB |
278 | and r7, r1, #0xff |
279 | cmp r7, #23 /* relative fixup? */ | |
ea34c9d6 | 280 | beq fixrel |
1f52d89f | 281 | cmp r7, #2 /* absolute fixup? */ |
ea34c9d6 DA |
282 | beq fixabs |
283 | /* ignore unknown type of fixup */ | |
284 | b fixnext | |
285 | fixabs: | |
286 | /* absolute fix: set location to (offset) symbol value */ | |
287 | mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ | |
288 | add r1, r10, r1 /* r1 <- address of symbol in table */ | |
289 | ldr r1, [r1, #4] /* r1 <- symbol value */ | |
3600945b | 290 | add r1, r1, r9 /* r1 <- relocated sym addr */ |
ea34c9d6 DA |
291 | b fixnext |
292 | fixrel: | |
293 | /* relative fix: increase location by offset */ | |
294 | ldr r1, [r0] | |
295 | add r1, r1, r9 | |
296 | fixnext: | |
297 | str r1, [r0] | |
e42a7dff | 298 | add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ |
a51dd67a | 299 | cmp r2, r3 |
ea34c9d6 | 300 | blo fixloop |
a51dd67a | 301 | #endif |
a51dd67a HS |
302 | |
303 | #ifdef CONFIG_ENABLE_MMU | |
304 | enable_mmu: | |
305 | /* enable domain access */ | |
306 | ldr r5, =0x0000ffff | |
307 | mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ | |
308 | ||
309 | /* Set the TTB register */ | |
310 | ldr r0, _mmu_table_base | |
311 | ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE | |
312 | ldr r2, =0xfff00000 | |
313 | bic r0, r0, r2 | |
314 | orr r1, r0, r1 | |
315 | mcr p15, 0, r1, c2, c0, 0 | |
316 | ||
317 | /* Enable the MMU */ | |
318 | mrc p15, 0, r0, c1, c0, 0 | |
319 | orr r0, r0, #1 /* Set CR_M to enable MMU */ | |
320 | ||
321 | /* Prepare to enable the MMU */ | |
322 | adr r1, skip_hw_init | |
323 | and r1, r1, #0x3fc | |
324 | ldr r2, _TEXT_BASE | |
325 | ldr r3, =0xfff00000 | |
326 | and r2, r2, r3 | |
327 | orr r2, r2, r1 | |
328 | b mmu_enable | |
329 | ||
330 | .align 5 | |
331 | /* Run in a single cache-line */ | |
332 | mmu_enable: | |
333 | ||
334 | mcr p15, 0, r0, c1, c0, 0 | |
335 | nop | |
336 | nop | |
337 | mov pc, r2 | |
338 | skip_hw_init: | |
339 | #endif | |
340 | ||
341 | clear_bss: | |
342 | #ifndef CONFIG_PRELOADER | |
ea34c9d6 DA |
343 | ldr r0, _bss_start_ofs |
344 | ldr r1, _bss_end_ofs | |
a78fb68f | 345 | mov r4, r6 /* reloc addr */ |
a51dd67a | 346 | add r0, r0, r4 |
a51dd67a HS |
347 | add r1, r1, r4 |
348 | mov r2, #0x00000000 /* clear */ | |
349 | ||
350 | clbss_l:str r2, [r0] /* clear loop... */ | |
351 | add r0, r0, #4 | |
352 | cmp r0, r1 | |
353 | bne clbss_l | |
354 | ||
355 | bl coloured_LED_init | |
356 | bl red_LED_on | |
357 | #endif | |
358 | ||
359 | /* | |
360 | * We are done. Do not return, instead branch to second part of board | |
361 | * initialization, now running from RAM. | |
362 | */ | |
363 | #ifdef CONFIG_NAND_SPL | |
364 | ldr pc, _nand_boot | |
365 | ||
366 | _nand_boot: .word nand_boot | |
367 | #else | |
ea34c9d6 DA |
368 | ldr r0, _board_init_r_ofs |
369 | adr r1, _start | |
370 | add lr, r0, r1 | |
ea34c9d6 | 371 | add lr, lr, r9 |
a51dd67a HS |
372 | /* setup parameters for board_init_r */ |
373 | mov r0, r5 /* gd_t */ | |
a78fb68f | 374 | mov r1, r6 /* dest_addr */ |
a51dd67a | 375 | /* jump to it ... */ |
a51dd67a HS |
376 | mov pc, lr |
377 | ||
ea34c9d6 DA |
378 | _board_init_r_ofs: |
379 | .word board_init_r - _start | |
a51dd67a HS |
380 | #endif |
381 | ||
e42a7dff AA |
382 | _rel_dyn_start_ofs: |
383 | .word __rel_dyn_start - _start | |
384 | _rel_dyn_end_ofs: | |
385 | .word __rel_dyn_end - _start | |
386 | _dynsym_start_ofs: | |
387 | .word __dynsym_start - _start | |
388 | ||
9b07773f GL |
389 | #ifdef CONFIG_ENABLE_MMU |
390 | _mmu_table_base: | |
391 | .word mmu_table | |
392 | #endif | |
393 | ||
394 | #ifndef CONFIG_NAND_SPL | |
395 | /* | |
396 | * we assume that cache operation is done before. (eg. cleanup_before_linux()) | |
397 | * actually, we don't need to do anything about cache if not use d-cache in | |
398 | * U-Boot. So, in this function we clean only MMU. by scsuh | |
399 | * | |
400 | * void theLastJump(void *kernel, int arch_num, uint boot_params); | |
401 | */ | |
402 | #ifdef CONFIG_ENABLE_MMU | |
403 | .globl theLastJump | |
404 | theLastJump: | |
405 | mov r9, r0 | |
406 | ldr r3, =0xfff00000 | |
407 | ldr r4, _TEXT_PHY_BASE | |
408 | adr r5, phy_last_jump | |
409 | bic r5, r5, r3 | |
410 | orr r5, r5, r4 | |
411 | mov pc, r5 | |
412 | phy_last_jump: | |
413 | /* | |
414 | * disable MMU stuff | |
415 | */ | |
416 | mrc p15, 0, r0, c1, c0, 0 | |
417 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ | |
418 | bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ | |
419 | orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ | |
420 | orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ | |
421 | mcr p15, 0, r0, c1, c0, 0 | |
422 | ||
423 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ | |
424 | ||
425 | mov r0, #0 | |
426 | mov pc, r9 | |
427 | #endif | |
678e008c CC |
428 | |
429 | ||
9b07773f GL |
430 | /* |
431 | ************************************************************************* | |
432 | * | |
433 | * Interrupt handling | |
434 | * | |
435 | ************************************************************************* | |
436 | */ | |
437 | @ | |
438 | @ IRQ stack frame. | |
439 | @ | |
440 | #define S_FRAME_SIZE 72 | |
441 | ||
442 | #define S_OLD_R0 68 | |
443 | #define S_PSR 64 | |
444 | #define S_PC 60 | |
445 | #define S_LR 56 | |
446 | #define S_SP 52 | |
447 | ||
448 | #define S_IP 48 | |
449 | #define S_FP 44 | |
450 | #define S_R10 40 | |
451 | #define S_R9 36 | |
452 | #define S_R8 32 | |
453 | #define S_R7 28 | |
454 | #define S_R6 24 | |
455 | #define S_R5 20 | |
456 | #define S_R4 16 | |
457 | #define S_R3 12 | |
458 | #define S_R2 8 | |
459 | #define S_R1 4 | |
460 | #define S_R0 0 | |
461 | ||
462 | #define MODE_SVC 0x13 | |
463 | #define I_BIT 0x80 | |
464 | ||
465 | /* | |
466 | * use bad_save_user_regs for abort/prefetch/undef/swi ... | |
467 | */ | |
468 | ||
469 | .macro bad_save_user_regs | |
470 | /* carve out a frame on current user stack */ | |
471 | sub sp, sp, #S_FRAME_SIZE | |
472 | /* Save user registers (now in svc mode) r0-r12 */ | |
473 | stmia sp, {r0 - r12} | |
474 | ||
a51dd67a | 475 | ldr r2, IRQ_STACK_START_IN |
9b07773f GL |
476 | /* get values for "aborted" pc and cpsr (into parm regs) */ |
477 | ldmia r2, {r2 - r3} | |
478 | /* grab pointer to old stack */ | |
479 | add r0, sp, #S_FRAME_SIZE | |
480 | ||
481 | add r5, sp, #S_SP | |
482 | mov r1, lr | |
483 | /* save sp_SVC, lr_SVC, pc, cpsr */ | |
484 | stmia r5, {r0 - r3} | |
485 | /* save current stack into r0 (param register) */ | |
486 | mov r0, sp | |
487 | .endm | |
488 | ||
489 | .macro get_bad_stack | |
a51dd67a | 490 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
9b07773f GL |
491 | |
492 | /* save caller lr in position 0 of saved stack */ | |
493 | str lr, [r13] | |
494 | /* get the spsr */ | |
495 | mrs lr, spsr | |
496 | /* save spsr in position 1 of saved stack */ | |
497 | str lr, [r13, #4] | |
498 | ||
499 | /* prepare SVC-Mode */ | |
500 | mov r13, #MODE_SVC | |
501 | @ msr spsr_c, r13 | |
502 | /* switch modes, make sure moves will execute */ | |
503 | msr spsr, r13 | |
504 | /* capture return pc */ | |
505 | mov lr, pc | |
506 | /* jump to next instruction & switch modes. */ | |
507 | movs pc, lr | |
508 | .endm | |
509 | ||
510 | .macro get_bad_stack_swi | |
511 | /* space on current stack for scratch reg. */ | |
512 | sub r13, r13, #4 | |
513 | /* save R0's value. */ | |
514 | str r0, [r13] | |
a51dd67a | 515 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
9b07773f GL |
516 | /* save caller lr in position 0 of saved stack */ |
517 | str lr, [r0] | |
518 | /* get the spsr */ | |
519 | mrs r0, spsr | |
520 | /* save spsr in position 1 of saved stack */ | |
521 | str lr, [r0, #4] | |
522 | /* restore r0 */ | |
523 | ldr r0, [r13] | |
524 | /* pop stack entry */ | |
525 | add r13, r13, #4 | |
526 | .endm | |
527 | ||
528 | /* | |
529 | * exception handlers | |
530 | */ | |
531 | .align 5 | |
532 | undefined_instruction: | |
533 | get_bad_stack | |
534 | bad_save_user_regs | |
535 | bl do_undefined_instruction | |
536 | ||
537 | .align 5 | |
538 | software_interrupt: | |
539 | get_bad_stack_swi | |
540 | bad_save_user_regs | |
541 | bl do_software_interrupt | |
542 | ||
543 | .align 5 | |
544 | prefetch_abort: | |
545 | get_bad_stack | |
546 | bad_save_user_regs | |
547 | bl do_prefetch_abort | |
548 | ||
549 | .align 5 | |
550 | data_abort: | |
551 | get_bad_stack | |
552 | bad_save_user_regs | |
553 | bl do_data_abort | |
554 | ||
555 | .align 5 | |
556 | not_used: | |
557 | get_bad_stack | |
558 | bad_save_user_regs | |
559 | bl do_not_used | |
560 | ||
561 | .align 5 | |
562 | irq: | |
563 | get_bad_stack | |
564 | bad_save_user_regs | |
565 | bl do_irq | |
566 | ||
567 | .align 5 | |
568 | fiq: | |
569 | get_bad_stack | |
570 | bad_save_user_regs | |
571 | bl do_fiq | |
572 | #endif /* CONFIG_NAND_SPL */ |