projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| fe8c2806 WD |
2 | /* |
| 3 | * armboot - Startup Code for ARM720 CPU-core | |
| 4 | * | |
| fa82f871 AA |
5 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 6 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> | |
| fe8c2806 WD |
7 | */ |
| 8 | ||
| 25ddd1fb | 9 | #include <asm-offsets.h> |
| fe8c2806 | 10 | #include <config.h> |
| fe8c2806 | 11 | |
| fe8c2806 WD |
12 | /* |
| 13 | ************************************************************************* | |
| 14 | * | |
| 15 | * Startup Code (reset vector) | |
| 16 | * | |
| f6e20fc6 | 17 | * do important init only if we don't start from RAM! |
| fe8c2806 WD |
18 | * relocate armboot to ram |
| 19 | * setup stack | |
| 20 | * jump to second stage | |
| 21 | * | |
| 22 | ************************************************************************* | |
| 23 | */ | |
| 24 | ||
| 41623c91 | 25 | .globl reset |
| abef7b85 HS |
26 | |
| 27 | reset: | |
| 28 | /* | |
| 29 | * set the cpu to SVC32 mode | |
| 30 | */ | |
| 31 | mrs r0,cpsr | |
| 32 | bic r0,r0,#0x1f | |
| 33 | orr r0,r0,#0xd3 | |
| 34 | msr cpsr,r0 | |
| 35 | ||
| 36 | /* | |
| 37 | * we do sys-critical inits only at reboot, | |
| 38 | * not when booting from ram! | |
| 39 | */ | |
| a2ac2b96 TR |
40 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ |
| 41 | !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) | |
| abef7b85 HS |
42 | bl cpu_init_crit |
| 43 | #endif | |
| 44 | ||
| e05e5de7 | 45 | bl _main |
| abef7b85 HS |
46 | |
| 47 | /*------------------------------------------------------------------------------*/ | |
| 48 | ||
| e05e5de7 AA |
49 | .globl c_runtime_cpu_setup |
| 50 | c_runtime_cpu_setup: | |
| 51 | ||
| 52 | mov pc, lr | |
| 53 | ||
| fe8c2806 WD |
54 | /* |
| 55 | ************************************************************************* | |
| 56 | * | |
| 57 | * CPU_init_critical registers | |
| 58 | * | |
| 59 | * setup important registers | |
| 60 | * setup memory timing | |
| 61 | * | |
| 62 | ************************************************************************* | |
| 63 | */ | |
| 64 | ||
| a2ac2b96 TR |
65 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ |
| 66 | !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) | |
| fe8c2806 | 67 | cpu_init_crit: |
| fe8c2806 | 68 | |
| 87cb6862 | 69 | mov ip, lr |
| fe8c2806 WD |
70 | /* |
| 71 | * before relocating, we have to setup RAM timing | |
| f6e20fc6 | 72 | * because memory timing is board-dependent, you will |
| 400558b5 | 73 | * find a lowlevel_init.S in your board directory. |
| fe8c2806 | 74 | */ |
| 400558b5 | 75 | bl lowlevel_init |
| fe8c2806 WD |
76 | mov lr, ip |
| 77 | ||
| 78 | mov pc, lr | |
| a2ac2b96 | 79 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |