[people/ms/u-boot.git] / arch / arm / cpu / arm920t / start.S

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm-offsets.h>
#include <common.h>
#include <config.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start:	b	start_code
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*
 *************************************************************************
 *
 * Startup Code (called from the ARM reset exception vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 *************************************************************************
 */

.globl _TEXT_BASE
_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

/*
 * These are defined in the board-specific linker script.
 * Subtracting _start from them lets the linker put their
 * relative position in the executable instead of leaving
 * them null.
 */
.globl _bss_start_ofs
_bss_start_ofs:
	.word __bss_start - _start

.globl _bss_end_ofs
_bss_end_ofs:
	.word __bss_end - _start

.globl _end_ofs
_end_ofs:
	.word _end - _start

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif

/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
	.word	0x0badc0de

/*
 * the actual start code
 */

start_code:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0, cpsr
	bic	r0, r0, #0x1f
	orr	r0, r0, #0xd3
	msr	cpsr, r0

#if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
	/*
	 * relocate exception table
	 */
	ldr	r0, =_start
	ldr	r1, =0x0
	mov	r2, #16
copyex:
	subs	r2, r2, #1
	ldr	r3, [r0], #4
	str	r3, [r1], #4
	bne	copyex
#endif

#ifdef CONFIG_S3C24X0
	/* turn off the watchdog */

# if defined(CONFIG_S3C2400)
#  define pWTCON	0x15300000
#  define INTMSK	0x14400008	/* Interrupt-Controller base addresses */
#  define CLKDIVN	0x14800014	/* clock divisor register */
#else
#  define pWTCON	0x53000000
#  define INTMSK	0x4A000008	/* Interrupt-Controller base addresses */
#  define INTSUBMSK	0x4A00001C
#  define CLKDIVN	0x4C000014	/* clock divisor register */
# endif

	ldr	r0, =pWTCON
	mov	r1, #0x0
	str	r1, [r0]

	/*
	 * mask all IRQs by setting all bits in the INTMR - default
	 */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
# if defined(CONFIG_S3C2410)
	ldr	r1, =0x3ff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
# endif

	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
#endif	/* CONFIG_S3C24X0 */

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
	bl	cpu_init_crit
#endif

	bl	_main

/*------------------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 */
	.globl	relocate_code
relocate_code:
	mov	r4, r0	/* save addr_sp */
	mov	r5, r1	/* save addr of gd */
	mov	r6, r2	/* save addr of destination */

	adr	r0, _start
	cmp	r0, r6
	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
	beq	relocate_done		/* skip relocation */
	mov	r1, r6			/* r1 <- scratch for copy_loop */
	ldr	r3, _bss_start_ofs
	add	r2, r0, r3		/* r2 <- source end address	    */

copy_loop:
	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end address [r2]    */
	blo	copy_loop

#ifndef CONFIG_SPL_BUILD
	/*
	 * fix .rel.dyn relocations
	 */
	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
	sub	r9, r6, r0		/* r9 <- relocation offset */
	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
	add	r10, r10, r0		/* r10 <- sym table in FLASH */
	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
fixloop:
	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
	ldr	r1, [r2, #4]
	and	r7, r1, #0xff
	cmp	r7, #23			/* relative fixup? */
	beq	fixrel
	cmp	r7, #2			/* absolute fixup? */
	beq	fixabs
	/* ignore unknown type of fixup */
	b	fixnext
fixabs:
	/* absolute fix: set location to (offset) symbol value */
	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
	add	r1, r10, r1		/* r1 <- address of symbol in table */
	ldr	r1, [r1, #4]		/* r1 <- symbol value */
	add	r1, r1, r9		/* r1 <- relocated sym addr */
	b	fixnext
fixrel:
	/* relative fix: increase location by offset */
	ldr	r1, [r0]
	add	r1, r1, r9
fixnext:
	str	r1, [r0]
	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
	cmp	r2, r3
	blo	fixloop
#endif

relocate_done:

	mov	pc, lr

_rel_dyn_start_ofs:
	.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
	.word __rel_dyn_end - _start
_dynsym_start_ofs:
	.word __dynsym_start - _start

	.globl	c_runtime_cpu_setup
c_runtime_cpu_setup:

	mov	pc, lr

/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */


#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a lowlevel_init.S in your board directory.
	 */
	mov	ip, lr

	bl	lowlevel_init

	mov	lr, ip
	mov	pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC	0x13
#define I_BIT		0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	ldr	r2, IRQ_STACK_START_IN
	ldmia	r2, {r2 - r3}			@ get pc, cpsr
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add	r7, sp, #S_PC
	stmdb	r7, {sp, lr}^			@ Calling SP, LR
	str	lr, [r7, #0]			@ Save calling PC
	mrs	r6, spsr
	str	r6, [r7, #4]			@ Save CPSR
	str	r0, [r7, #8]			@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	/* return & move spsr_svc into cpsr */
	subs	pc, lr, #4
	.endm

	.macro get_bad_stack
	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str	lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/*
 * exception handlers
 */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* armboot - Startup Code for ARM920 CPU-core
	3	*
fa82f871 AA	4	* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
fa82f871 AA	5	* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb	6	* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
fe8c2806 WD	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
25ddd1fb	27	#include <asm-offsets.h>
9689ddcc	28	#include <common.h>
fe8c2806	29	#include <config.h>
fe8c2806 WD	30
	31	/*
	32	*************************************************************************
	33	*
	34	* Jump vector table as in table 3.1 in [1]
	35	*
	36	*************************************************************************
	37	*/
	38
	39
	40	.globl _start
d67cce2d	41	_start: b start_code
fe8c2806 WD	42	ldr pc, _undefined_instruction
	43	ldr pc, _software_interrupt
	44	ldr pc, _prefetch_abort
	45	ldr pc, _data_abort
	46	ldr pc, _not_used
	47	ldr pc, _irq
	48	ldr pc, _fiq
	49
	50	_undefined_instruction: .word undefined_instruction
	51	_software_interrupt: .word software_interrupt
	52	_prefetch_abort: .word prefetch_abort
	53	_data_abort: .word data_abort
	54	_not_used: .word not_used
	55	_irq: .word irq
	56	_fiq: .word fiq
	57
	58	.balignl 16,0xdeadbeef
	59
	60
	61	/*
	62	*************************************************************************
	63	*
80767a6c	64	* Startup Code (called from the ARM reset exception vector)
fe8c2806 WD	65	*
	66	* do important init only if we don't start from memory!
	67	* relocate armboot to ram
	68	* setup stack
	69	* jump to second stage
	70	*
	71	*************************************************************************
	72	*/
	73
cc7cdcbd	74	.globl _TEXT_BASE
fe8c2806	75	_TEXT_BASE:
14d0a02a	76	.word CONFIG_SYS_TEXT_BASE
fe8c2806	77
fe8c2806	78	/*
f6e20fc6	79	* These are defined in the board-specific linker script.
3336ca60 AA	80	* Subtracting _start from them lets the linker put their
	81	* relative position in the executable instead of leaving
	82	* them null.
fe8c2806	83	*/
3336ca60 AA	84	.globl _bss_start_ofs
	85	_bss_start_ofs:
	86	.word __bss_start - _start
f6e20fc6	87
3336ca60 AA	88	.globl _bss_end_ofs
3336ca60 AA	89	_bss_end_ofs:
3929fb0a	90	.word __bss_end - _start
fe8c2806	91
f326cbba PYC	92	.globl _end_ofs
	93	_end_ofs:
	94	.word _end - _start
	95
fe8c2806 WD	96	#ifdef CONFIG_USE_IRQ
	97	/* IRQ stack memory (calculated at run-time) */
	98	.globl IRQ_STACK_START
	99	IRQ_STACK_START:
	100	.word 0x0badc0de
	101
	102	/* IRQ stack memory (calculated at run-time) */
	103	.globl FIQ_STACK_START
	104	FIQ_STACK_START:
	105	.word 0x0badc0de
	106	#endif
	107
cc7cdcbd HS	108	/* IRQ stack memory (calculated at run-time) + 8 bytes */
	109	.globl IRQ_STACK_START_IN
	110	IRQ_STACK_START_IN:
	111	.word 0x0badc0de
	112
fe8c2806	113	/*
80767a6c	114	* the actual start code
fe8c2806 WD	115	*/
fe8c2806 WD	116
80767a6c	117	start_code:
fe8c2806 WD	118	/*
	119	* set the cpu to SVC32 mode
	120	*/
d67cce2d	121	mrs r0, cpsr
	122	bic r0, r0, #0x1f
	123	orr r0, r0, #0xd3
	124	msr cpsr, r0
80767a6c	125
ed3b18e0	126	#if defined(CONFIG_AT91RM9200DK) \|\| defined(CONFIG_AT91RM9200EK)
d4fc6012	127	/*
80767a6c	128	* relocate exception table
d4fc6012 PP	129	*/
	130	ldr r0, =_start
	131	ldr r1, =0x0
	132	mov r2, #16
	133	copyex:
	134	subs r2, r2, #1
	135	ldr r3, [r0], #4
	136	str r3, [r1], #4
	137	bne copyex
	138	#endif
	139
ac67804f	140	#ifdef CONFIG_S3C24X0
80767a6c PP	141	/* turn off the watchdog */
	142
	143	# if defined(CONFIG_S3C2400)
d67cce2d	144	# define pWTCON 0x15300000
16263087	145	# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
80767a6c PP	146	# define CLKDIVN 0x14800014 /* clock divisor register */
80767a6c PP	147	#else
d67cce2d	148	# define pWTCON 0x53000000
16263087	149	# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
80767a6c PP	150	# define INTSUBMSK 0x4A00001C
	151	# define CLKDIVN 0x4C000014 /* clock divisor register */
	152	# endif
	153
d67cce2d	154	ldr r0, =pWTCON
	155	mov r1, #0x0
	156	str r1, [r0]
fe8c2806 WD	157
	158	/*
	159	* mask all IRQs by setting all bits in the INTMR - default
	160	*/
	161	mov r1, #0xffffffff
	162	ldr r0, =INTMSK
	163	str r1, [r0]
281e00a3	164	# if defined(CONFIG_S3C2410)
fe8c2806 WD	165	ldr r1, =0x3ff
	166	ldr r0, =INTSUBMSK
	167	str r1, [r0]
281e00a3	168	# endif
fe8c2806 WD	169
	170	/* FCLK:HCLK:PCLK = 1:2:4 */
	171	/* default FCLK is 120 MHz ! */
	172	ldr r0, =CLKDIVN
	173	mov r1, #3
	174	str r1, [r0]
ac67804f	175	#endif /* CONFIG_S3C24X0 */
fe8c2806 WD	176
	177	/*
	178	* we do sys-critical inits only at reboot,
	179	* not when booting from ram!
	180	*/
8aa1a2d1	181	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fe8c2806 WD	182	bl cpu_init_crit
	183	#endif
	184
e05e5de7	185	bl _main
cc7cdcbd HS	186
	187	/------------------------------------------------------------------------------/
	188
	189	/*
	190	* void relocate_code (addr_sp, gd, addr_moni)
	191	*
	192	* This "function" does not return, instead it continues in RAM
	193	* after relocating the monitor code.
	194	*
	195	*/
	196	.globl relocate_code
	197	relocate_code:
	198	mov r4, r0 /* save addr_sp */
	199	mov r5, r1 /* save addr of gd */
	200	mov r6, r2 /* save addr of destination */
cc7cdcbd	201
cc7cdcbd	202	adr r0, _start
a1a47d3c	203	cmp r0, r6
76abfa57	204	moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
e05e5de7	205	beq relocate_done /* skip relocation */
a78fb68f	206	mov r1, r6 /* r1 <- scratch for copy_loop */
3336ca60 AA	207	ldr r3, _bss_start_ofs
3336ca60 AA	208	add r2, r0, r3 /* r2 <- source end address */
cc7cdcbd	209
cc7cdcbd HS	210	copy_loop:
cc7cdcbd HS	211	ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f	212	stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce AA	213	cmp r0, r2 /* until source end address [r2] */
da90d4ce AA	214	blo copy_loop
cc7cdcbd	215
401bb30b	216	#ifndef CONFIG_SPL_BUILD
3336ca60 AA	217	/*
	218	* fix .rel.dyn relocations
	219	*/
	220	ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f	221	sub r9, r6, r0 /* r9 <- relocation offset */
3336ca60 AA	222	ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
	223	add r10, r10, r0 /* r10 <- sym table in FLASH */
	224	ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
	225	add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
	226	ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
	227	add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
cc7cdcbd	228	fixloop:
3336ca60 AA	229	ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
	230	add r0, r0, r9 /* r0 <- location to fix up in RAM */
	231	ldr r1, [r2, #4]
1f52d89f AB	232	and r7, r1, #0xff
1f52d89f AB	233	cmp r7, #23 /* relative fixup? */
3336ca60	234	beq fixrel
1f52d89f	235	cmp r7, #2 /* absolute fixup? */
3336ca60 AA	236	beq fixabs
	237	/* ignore unknown type of fixup */
	238	b fixnext
	239	fixabs:
	240	/* absolute fix: set location to (offset) symbol value */
	241	mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
	242	add r1, r10, r1 /* r1 <- address of symbol in table */
	243	ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b	244	add r1, r1, r9 /* r1 <- relocated sym addr */
3336ca60 AA	245	b fixnext
	246	fixrel:
	247	/* relative fix: increase location by offset */
	248	ldr r1, [r0]
	249	add r1, r1, r9
	250	fixnext:
	251	str r1, [r0]
	252	add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cc7cdcbd	253	cmp r2, r3
79e63139	254	blo fixloop
cc7cdcbd	255	#endif
cc7cdcbd	256
e05e5de7	257	relocate_done:
cc7cdcbd	258
cc7cdcbd HS	259	mov pc, lr
cc7cdcbd HS	260
3336ca60 AA	261	_rel_dyn_start_ofs:
	262	.word __rel_dyn_start - _start
	263	_rel_dyn_end_ofs:
	264	.word __rel_dyn_end - _start
	265	_dynsym_start_ofs:
	266	.word __dynsym_start - _start
	267
e05e5de7 AA	268	.globl c_runtime_cpu_setup
	269	c_runtime_cpu_setup:
	270
	271	mov pc, lr
	272
fe8c2806 WD	273	/*
	274	*************************************************************************
	275	*
	276	* CPU_init_critical registers
	277	*
	278	* setup important registers
	279	* setup memory timing
	280	*
	281	*************************************************************************
	282	*/
	283
	284
db28ddb4	285	#ifndef CONFIG_SKIP_LOWLEVEL_INIT
fe8c2806 WD	286	cpu_init_crit:
	287	/*
	288	* flush v4 I/D caches
	289	*/
	290	mov r0, #0
	291	mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
	292	mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
	293
	294	/*
	295	* disable MMU stuff and caches
	296	*/
	297	mrc p15, 0, r0, c1, c0, 0
	298	bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
	299	bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
	300	orr r0, r0, #0x00000002 @ set bit 2 (A) Align
	301	orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
	302	mcr p15, 0, r0, c1, c0, 0
	303
fe8c2806 WD	304	/*
	305	* before relocating, we have to setup RAM timing
	306	* because memory timing is board-dependend, you will
400558b5	307	* find a lowlevel_init.S in your board directory.
fe8c2806 WD	308	*/
fe8c2806 WD	309	mov ip, lr
d4fc6012	310
400558b5	311	bl lowlevel_init
cb82a532	312
fe8c2806	313	mov lr, ip
fe8c2806	314	mov pc, lr
db28ddb4	315	#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
fe8c2806	316
fe8c2806 WD	317	/*
	318	*************************************************************************
	319	*
	320	* Interrupt handling
	321	*
	322	*************************************************************************
	323	*/
	324
	325	@
	326	@ IRQ stack frame.
	327	@
	328	#define S_FRAME_SIZE 72
	329
	330	#define S_OLD_R0 68
	331	#define S_PSR 64
	332	#define S_PC 60
	333	#define S_LR 56
	334	#define S_SP 52
	335
	336	#define S_IP 48
	337	#define S_FP 44
	338	#define S_R10 40
	339	#define S_R9 36
	340	#define S_R8 32
	341	#define S_R7 28
	342	#define S_R6 24
	343	#define S_R5 20
	344	#define S_R4 16
	345	#define S_R3 12
	346	#define S_R2 8
	347	#define S_R1 4
	348	#define S_R0 0
	349
d67cce2d	350	#define MODE_SVC 0x13
d67cce2d	351	#define I_BIT 0x80
fe8c2806 WD	352
	353	/*
	354	* use bad_save_user_regs for abort/prefetch/undef/swi ...
	355	* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
	356	*/
	357
	358	.macro bad_save_user_regs
	359	sub sp, sp, #S_FRAME_SIZE
	360	stmia sp, {r0 - r12} @ Calling r0-r12
cc7cdcbd	361	ldr r2, IRQ_STACK_START_IN
f07771cc	362	ldmia r2, {r2 - r3} @ get pc, cpsr
fe8c2806 WD	363	add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
	364
	365	add r5, sp, #S_SP
	366	mov r1, lr
f07771cc	367	stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
fe8c2806 WD	368	mov r0, sp
	369	.endm
	370
	371	.macro irq_save_user_regs
	372	sub sp, sp, #S_FRAME_SIZE
	373	stmia sp, {r0 - r12} @ Calling r0-r12
d67cce2d	374	add r7, sp, #S_PC
	375	stmdb r7, {sp, lr}^ @ Calling SP, LR
	376	str lr, [r7, #0] @ Save calling PC
	377	mrs r6, spsr
	378	str r6, [r7, #4] @ Save CPSR
	379	str r0, [r7, #8] @ Save OLD_R0
fe8c2806 WD	380	mov r0, sp
	381	.endm
	382
	383	.macro irq_restore_user_regs
	384	ldmia sp, {r0 - lr}^ @ Calling r0 - lr
	385	mov r0, r0
	386	ldr lr, [sp, #S_PC] @ Get PC
	387	add sp, sp, #S_FRAME_SIZE
d67cce2d	388	/* return & move spsr_svc into cpsr */
d67cce2d	389	subs pc, lr, #4
fe8c2806 WD	390	.endm
	391
	392	.macro get_bad_stack
cc7cdcbd	393	ldr r13, IRQ_STACK_START_IN @ setup our mode stack
fe8c2806 WD	394
	395	str lr, [r13] @ save caller lr / spsr
	396	mrs lr, spsr
d67cce2d	397	str lr, [r13, #4]
fe8c2806 WD	398
	399	mov r13, #MODE_SVC @ prepare SVC-Mode
	400	@ msr spsr_c, r13
	401	msr spsr, r13
	402	mov lr, pc
	403	movs pc, lr
	404	.endm
	405
	406	.macro get_irq_stack @ setup IRQ stack
	407	ldr sp, IRQ_STACK_START
	408	.endm
	409
	410	.macro get_fiq_stack @ setup FIQ stack
	411	ldr sp, FIQ_STACK_START
	412	.endm
	413
	414	/*
	415	* exception handlers
	416	*/
	417	.align 5
	418	undefined_instruction:
	419	get_bad_stack
	420	bad_save_user_regs
53677ef1	421	bl do_undefined_instruction
fe8c2806 WD	422
	423	.align 5
	424	software_interrupt:
	425	get_bad_stack
	426	bad_save_user_regs
53677ef1	427	bl do_software_interrupt
fe8c2806 WD	428
	429	.align 5
	430	prefetch_abort:
	431	get_bad_stack
	432	bad_save_user_regs
53677ef1	433	bl do_prefetch_abort
fe8c2806 WD	434
	435	.align 5
	436	data_abort:
	437	get_bad_stack
	438	bad_save_user_regs
53677ef1	439	bl do_data_abort
fe8c2806 WD	440
	441	.align 5
	442	not_used:
	443	get_bad_stack
	444	bad_save_user_regs
53677ef1	445	bl do_not_used
fe8c2806 WD	446
	447	#ifdef CONFIG_USE_IRQ
	448
	449	.align 5
	450	irq:
	451	get_irq_stack
	452	irq_save_user_regs
53677ef1	453	bl do_irq
fe8c2806 WD	454	irq_restore_user_regs
	455
	456	.align 5
	457	fiq:
	458	get_fiq_stack
	459	/* someone ought to write a more effiction fiq_save_user_regs */
	460	irq_save_user_regs
53677ef1	461	bl do_fiq
fe8c2806 WD	462	irq_restore_user_regs
	463
	464	#else
	465
	466	.align 5
	467	irq:
	468	get_bad_stack
	469	bad_save_user_regs
53677ef1	470	bl do_irq
fe8c2806 WD	471
	472	.align 5
	473	fiq:
	474	get_bad_stack
	475	bad_save_user_regs
53677ef1	476	bl do_fiq
fe8c2806 WD	477
fe8c2806 WD	478	#endif