[people/ms/u-boot.git] / arch / arm / cpu / arm926ejs / davinci / da850_lowlevel.c

/*
 * SoC-specific lowlevel code for DA850
 *
 * Copyright (C) 2011
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <common.h>
#include <nand.h>
#include <ns16550.h>
#include <post.h>
#include <asm/arch/da850_lowlevel.h>
#include <asm/arch/hardware.h>
#include <asm/arch/davinci_misc.h>
#include <asm/arch/ddr2_defs.h>
#include <asm/arch/emif_defs.h>
#include <asm/arch/pll_defs.h>

void da850_waitloop(unsigned long loopcnt)
{
	unsigned long	i;

	for (i = 0; i < loopcnt; i++)
		asm("   NOP");
}

int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
{
	if (reg == davinci_pllc0_regs)
		/* Unlock PLL registers. */
		clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);

	/*
	 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
	 * through MMR
	 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
	/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);

	/* Set PLLEN=0 => PLL BYPASS MODE */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);

	da850_waitloop(150);

	if (reg == davinci_pllc0_regs) {
		/*
		 * Select the Clock Mode bit 8 as External Clock or On Chip
		 * Oscilator
		 */
		dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
		setbits_le32(&reg->pllctl,
			(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
	}

	/* Clear PLLRST bit to reset the PLL */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);

	/* Disable the PLL output */
	setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);

	/* PLL initialization sequence */
	/*
	 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
	 * power down bit
	 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);

	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);

#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
	/* program the prediv */
	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
		writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
			&reg->prediv);
#endif

	/* Program the required multiplier value in PLLM */
	writel(pllmult, &reg->pllm);

	/* program the postdiv */
	if (reg == davinci_pllc0_regs)
		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
			&reg->postdiv);
	else
		writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
			&reg->postdiv);

	/*
	 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
	 * no GO operation is currently in progress
	 */
	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
		;

	if (reg == davinci_pllc0_regs) {
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
		writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
	} else {
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
		writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
	}

	/*
	 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
	 * transition.
	 */
	setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);

	/*
	 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
	 * (completion of phase alignment).
	 */
	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
		;

	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
	da850_waitloop(200);

	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
	setbits_le32(&reg->pllctl, PLLCTL_PLLRST);

	/* Wait for PLL to lock. See PLL spec for PLL lock time */
	da850_waitloop(2400);

	/*
	 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
	 * mode
	 */
	setbits_le32(&reg->pllctl, PLLCTL_PLLEN);


	/*
	 * clear EMIFA and EMIFB clock source settings, let them
	 * run off SYSCLK
	 */
	if (reg == davinci_pllc0_regs)
		dv_maskbits(&davinci_syscfg_regs->cfgchip3,
			~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));

	return 0;
}

int da850_ddr_setup(void)
{
	unsigned long	tmp;

	/* Enable the Clock to DDR2/mDDR */
	lpsc_on(DAVINCI_LPSC_DDR_EMIF);

	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
		/* Begin VTP Calibration */
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
		clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);

		/* Polling READY bit to see when VTP calibration is done */
		tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
		while ((tmp & VTP_READY) != VTP_READY)
			tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);

		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);

		setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
	}

	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
		(1 << DDR_SLEW_CMOSEN_BIT));

	/*
	 * SDRAM Configuration Register (SDCR):
	 * First set the BOOTUNLOCK bit to make configuration bits
	 * writeable.
	 */
	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);

	/*
	 * Write the new value of these bits and clear BOOTUNLOCK.
	 * At the same time, set the TIMUNLOCK bit to allow changing
	 * the timing registers
	 */
	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
	tmp &= ~DV_DDR_BOOTUNLOCK;
	tmp |= DV_DDR_TIMUNLOCK;
	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);

	/* write memory configuration and timing */
	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);

	/* clear the TIMUNLOCK bit and write the value of the CL field */
	tmp &= ~DV_DDR_TIMUNLOCK;
	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);

	/*
	 * LPMODEN and MCLKSTOPEN must be set!
	 * Without this bits set, PSC don;t switch states !!
	 */
	writel(CONFIG_SYS_DA850_DDR2_SDRCR |
		(1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
		(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
		&dv_ddr2_regs_ctrl->sdrcr);

	/* SyncReset the Clock to EMIF3A SDRAM */
	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
	/* Enable the Clock to EMIF3A SDRAM */
	lpsc_on(DAVINCI_LPSC_DDR_EMIF);

	/* disable self refresh */
	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
		DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);

	return 0;
}

__attribute__((weak))
void board_gpio_init(void)
{
	return;
}

/* pinmux_resource[] vector is defined in the board specific file */
extern const struct pinmux_resource pinmuxes[];
extern const int pinmuxes_size;

int arch_cpu_init(void)
{
	/* Unlock kick registers */
	writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);

	dv_maskbits(&davinci_syscfg_regs->suspsrc,
		CONFIG_SYS_DA850_SYSCFG_SUSPSRC);

	/* configure pinmux settings */
	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
		return 1;

	/* PLL setup */
	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);

	/* GPIO setup */
	board_gpio_init();

	/* setup CSn config */
#if defined(CONFIG_SYS_DA850_CS2CFG)
	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
#endif
#if defined(CONFIG_SYS_DA850_CS3CFG)
	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
#endif

	lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);

	/*
	 * Fix Power and Emulation Management Register
	 * see sprufw3a.pdf page 37 Table 24
	 */
	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
		DAVINCI_UART_PWREMU_MGMT_UTRST),
	       &davinci_uart2_ctrl_regs->pwremu_mgmt);

	da850_ddr_setup();
	return 0;
}
Commit	Line	Data
310ae55e	1	/*
effea9d1	2	* SoC-specific lowlevel code for DA850
310ae55e HS	3	*
	4	* Copyright (C) 2011
	5	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	23	*/
	24	#include <common.h>
	25	#include <nand.h>
	26	#include <ns16550.h>
	27	#include <post.h>
effea9d1	28	#include <asm/arch/da850_lowlevel.h>
310ae55e	29	#include <asm/arch/hardware.h>
65204715	30	#include <asm/arch/davinci_misc.h>
310ae55e HS	31	#include <asm/arch/ddr2_defs.h>
310ae55e HS	32	#include <asm/arch/emif_defs.h>
f3c149d6	33	#include <asm/arch/pll_defs.h>
310ae55e	34
effea9d1	35	void da850_waitloop(unsigned long loopcnt)
310ae55e HS	36	{
	37	unsigned long i;
	38
	39	for (i = 0; i < loopcnt; i++)
	40	asm(" NOP");
	41	}
	42
effea9d1	43	int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
310ae55e HS	44	{
	45	if (reg == davinci_pllc0_regs)
	46	/* Unlock PLL registers. */
f3c149d6	47	clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
310ae55e HS	48
	49	/*
	50	* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
	51	* through MMR
	52	*/
f3c149d6	53	clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
310ae55e	54	/* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
f3c149d6	55	clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
310ae55e HS	56
310ae55e HS	57	/* Set PLLEN=0 => PLL BYPASS MODE */
f3c149d6	58	clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
310ae55e	59
effea9d1	60	da850_waitloop(150);
310ae55e HS	61
	62	if (reg == davinci_pllc0_regs) {
	63	/*
	64	* Select the Clock Mode bit 8 as External Clock or On Chip
	65	* Oscilator
	66	*/
f3c149d6 HS	67	dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
	68	setbits_le32(&reg->pllctl,
	69	(CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
310ae55e HS	70	}
	71
	72	/* Clear PLLRST bit to reset the PLL */
f3c149d6	73	clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
310ae55e HS	74
310ae55e HS	75	/* Disable the PLL output */
f3c149d6	76	setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
310ae55e HS	77
	78	/* PLL initialization sequence */
	79	/*
	80	* Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
	81	* power down bit
	82	*/
f3c149d6	83	clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
310ae55e HS	84
310ae55e HS	85	/* Enable the PLL from Disable Mode PLLDIS bit to 0 */
f3c149d6	86	clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
310ae55e	87
d652a344 BG	88	#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
	89	/* program the prediv */
	90	if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
	91	writel((PLL_DIVEN \| CONFIG_SYS_DA850_PLL0_PREDIV),
	92	&reg->prediv);
	93	#endif
	94
310ae55e HS	95	/* Program the required multiplier value in PLLM */
	96	writel(pllmult, &reg->pllm);
	97
	98	/* program the postdiv */
	99	if (reg == davinci_pllc0_regs)
f3c149d6	100	writel((PLL_POSTDEN \| CONFIG_SYS_DA850_PLL0_POSTDIV),
310ae55e HS	101	&reg->postdiv);
310ae55e HS	102	else
f3c149d6	103	writel((PLL_POSTDEN \| CONFIG_SYS_DA850_PLL1_POSTDIV),
310ae55e HS	104	&reg->postdiv);
	105
	106	/*
	107	* Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
	108	* no GO operation is currently in progress
	109	*/
f3c149d6	110	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
310ae55e HS	111	;
	112
	113	if (reg == davinci_pllc0_regs) {
effea9d1 CR	114	writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
	115	writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
	116	writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
	117	writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
	118	writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
	119	writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
	120	writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
310ae55e	121	} else {
effea9d1 CR	122	writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
	123	writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
	124	writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
310ae55e HS	125	}
	126
	127	/*
	128	* Set the GOSET bit in PLLCMD to 1 to initiate a new divider
	129	* transition.
	130	*/
f3c149d6	131	setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
310ae55e HS	132
	133	/*
	134	* Wait for the GOSTAT bit in PLLSTAT to clear to 0
	135	* (completion of phase alignment).
	136	*/
f3c149d6	137	while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
310ae55e HS	138	;
	139
	140	/* Wait for PLL to reset properly. See PLL spec for PLL reset time */
effea9d1	141	da850_waitloop(200);
310ae55e HS	142
310ae55e HS	143	/* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
f3c149d6	144	setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
310ae55e HS	145
310ae55e HS	146	/* Wait for PLL to lock. See PLL spec for PLL lock time */
effea9d1	147	da850_waitloop(2400);
310ae55e HS	148
	149	/*
	150	* Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
	151	* mode
	152	*/
f3c149d6	153	setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
310ae55e HS	154
	155
	156	/*
	157	* clear EMIFA and EMIFB clock source settings, let them
	158	* run off SYSCLK
	159	*/
	160	if (reg == davinci_pllc0_regs)
f3c149d6 HS	161	dv_maskbits(&davinci_syscfg_regs->cfgchip3,
f3c149d6 HS	162	~(PLL_SCSCFG3_DIV45PENA \| PLL_SCSCFG3_EMA_CLKSRC));
310ae55e HS	163
	164	return 0;
	165	}
	166
f3c149d6	167	int da850_ddr_setup(void)
310ae55e HS	168	{
	169	unsigned long tmp;
	170
	171	/* Enable the Clock to DDR2/mDDR */
95c248f4	172	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
310ae55e HS	173
	174	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	175	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
	176	/* Begin VTP Calibration */
	177	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
	178	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
	179	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	180	clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	181	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
	182
	183	/* Polling READY bit to see when VTP calibration is done */
	184	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	185	while ((tmp & VTP_READY) != VTP_READY)
	186	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
	187
	188	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
	189	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
	190
	191	setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
	192	}
	193
effea9d1	194	writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
310ae55e HS	195	clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
	196	(1 << DDR_SLEW_CMOSEN_BIT));
	197
085d4574 CR	198	/*
	199	* SDRAM Configuration Register (SDCR):
	200	* First set the BOOTUNLOCK bit to make configuration bits
	201	* writeable.
	202	*/
310ae55e HS	203	setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
310ae55e HS	204
085d4574 CR	205	/*
	206	* Write the new value of these bits and clear BOOTUNLOCK.
	207	* At the same time, set the TIMUNLOCK bit to allow changing
	208	* the timing registers
	209	*/
	210	tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
f3c149d6 HS	211	tmp &= ~DV_DDR_BOOTUNLOCK;
f3c149d6 HS	212	tmp \|= DV_DDR_TIMUNLOCK;
085d4574	213	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
310ae55e	214
085d4574 CR	215	/* write memory configuration and timing */
085d4574 CR	216	writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
effea9d1 CR	217	writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
effea9d1 CR	218	writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
310ae55e	219
085d4574	220	/* clear the TIMUNLOCK bit and write the value of the CL field */
f3c149d6	221	tmp &= ~DV_DDR_TIMUNLOCK;
085d4574	222	writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
310ae55e HS	223
	224	/*
	225	* LPMODEN and MCLKSTOPEN must be set!
	226	* Without this bits set, PSC don;t switch states !!
	227	*/
effea9d1	228	writel(CONFIG_SYS_DA850_DDR2_SDRCR \|
310ae55e HS	229	(1 << DV_DDR_SRCR_LPMODEN_SHIFT) \|
	230	(1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
	231	&dv_ddr2_regs_ctrl->sdrcr);
	232
	233	/* SyncReset the Clock to EMIF3A SDRAM */
95c248f4	234	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
310ae55e	235	/* Enable the Clock to EMIF3A SDRAM */
95c248f4	236	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
310ae55e HS	237
310ae55e HS	238	/* disable self refresh */
f3c149d6 HS	239	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
	240	DV_DDR_SDRCR_LPMODEN \| DV_DDR_SDRCR_LPMODEN);
	241	writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
310ae55e HS	242
	243	return 0;
	244	}
	245
310ae55e HS	246	__attribute__((weak))
	247	void board_gpio_init(void)
	248	{
	249	return;
	250	}
	251
65204715 CR	252	/* pinmux_resource[] vector is defined in the board specific file */
	253	extern const struct pinmux_resource pinmuxes[];
	254	extern const int pinmuxes_size;
	255
310ae55e	256	int arch_cpu_init(void)
310ae55e	257	{
310ae55e	258	/* Unlock kick registers */
f3c149d6 HS	259	writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
f3c149d6 HS	260	writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
310ae55e HS	261
310ae55e HS	262	dv_maskbits(&davinci_syscfg_regs->suspsrc,
f3c149d6	263	CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
310ae55e	264
65204715 CR	265	/* configure pinmux settings */
	266	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
	267	return 1;
310ae55e HS	268
310ae55e HS	269	/* PLL setup */
effea9d1 CR	270	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
effea9d1 CR	271	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
310ae55e HS	272
	273	/* GPIO setup */
	274	board_gpio_init();
	275
	276	/* setup CSn config */
f3c149d6	277	#if defined(CONFIG_SYS_DA850_CS2CFG)
effea9d1	278	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
f3c149d6 HS	279	#endif
f3c149d6 HS	280	#if defined(CONFIG_SYS_DA850_CS3CFG)
effea9d1	281	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
f3c149d6	282	#endif
310ae55e	283
f3c149d6	284	lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
310ae55e HS	285	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
	286	CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
	287
	288	/*
	289	* Fix Power and Emulation Management Register
	290	* see sprufw3a.pdf page 37 Table 24
	291	*/
f3c149d6 HS	292	writel((DAVINCI_UART_PWREMU_MGMT_FREE \| DAVINCI_UART_PWREMU_MGMT_URRST \|
	293	DAVINCI_UART_PWREMU_MGMT_UTRST),
	294	&davinci_uart2_ctrl_regs->pwremu_mgmt);
310ae55e	295
f3c149d6	296	da850_ddr_setup();
310ae55e	297	return 0;
310ae55e	298	}