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4efb77d4 PW |
1 | /* |
2 | * Copyright (C) Marvell International Ltd. and its affiliates | |
3 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
21 | * MA 02110-1301 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/arch/kirkwood.h> | |
26 | ||
27 | #define UBOOT_CNTR 0 /* counter to use for uboot timer */ | |
28 | ||
29 | /* Timer reload and current value registers */ | |
30 | struct kwtmr_val { | |
31 | u32 reload; /* Timer reload reg */ | |
32 | u32 val; /* Timer value reg */ | |
33 | }; | |
34 | ||
35 | /* Timer registers */ | |
36 | struct kwtmr_registers { | |
37 | u32 ctrl; /* Timer control reg */ | |
38 | u32 pad[3]; | |
39 | struct kwtmr_val tmr[2]; | |
40 | u32 wdt_reload; | |
41 | u32 wdt_val; | |
42 | }; | |
43 | ||
44 | struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; | |
45 | ||
46 | /* | |
47 | * ARM Timers Registers Map | |
48 | */ | |
49 | #define CNTMR_CTRL_REG &kwtmr_regs->ctrl | |
50 | #define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload | |
51 | #define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val | |
52 | ||
53 | /* | |
54 | * ARM Timers Control Register | |
55 | * CPU_TIMERS_CTRL_REG (CTCR) | |
56 | */ | |
57 | #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) | |
58 | #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) | |
59 | #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) | |
60 | #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) | |
61 | ||
62 | #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) | |
63 | #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) | |
64 | #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) | |
65 | #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) | |
66 | ||
67 | /* | |
68 | * ARM Timer\Watchdog Reload Register | |
69 | * CNTMR_RELOAD_REG (TRR) | |
70 | */ | |
71 | #define TRG_ARM_TIMER_REL_OFFS 0 | |
72 | #define TRG_ARM_TIMER_REL_MASK 0xffffffff | |
73 | ||
74 | /* | |
75 | * ARM Timer\Watchdog Register | |
76 | * CNTMR_VAL_REG (TVRG) | |
77 | */ | |
78 | #define TVR_ARM_TIMER_OFFS 0 | |
79 | #define TVR_ARM_TIMER_MASK 0xffffffff | |
80 | #define TVR_ARM_TIMER_MAX 0xffffffff | |
81 | #define TIMER_LOAD_VAL 0xffffffff | |
82 | ||
83 | #define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ | |
84 | (CONFIG_SYS_TCLK / 1000)) | |
85 | ||
c9ac3ba1 HS |
86 | DECLARE_GLOBAL_DATA_PTR; |
87 | ||
88 | #define timestamp gd->tbl | |
89 | #define lastdec gd->lastinc | |
4efb77d4 | 90 | |
4efb77d4 PW |
91 | ulong get_timer_masked(void) |
92 | { | |
93 | ulong now = READ_TIMER; | |
94 | ||
95 | if (lastdec >= now) { | |
96 | /* normal mode */ | |
97 | timestamp += lastdec - now; | |
98 | } else { | |
99 | /* we have an overflow ... */ | |
100 | timestamp += lastdec + | |
101 | (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; | |
102 | } | |
103 | lastdec = now; | |
104 | ||
105 | return timestamp; | |
106 | } | |
107 | ||
4efb77d4 PW |
108 | ulong get_timer(ulong base) |
109 | { | |
110 | return get_timer_masked() - base; | |
111 | } | |
112 | ||
3eb90bad | 113 | void __udelay(unsigned long usec) |
4efb77d4 PW |
114 | { |
115 | uint current; | |
116 | ulong delayticks; | |
117 | ||
118 | current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); | |
119 | delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); | |
120 | ||
121 | if (current < delayticks) { | |
122 | delayticks -= current; | |
123 | while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; | |
124 | while ((TIMER_LOAD_VAL - delayticks) < | |
125 | readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; | |
126 | } else { | |
127 | while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > | |
128 | (current - delayticks)) ; | |
129 | } | |
130 | } | |
131 | ||
132 | /* | |
133 | * init the counter | |
134 | */ | |
135 | int timer_init(void) | |
136 | { | |
137 | unsigned int cntmrctrl; | |
138 | ||
139 | /* load value into timer */ | |
140 | writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); | |
141 | writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); | |
142 | ||
143 | /* enable timer in auto reload mode */ | |
144 | cntmrctrl = readl(CNTMR_CTRL_REG); | |
145 | cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); | |
146 | cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); | |
147 | writel(cntmrctrl, CNTMR_CTRL_REG); | |
148 | ||
149 | /* init the timestamp and lastdec value */ | |
17659d7d GR |
150 | lastdec = READ_TIMER; |
151 | timestamp = 0; | |
4efb77d4 PW |
152 | |
153 | return 0; | |
154 | } |