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04fe4273 MV |
1 | /* |
2 | * armboot - Startup Code for ARM926EJS CPU-core | |
3 | * | |
4 | * Copyright (c) 2003 Texas Instruments | |
5 | * | |
6 | * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ | |
7 | * | |
8 | * Copyright (c) 2001 Marius Groger <mag@sysgo.de> | |
9 | * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> | |
10 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> | |
11 | * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> | |
12 | * Copyright (c) 2003 Kshitij <kshitij@ti.com> | |
13 | * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> | |
14 | * | |
15 | * Change to support call back into iMX28 bootrom | |
16 | * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> | |
17 | * on behalf of DENX Software Engineering GmbH | |
18 | * | |
19 | * See file CREDITS for list of people who contributed to this | |
20 | * project. | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or | |
23 | * modify it under the terms of the GNU General Public License as | |
24 | * published by the Free Software Foundation; either version 2 of | |
25 | * the License, or (at your option) any later version. | |
26 | * | |
27 | * This program is distributed in the hope that it will be useful, | |
28 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
29 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 | * GNU General Public License for more details. | |
31 | * | |
32 | * You should have received a copy of the GNU General Public License | |
33 | * along with this program; if not, write to the Free Software | |
34 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
35 | * MA 02111-1307 USA | |
36 | */ | |
37 | ||
38 | #include <asm-offsets.h> | |
39 | #include <config.h> | |
40 | #include <common.h> | |
41 | #include <version.h> | |
42 | ||
04fe4273 MV |
43 | /* |
44 | ************************************************************************* | |
45 | * | |
46 | * Jump vector table as in table 3.1 in [1] | |
47 | * | |
48 | ************************************************************************* | |
49 | */ | |
50 | ||
51 | ||
52 | .globl _start | |
53 | _start: | |
54 | b reset | |
22fe68fb MV |
55 | b undefined_instruction |
56 | b software_interrupt | |
57 | b prefetch_abort | |
58 | b data_abort | |
59 | b not_used | |
60 | b irq | |
61 | b fiq | |
04fe4273 | 62 | |
22fe68fb MV |
63 | /* |
64 | * Vector table, located at address 0x20. | |
65 | * This table allows the code running AFTER SPL, the U-Boot, to install it's | |
66 | * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, | |
67 | * including it's interrupt vectoring table and the table at 0x0 is still the | |
68 | * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table | |
69 | * is still used. | |
70 | */ | |
71 | _vt_reset: | |
72 | .word _reset | |
73 | _vt_undefined_instruction: | |
74 | .word _hang | |
75 | _vt_software_interrupt: | |
76 | .word _hang | |
77 | _vt_prefetch_abort: | |
78 | .word _hang | |
79 | _vt_data_abort: | |
80 | .word _hang | |
81 | _vt_not_used: | |
82 | .word _reset | |
83 | _vt_irq: | |
84 | .word _hang | |
85 | _vt_fiq: | |
86 | .word _hang | |
04fe4273 | 87 | |
22fe68fb MV |
88 | reset: |
89 | ldr pc, _vt_reset | |
90 | undefined_instruction: | |
91 | ldr pc, _vt_undefined_instruction | |
92 | software_interrupt: | |
93 | ldr pc, _vt_software_interrupt | |
94 | prefetch_abort: | |
95 | ldr pc, _vt_prefetch_abort | |
96 | data_abort: | |
97 | ldr pc, _vt_data_abort | |
98 | not_used: | |
99 | ldr pc, _vt_not_used | |
100 | irq: | |
101 | ldr pc, _vt_irq | |
102 | fiq: | |
103 | ldr pc, _vt_fiq | |
04fe4273 | 104 | |
04fe4273 MV |
105 | .balignl 16,0xdeadbeef |
106 | ||
04fe4273 MV |
107 | /* |
108 | ************************************************************************* | |
109 | * | |
110 | * Startup Code (reset vector) | |
111 | * | |
112 | * do important init only if we don't start from memory! | |
113 | * setup Memory and board specific bits prior to relocation. | |
114 | * relocate armboot to ram | |
115 | * setup stack | |
116 | * | |
117 | ************************************************************************* | |
118 | */ | |
119 | ||
120 | .globl _TEXT_BASE | |
121 | _TEXT_BASE: | |
508611bc BT |
122 | #ifdef CONFIG_SPL_TEXT_BASE |
123 | .word CONFIG_SPL_TEXT_BASE | |
124 | #else | |
04fe4273 | 125 | .word CONFIG_SYS_TEXT_BASE |
508611bc | 126 | #endif |
04fe4273 MV |
127 | |
128 | /* | |
129 | * These are defined in the board-specific linker script. | |
130 | * Subtracting _start from them lets the linker put their | |
131 | * relative position in the executable instead of leaving | |
132 | * them null. | |
133 | */ | |
134 | .globl _bss_start_ofs | |
135 | _bss_start_ofs: | |
136 | .word __bss_start - _start | |
137 | ||
138 | .globl _bss_end_ofs | |
139 | _bss_end_ofs: | |
3929fb0a | 140 | .word __bss_end - _start |
04fe4273 MV |
141 | |
142 | .globl _end_ofs | |
143 | _end_ofs: | |
144 | .word _end - _start | |
145 | ||
146 | #ifdef CONFIG_USE_IRQ | |
147 | /* IRQ stack memory (calculated at run-time) */ | |
148 | .globl IRQ_STACK_START | |
149 | IRQ_STACK_START: | |
150 | .word 0x0badc0de | |
151 | ||
152 | /* IRQ stack memory (calculated at run-time) */ | |
153 | .globl FIQ_STACK_START | |
154 | FIQ_STACK_START: | |
155 | .word 0x0badc0de | |
156 | #endif | |
157 | ||
158 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ | |
159 | .globl IRQ_STACK_START_IN | |
160 | IRQ_STACK_START_IN: | |
161 | .word 0x0badc0de | |
162 | ||
163 | /* | |
164 | * the actual reset code | |
165 | */ | |
166 | ||
22fe68fb | 167 | _reset: |
04fe4273 MV |
168 | /* |
169 | * Store all registers on old stack pointer, this will allow us later to | |
170 | * return to the BootROM and let the BootROM load U-Boot into RAM. | |
171 | */ | |
172 | push {r0-r12,r14} | |
173 | ||
61698fd5 MF |
174 | /* save control register c1 */ |
175 | mrc p15, 0, r0, c1, c0, 0 | |
176 | push {r0} | |
177 | ||
04fe4273 | 178 | /* |
61698fd5 | 179 | * set the cpu to SVC32 mode and store old CPSR register content |
04fe4273 MV |
180 | */ |
181 | mrs r0,cpsr | |
61698fd5 | 182 | push {r0} |
04fe4273 MV |
183 | bic r0,r0,#0x1f |
184 | orr r0,r0,#0xd3 | |
185 | msr cpsr,r0 | |
186 | ||
04fe4273 MV |
187 | bl board_init_ll |
188 | ||
61698fd5 MF |
189 | /* |
190 | * restore bootrom's cpu mode (especially FIQ) | |
191 | */ | |
192 | pop {r0} | |
193 | msr cpsr,r0 | |
194 | ||
195 | /* | |
196 | * restore c1 register | |
197 | * (especially set exception vector location back to | |
198 | * bootrom space which is required by bootrom for USB boot) | |
199 | */ | |
200 | pop {r0} | |
201 | mcr p15, 0, r0, c1, c0, 0 | |
202 | ||
04fe4273 MV |
203 | pop {r0-r12,r14} |
204 | bx lr | |
205 | ||
22fe68fb | 206 | _hang: |
04fe4273 MV |
207 | ldr sp, _TEXT_BASE /* switch to abort stack */ |
208 | 1: | |
209 | bl 1b /* hang and never return */ |