projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4ae8bc43 SR |
1 | /* |
| 2 | * armboot - Startup Code for ARM926EJS CPU-core | |
| 3 | * | |
| 4 | * Copyright (c) 2003 Texas Instruments | |
| 5 | * | |
| 6 | * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ | |
| 7 | * | |
| 8 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> | |
| 9 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> | |
| 10 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> | |
| 11 | * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> | |
| 12 | * Copyright (c) 2003 Kshitij <kshitij@ti.com> | |
| 13 | * | |
| 1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
| 4ae8bc43 SR |
15 | */ |
| 16 | ||
| 17 | ||
| 18 | #include <config.h> | |
| 19 | ||
| 4ae8bc43 SR |
20 | /* |
| 21 | ************************************************************************* | |
| 22 | * | |
| 23 | * Startup Code (reset vector) | |
| 24 | * | |
| 25 | * Below are the critical initializations already taken place in BootROM. | |
| 26 | * So, these are not taken care in Xloader | |
| 27 | * 1. Relocation to RAM | |
| 28 | * 2. Initializing stacks | |
| 29 | * | |
| 30 | ************************************************************************* | |
| 31 | */ | |
| 32 | ||
| 41623c91 | 33 | .globl reset |
| 4ae8bc43 SR |
34 | |
| 35 | reset: | |
| 36 | /* | |
| 37 | * Xloader has to return back to BootROM in a few cases. | |
| 38 | * eg. Ethernet boot, UART boot, USB boot | |
| 39 | * Saving registers for returning back | |
| 40 | */ | |
| 41 | stmdb sp!, {r0-r12,r14} | |
| 42 | bl cpu_init_crit | |
| 43 | /* | |
| 44 | * Clearing bss area is not done in Xloader. | |
| 45 | * BSS area lies in the DDR location which is not yet initialized | |
| 46 | * bss is assumed to be uninitialized. | |
| 47 | */ | |
| 48 | bl spl_boot | |
| 49 | ldmia sp!, {r0-r12,pc} | |
| 50 | ||
| 51 | /* | |
| 52 | ************************************************************************* | |
| 53 | * | |
| 54 | * CPU_init_critical registers | |
| 55 | * | |
| 56 | * setup important registers | |
| 57 | * setup memory timing | |
| 58 | * | |
| 59 | ************************************************************************* | |
| 60 | */ | |
| 61 | cpu_init_crit: | |
| 62 | /* | |
| 63 | * flush v4 I/D caches | |
| 64 | */ | |
| 65 | mov r0, #0 | |
| 66 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ | |
| 67 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ | |
| 68 | ||
| 69 | /* | |
| 70 | * enable instruction cache | |
| 71 | */ | |
| 72 | mrc p15, 0, r0, c1, c0, 0 | |
| 73 | orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ | |
| 74 | mcr p15, 0, r0, c1, c0, 0 | |
| 75 | ||
| 76 | /* | |
| 77 | * Go setup Memory and board specific bits prior to relocation. | |
| 78 | */ | |
| 79 | stmdb sp!, {lr} | |
| 80 | bl lowlevel_init /* go setup pll,mux,memory */ | |
| 81 | ldmia sp!, {pc} |