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ARM: SPL: Convert davinci to CONFIG_SPL_FRAMEWORK
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6f21347d
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1/*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
a56bd922 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
6f21347d 7 *
fa82f871
AA
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
792a09eb 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
57b4bce9 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
6f21347d
WD
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
25ddd1fb 34#include <asm-offsets.h>
6f21347d 35#include <config.h>
fcd3c87e 36#include <common.h>
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WD
37#include <version.h>
38
39#if defined(CONFIG_OMAP1610)
40#include <./configs/omap1510.h>
a56bd922
WD
41#elif defined(CONFIG_OMAP730)
42#include <./configs/omap730.h>
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43#endif
44
45/*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
52
53
337c4333 54#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
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55.globl _start
56_start:
337c4333
HS
57.globl _NOR_BOOT_CFG
58_NOR_BOOT_CFG:
59 .word CONFIG_SYS_DV_NOR_BOOT_CFG
6f21347d 60 b reset
337c4333
HS
61#else
62.globl _start
63_start:
64 b reset
65#endif
401bb30b 66#ifdef CONFIG_SPL_BUILD
ef22b503
JR
67/* No exception handlers in preloader */
68 ldr pc, _hang
69 ldr pc, _hang
70 ldr pc, _hang
71 ldr pc, _hang
72 ldr pc, _hang
73 ldr pc, _hang
74 ldr pc, _hang
75
76_hang:
77 .word do_hang
78/* pad to 64 byte boundary */
79 .word 0x12345678
80 .word 0x12345678
81 .word 0x12345678
82 .word 0x12345678
83 .word 0x12345678
84 .word 0x12345678
85 .word 0x12345678
86#else
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87 ldr pc, _undefined_instruction
88 ldr pc, _software_interrupt
89 ldr pc, _prefetch_abort
90 ldr pc, _data_abort
91 ldr pc, _not_used
92 ldr pc, _irq
93 ldr pc, _fiq
94
95_undefined_instruction:
96 .word undefined_instruction
97_software_interrupt:
98 .word software_interrupt
99_prefetch_abort:
100 .word prefetch_abort
101_data_abort:
102 .word data_abort
103_not_used:
104 .word not_used
105_irq:
106 .word irq
107_fiq:
108 .word fiq
109
401bb30b 110#endif /* CONFIG_SPL_BUILD */
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111 .balignl 16,0xdeadbeef
112
113
114/*
115 *************************************************************************
116 *
117 * Startup Code (reset vector)
118 *
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
122 * setup stack
123 *
124 *************************************************************************
125 */
126
ab86f72c 127.globl _TEXT_BASE
6f21347d 128_TEXT_BASE:
435199f3 129#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
14d0a02a 130 .word CONFIG_SYS_TEXT_BASE
435199f3
HS
131#else
132#ifdef CONFIG_SPL_BUILD
133 .word CONFIG_SPL_TEXT_BASE
134#else
135 .word CONFIG_SYS_TEXT_BASE
136#endif
137#endif
6f21347d 138
6f21347d 139/*
f6e20fc6 140 * These are defined in the board-specific linker script.
92d5ecba
AA
141 * Subtracting _start from them lets the linker put their
142 * relative position in the executable instead of leaving
143 * them null.
6f21347d 144 */
92d5ecba
AA
145.globl _bss_start_ofs
146_bss_start_ofs:
147 .word __bss_start - _start
f6e20fc6 148
92d5ecba
AA
149.globl _bss_end_ofs
150_bss_end_ofs:
44c6e659 151 .word __bss_end__ - _start
6f21347d 152
f326cbba
PYC
153.globl _end_ofs
154_end_ofs:
155 .word _end - _start
156
6a6e1677
HS
157#ifdef CONFIG_NAND_U_BOOT
158.globl _end
159_end:
160 .word __bss_end__
161#endif
162
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163#ifdef CONFIG_USE_IRQ
164/* IRQ stack memory (calculated at run-time) */
165.globl IRQ_STACK_START
166IRQ_STACK_START:
167 .word 0x0badc0de
168
169/* IRQ stack memory (calculated at run-time) */
170.globl FIQ_STACK_START
171FIQ_STACK_START:
172 .word 0x0badc0de
173#endif
174
ab86f72c
HS
175/* IRQ stack memory (calculated at run-time) + 8 bytes */
176.globl IRQ_STACK_START_IN
177IRQ_STACK_START_IN:
178 .word 0x0badc0de
179
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180/*
181 * the actual reset code
182 */
183
184reset:
185 /*
186 * set the cpu to SVC32 mode
187 */
188 mrs r0,cpsr
189 bic r0,r0,#0x1f
190 orr r0,r0,#0xd3
191 msr cpsr,r0
192
6f21347d 193 /*
a8c7c708
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194 * we do sys-critical inits only at reboot,
195 * not when booting from ram!
6f21347d 196 */
27b66622 197#ifndef CONFIG_SKIP_LOWLEVEL_INIT
a8c7c708 198 bl cpu_init_crit
27b66622 199#endif
a8c7c708 200
ab86f72c
HS
201/* Set stackpointer in internal RAM to call board_init_f */
202call_board_init_f:
435199f3
HS
203#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
204 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
205#else
206#ifdef CONFIG_SPL_BUILD
207 ldr sp, =(CONFIG_SPL_STACK)
208#else
ab86f72c 209 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
435199f3
HS
210#endif
211#endif
296cae73 212 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ab86f72c
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213 ldr r0,=0x00000000
214 bl board_init_f
215
216/*------------------------------------------------------------------------------*/
217
3f7f2414 218#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
ab86f72c
HS
219/*
220 * void relocate_code (addr_sp, gd, addr_moni)
221 *
222 * This "function" does not return, instead it continues in RAM
223 * after relocating the monitor code.
224 *
225 */
226 .globl relocate_code
227relocate_code:
228 mov r4, r0 /* save addr_sp */
229 mov r5, r1 /* save addr of gd */
230 mov r6, r2 /* save addr of destination */
ab86f72c
HS
231
232 /* Set up the stack */
233stack_setup:
234 mov sp, r4
235
236 adr r0, _start
435199f3 237 sub r9, r6, r0 /* r9 <- relocation offset */
a1a47d3c
AB
238 cmp r0, r6
239 beq clear_bss /* skip relocation */
a78fb68f 240 mov r1, r6 /* r1 <- scratch for copy loop */
92d5ecba
AA
241 ldr r3, _bss_start_ofs
242 add r2, r0, r3 /* r2 <- source end address */
ab86f72c 243
ab86f72c
HS
244copy_loop:
245 ldmia r0!, {r9-r10} /* copy from source address [r0] */
a78fb68f 246 stmia r1!, {r9-r10} /* copy to target address [r1] */
da90d4ce
AA
247 cmp r0, r2 /* until source end address [r2] */
248 blo copy_loop
ab86f72c 249
401bb30b 250#ifndef CONFIG_SPL_BUILD
92d5ecba
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251 /*
252 * fix .rel.dyn relocations
253 */
254 ldr r0, _TEXT_BASE /* r0 <- Text base */
a78fb68f 255 sub r9, r6, r0 /* r9 <- relocation offset */
92d5ecba
AA
256 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
257 add r10, r10, r0 /* r10 <- sym table in FLASH */
258 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
259 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
260 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
261 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
ab86f72c 262fixloop:
8c0c2b90
GR
263 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
264 add r0, r0, r9 /* r0 <- location to fix up in RAM */
92d5ecba 265 ldr r1, [r2, #4]
1f52d89f
AB
266 and r7, r1, #0xff
267 cmp r7, #23 /* relative fixup? */
92d5ecba 268 beq fixrel
1f52d89f 269 cmp r7, #2 /* absolute fixup? */
92d5ecba
AA
270 beq fixabs
271 /* ignore unknown type of fixup */
272 b fixnext
273fixabs:
274 /* absolute fix: set location to (offset) symbol value */
275 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
276 add r1, r10, r1 /* r1 <- address of symbol in table */
277 ldr r1, [r1, #4] /* r1 <- symbol value */
3600945b 278 add r1, r1, r9 /* r1 <- relocated sym addr */
92d5ecba
AA
279 b fixnext
280fixrel:
281 /* relative fix: increase location by offset */
282 ldr r1, [r0]
283 add r1, r1, r9
284fixnext:
285 str r1, [r0]
8c0c2b90 286 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
ab86f72c 287 cmp r2, r3
92d5ecba 288 blo fixloop
ab86f72c 289#endif
ab86f72c
HS
290
291clear_bss:
435199f3
HS
292#ifdef CONFIG_SPL_BUILD
293 /* No relocation for SPL */
294 ldr r0, =__bss_start
295 ldr r1, =__bss_end__
296#else
92d5ecba
AA
297 ldr r0, _bss_start_ofs
298 ldr r1, _bss_end_ofs
a78fb68f 299 mov r4, r6 /* reloc addr */
ab86f72c 300 add r0, r0, r4
ab86f72c 301 add r1, r1, r4
435199f3 302#endif
ab86f72c
HS
303 mov r2, #0x00000000 /* clear */
304
8f1da535
CR
305clbss_l:cmp r0, r1 /* clear loop... */
306 bhs clbss_e /* if reached end of bss, exit */
307 str r2, [r0]
ab86f72c 308 add r0, r0, #4
8f1da535
CR
309 b clbss_l
310clbss_e:
ab86f72c 311
435199f3 312#ifndef CONFIG_SPL_BUILD
ab86f72c 313 bl coloured_LED_init
2d3be7c4 314 bl red_led_on
ab86f72c
HS
315#endif
316
317/*
318 * We are done. Do not return, instead branch to second part of board
319 * initialization, now running from RAM.
320 */
321#ifdef CONFIG_NAND_SPL
92d5ecba 322 ldr r0, _nand_boot_ofs
9710504d 323 mov pc, r0
ab86f72c 324
9710504d
HS
325_nand_boot_ofs:
326 .word nand_boot
ab86f72c 327#else
92d5ecba 328 ldr r0, _board_init_r_ofs
6087f1a9 329 ldr r1, _TEXT_BASE
123fb7de 330 add lr, r0, r1
123fb7de 331 add lr, lr, r9
ab86f72c
HS
332 /* setup parameters for board_init_r */
333 mov r0, r5 /* gd_t */
a78fb68f 334 mov r1, r6 /* dest_addr */
ab86f72c 335 /* jump to it ... */
ab86f72c
HS
336 mov pc, lr
337
92d5ecba
AA
338_board_init_r_ofs:
339 .word board_init_r - _start
ab86f72c
HS
340#endif
341
92d5ecba
AA
342_rel_dyn_start_ofs:
343 .word __rel_dyn_start - _start
344_rel_dyn_end_ofs:
345 .word __rel_dyn_end - _start
346_dynsym_start_ofs:
347 .word __dynsym_start - _start
3f7f2414 348#endif
92d5ecba 349
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350/*
351 *************************************************************************
352 *
353 * CPU_init_critical registers
354 *
355 * setup important registers
356 * setup memory timing
357 *
358 *************************************************************************
359 */
27b66622 360#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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361cpu_init_crit:
362 /*
da104e04 363 * flush D cache before disabling it
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364 */
365 mov r0, #0
da104e04
SG
366flush_dcache:
367 mrc p15, 0, r15, c7, c10, 3
368 bne flush_dcache
369
370 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
371 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
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372
373 /*
d735a99d
CR
374 * disable MMU and D cache
375 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
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376 */
377 mrc p15, 0, r0, c1, c0, 0
b67d8816 378 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
6f21347d 379 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
b67d8816
CR
380#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
381 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
382#else
383 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
384#endif
6f21347d 385 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
d735a99d 386#ifndef CONFIG_SYS_ICACHE_OFF
6f21347d 387 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
d735a99d 388#endif
6f21347d
WD
389 mcr p15, 0, r0, c1, c0, 0
390
391 /*
392 * Go setup Memory and board specific bits prior to relocation.
393 */
394 mov ip, lr /* perserve link reg across call */
87cb6862 395 bl lowlevel_init /* go setup pll,mux,memory */
6f21347d 396 mov lr, ip /* restore link */
ca4b5580 397 mov pc, lr /* back to my caller */
27b66622 398#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
a6cdd21b 399
401bb30b 400#ifndef CONFIG_SPL_BUILD
6f21347d
WD
401/*
402 *************************************************************************
403 *
404 * Interrupt handling
405 *
406 *************************************************************************
407 */
408
409@
410@ IRQ stack frame.
411@
412#define S_FRAME_SIZE 72
413
414#define S_OLD_R0 68
415#define S_PSR 64
416#define S_PC 60
417#define S_LR 56
418#define S_SP 52
419
420#define S_IP 48
421#define S_FP 44
422#define S_R10 40
423#define S_R9 36
424#define S_R8 32
425#define S_R7 28
426#define S_R6 24
427#define S_R5 20
428#define S_R4 16
429#define S_R3 12
430#define S_R2 8
431#define S_R1 4
432#define S_R0 0
433
434#define MODE_SVC 0x13
435#define I_BIT 0x80
436
437/*
438 * use bad_save_user_regs for abort/prefetch/undef/swi ...
439 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
440 */
441
442 .macro bad_save_user_regs
443 @ carve out a frame on current user stack
444 sub sp, sp, #S_FRAME_SIZE
445 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ab86f72c 446 ldr r2, IRQ_STACK_START_IN
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WD
447 @ get values for "aborted" pc and cpsr (into parm regs)
448 ldmia r2, {r2 - r3}
449 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
450 add r5, sp, #S_SP
451 mov r1, lr
452 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
453 mov r0, sp @ save current stack into r0 (param register)
454 .endm
455
456 .macro irq_save_user_regs
457 sub sp, sp, #S_FRAME_SIZE
458 stmia sp, {r0 - r12} @ Calling r0-r12
459 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
460 add r8, sp, #S_PC
461 stmdb r8, {sp, lr}^ @ Calling SP, LR
462 str lr, [r8, #0] @ Save calling PC
463 mrs r6, spsr
464 str r6, [r8, #4] @ Save CPSR
465 str r0, [r8, #8] @ Save OLD_R0
466 mov r0, sp
467 .endm
468
469 .macro irq_restore_user_regs
470 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
471 mov r0, r0
472 ldr lr, [sp, #S_PC] @ Get PC
473 add sp, sp, #S_FRAME_SIZE
474 subs pc, lr, #4 @ return & move spsr_svc into cpsr
475 .endm
476
477 .macro get_bad_stack
ab86f72c 478 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
6f21347d
WD
479
480 str lr, [r13] @ save caller lr in position 0 of saved stack
481 mrs lr, spsr @ get the spsr
482 str lr, [r13, #4] @ save spsr in position 1 of saved stack
483 mov r13, #MODE_SVC @ prepare SVC-Mode
484 @ msr spsr_c, r13
485 msr spsr, r13 @ switch modes, make sure moves will execute
486 mov lr, pc @ capture return pc
487 movs pc, lr @ jump to next instruction & switch modes.
488 .endm
489
490 .macro get_irq_stack @ setup IRQ stack
491 ldr sp, IRQ_STACK_START
492 .endm
493
494 .macro get_fiq_stack @ setup FIQ stack
495 ldr sp, FIQ_STACK_START
496 .endm
401bb30b 497#endif /* CONFIG_SPL_BUILD */
6f21347d
WD
498
499/*
500 * exception handlers
501 */
401bb30b 502#ifdef CONFIG_SPL_BUILD
ef22b503
JR
503 .align 5
504do_hang:
505 ldr sp, _TEXT_BASE /* switch to abort stack */
5061:
507 bl 1b /* hang and never return */
401bb30b 508#else /* !CONFIG_SPL_BUILD */
6f21347d
WD
509 .align 5
510undefined_instruction:
511 get_bad_stack
512 bad_save_user_regs
513 bl do_undefined_instruction
514
515 .align 5
516software_interrupt:
517 get_bad_stack
518 bad_save_user_regs
519 bl do_software_interrupt
520
521 .align 5
522prefetch_abort:
523 get_bad_stack
524 bad_save_user_regs
525 bl do_prefetch_abort
526
527 .align 5
528data_abort:
529 get_bad_stack
530 bad_save_user_regs
531 bl do_data_abort
532
533 .align 5
534not_used:
535 get_bad_stack
536 bad_save_user_regs
537 bl do_not_used
538
539#ifdef CONFIG_USE_IRQ
540
541 .align 5
542irq:
543 get_irq_stack
544 irq_save_user_regs
53677ef1 545 bl do_irq
6f21347d
WD
546 irq_restore_user_regs
547
548 .align 5
549fiq:
550 get_fiq_stack
551 /* someone ought to write a more effiction fiq_save_user_regs */
552 irq_save_user_regs
53677ef1 553 bl do_fiq
6f21347d
WD
554 irq_restore_user_regs
555
556#else
557
558 .align 5
559irq:
560 get_bad_stack
561 bad_save_user_regs
562 bl do_irq
563
564 .align 5
565fiq:
566 get_bad_stack
567 bad_save_user_regs
568 bl do_fiq
569
570#endif
401bb30b 571#endif /* CONFIG_SPL_BUILD */