]> git.ipfire.org Git - people/ms/u-boot.git/blame - arch/arm/cpu/arm946es/cpu.c
arm: Move cpu/$CPU to arch/arm/cpu/$CPU
[people/ms/u-boot.git] / arch / arm / cpu / arm946es / cpu.c
CommitLineData
74f4304e
WD
1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
792a09eb 7 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
74f4304e
WD
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
fe7eb5d8 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
74f4304e
WD
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/*
29 * CPU specific code
30 */
31
32#include <common.h>
33#include <command.h>
677e62f4 34#include <asm/system.h>
74f4304e 35
b3acb6cd 36static void cache_flush(void);
74f4304e 37
74f4304e
WD
38int cleanup_before_linux (void)
39{
40 /*
41 * this function is called just before we call linux
42 * it prepares the processor for linux
43 *
44 * we turn off caches etc ...
45 */
46
74f4304e
WD
47 disable_interrupts ();
48
fe7eb5d8
WD
49 /* ARM926E-S needs the protection unit enabled for the icache to have
50 * been enabled - left for possible later use
74f4304e 51 * should turn off the protection unit as well....
fe7eb5d8 52 */
74f4304e 53 /* turn off I/D-cache */
b3acb6cd
JCPV
54 icache_disable();
55 dcache_disable();
74f4304e 56 /* flush I/D-cache */
b3acb6cd
JCPV
57 cache_flush();
58
59 return 0;
74f4304e
WD
60}
61
b3acb6cd
JCPV
62/* flush I/D-cache */
63static void cache_flush (void)
74f4304e 64{
b3acb6cd 65 unsigned long i = 0;
74f4304e 66
b3acb6cd
JCPV
67 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
68 asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
74f4304e 69}