projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 74f4304e WD |
2 | /* |
| 3 | * armboot - Startup Code for ARM926EJS CPU-core | |
| 4 | * | |
| 5 | * Copyright (c) 2003 Texas Instruments | |
| 6 | * | |
| 7 | * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ | |
| 8 | * | |
| fa82f871 AA |
9 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 10 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> | |
| 792a09eb | 11 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
| 74f4304e WD |
12 | * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> |
| 13 | * Copyright (c) 2003 Kshitij <kshitij@ti.com> | |
| 57b4bce9 | 14 | * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> |
| 74f4304e WD |
15 | */ |
| 16 | ||
| 25ddd1fb | 17 | #include <asm-offsets.h> |
| 74f4304e | 18 | #include <config.h> |
| 74f4304e | 19 | |
| 74f4304e WD |
20 | /* |
| 21 | ************************************************************************* | |
| 22 | * | |
| 23 | * Startup Code (reset vector) | |
| 24 | * | |
| 25 | * do important init only if we don't start from memory! | |
| 26 | * setup Memory and board specific bits prior to relocation. | |
| 27 | * relocate armboot to ram | |
| 28 | * setup stack | |
| 29 | * | |
| 30 | ************************************************************************* | |
| 31 | */ | |
| 32 | ||
| 41623c91 | 33 | .globl reset |
| 5a8a87ed HS |
34 | |
| 35 | reset: | |
| 36 | /* | |
| 37 | * set the cpu to SVC32 mode | |
| 38 | */ | |
| 39 | mrs r0,cpsr | |
| 40 | bic r0,r0,#0x1f | |
| 41 | orr r0,r0,#0xd3 | |
| 42 | msr cpsr,r0 | |
| 43 | ||
| 44 | /* | |
| 45 | * we do sys-critical inits only at reboot, | |
| 46 | * not when booting from ram! | |
| 47 | */ | |
| a2ac2b96 | 48 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
| 5a8a87ed HS |
49 | bl cpu_init_crit |
| 50 | #endif | |
| 51 | ||
| e05e5de7 | 52 | bl _main |
| 5a8a87ed HS |
53 | |
| 54 | /*------------------------------------------------------------------------------*/ | |
| 55 | ||
| e05e5de7 AA |
56 | .globl c_runtime_cpu_setup |
| 57 | c_runtime_cpu_setup: | |
| 58 | ||
| 59 | mov pc, lr | |
| 60 | ||
| 74f4304e WD |
61 | /* |
| 62 | ************************************************************************* | |
| 63 | * | |
| 64 | * CPU_init_critical registers | |
| 65 | * | |
| 66 | * setup important registers | |
| 67 | * setup memory timing | |
| 68 | * | |
| 69 | ************************************************************************* | |
| 70 | */ | |
| 71 | ||
| 72 | ||
| a2ac2b96 | 73 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
| 74f4304e WD |
74 | cpu_init_crit: |
| 75 | /* | |
| 76 | * flush v4 I/D caches | |
| 77 | */ | |
| 78 | mov r0, #0 | |
| 79 | mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */ | |
| 80 | mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */ | |
| 81 | ||
| 82 | /* | |
| 83 | * disable MMU stuff and caches | |
| 84 | */ | |
| 85 | mrc p15, 0, r0, c1, c0, 0 | |
| 86 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ | |
| 87 | bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ | |
| ba10b852 | 88 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ |
| 74f4304e WD |
89 | orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ |
| 90 | mcr p15, 0, r0, c1, c0, 0 | |
| 91 | ||
| a2ac2b96 | 92 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) |
| 74f4304e WD |
93 | /* |
| 94 | * Go setup Memory and board specific bits prior to relocation. | |
| 95 | */ | |
| 96 | mov ip, lr /* perserve link reg across call */ | |
| 87cb6862 | 97 | bl lowlevel_init /* go setup memory */ |
| 74f4304e | 98 | mov lr, ip /* restore link */ |
| b5bd0982 | 99 | #endif |
| 74f4304e | 100 | mov pc, lr /* back to my caller */ |
| 8fc3bb4b | 101 | #endif |