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acf15001 1if CPU_V7A
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2
3config CPU_V7_HAS_NONSEC
4 bool
5
6config CPU_V7_HAS_VIRT
7 bool
8
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MY
9config ARCH_SUPPORT_PSCI
10 bool
11
ea624e19 12config ARMV7_NONSEC
ab65006b 13 bool "Enable support for booting in non-secure mode" if EXPERT
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14 depends on CPU_V7_HAS_NONSEC
15 default y
16 ---help---
17 Say Y here to enable support for booting in non-secure / SVC mode.
18
8bc347e2 19config ARMV7_BOOT_SEC_DEFAULT
ab65006b 20 bool "Boot in secure mode by default" if EXPERT
8bc347e2 21 depends on ARMV7_NONSEC
18138ab2 22 default y if ARCH_TEGRA
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23 ---help---
24 Say Y here to boot in secure mode by default even if non-secure mode
25 is supported. This option is useful to boot kernels which do not
26 suppport booting in non-secure mode. Only set this if you need it.
62a3b7dd 27 This can be overridden at run-time by setting the bootm_boot_mode env.
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28 variable to "sec" or "nonsec".
29
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30config HAS_ARMV7_SECURE_BASE
31 bool "Enable support for a ahardware secure memory area"
32 default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
33 || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
34
35config ARMV7_SECURE_BASE
36 hex "Base address for secure mode memory"
37 depends on HAS_ARMV7_SECURE_BASE
38 default 0xfff00000 if TEGRA124
39 default 0x2ffc0000 if ARCH_STM32MP
40 default 0x2f000000 if ARCH_MX7ULP
41 default 0x10010000 if ARCH_LS1021A
42 default 0x00900000 if ARCH_MX7
43 default 0x00044000 if MACH_SUN8I
44 default 0x00020000 if MACH_SUN6I || MACH_SUN7I
45
46config ARMV7_SECURE_RESERVE_SIZE
47 hex
48 depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
49 default 0x100000
50 help
51 Reserve top 1M for secure RAM
52
53config ARMV7_SECURE_MAX_SIZE
54 hex
55 depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \
56 || MACH_SUN7I || MACH_SUN8I
57 default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
58 default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
59 default 0x10000
60
ea624e19 61config ARMV7_VIRT
ab65006b 62 bool "Enable support for hardware virtualization" if EXPERT
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63 depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
64 default y
65 ---help---
66 Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
67
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MY
68config ARMV7_PSCI
69 bool "Enable PSCI support" if EXPERT
70 depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
71 default y
72 help
73 Say Y here to enable PSCI support.
74
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75choice
76 prompt "Supported PSCI version"
77 depends on ARMV7_PSCI
7f772fbc 78 default ARMV7_PSCI_0_1 if ARCH_SUNXI
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79 default ARMV7_PSCI_1_0
80 help
81 Select the supported PSCI version.
82
83config ARMV7_PSCI_1_0
84 bool "PSCI V1.0"
85
86config ARMV7_PSCI_0_2
87 bool "PSCI V0.2"
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IZ
88
89config ARMV7_PSCI_0_1
90 bool "PSCI V0.1"
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91endchoice
92
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93config ARMV7_PSCI_NR_CPUS
94 int "Maximum supported CPUs for PSCI"
95 depends on ARMV7_NONSEC
96 default 4
97 help
98 The maximum number of CPUs supported in the PSCI firmware.
99 It is no problem to set a larger value than the number of
100 CPUs in the actual hardware implementation.
101
d990f5c8 102config ARMV7_LPAE
ab65006b 103 bool "Use LPAE page table format" if EXPERT
acf15001 104 depends on CPU_V7A
d32e86bd 105 default y if ARMV7_VIRT
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106 ---help---
107 Say Y here to use the long descriptor page table format. This is
108 required if U-Boot runs in HYP mode.
109
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110config ARMV7_SET_CORTEX_SMPEN
111 bool
112 help
1be82afa 113 Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
54232a70 114
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115config SPL_ARMV7_SET_CORTEX_SMPEN
116 bool
117 help
118 Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
119
ea624e19 120endif