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5289e83a CN |
1 | /* |
2 | * board.c | |
3 | * | |
4 | * Common board functions for AM33XX based boards | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5289e83a CN |
9 | */ |
10 | ||
11 | #include <common.h> | |
973b6638 | 12 | #include <errno.h> |
47f7bcae | 13 | #include <spl.h> |
5289e83a CN |
14 | #include <asm/arch/cpu.h> |
15 | #include <asm/arch/hardware.h> | |
8a8f084e | 16 | #include <asm/arch/omap.h> |
5289e83a CN |
17 | #include <asm/arch/ddr_defs.h> |
18 | #include <asm/arch/clock.h> | |
3b97152b | 19 | #include <asm/arch/gpio.h> |
8eb16b7f | 20 | #include <asm/arch/mem.h> |
8a8f084e | 21 | #include <asm/arch/mmc_host_def.h> |
db7dd810 | 22 | #include <asm/arch/sys_proto.h> |
5289e83a | 23 | #include <asm/io.h> |
fda35eb9 | 24 | #include <asm/emif.h> |
65d750be | 25 | #include <asm/gpio.h> |
973b6638 TR |
26 | #include <i2c.h> |
27 | #include <miiphy.h> | |
28 | #include <cpsw.h> | |
7df5cf35 IY |
29 | #include <asm/errno.h> |
30 | #include <linux/usb/ch9.h> | |
31 | #include <linux/usb/gadget.h> | |
32 | #include <linux/usb/musb.h> | |
33 | #include <asm/omap_musb.h> | |
5289e83a CN |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
3b97152b SS |
37 | static const struct gpio_bank gpio_bank_am33xx[4] = { |
38 | { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX }, | |
39 | { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX }, | |
40 | { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX }, | |
41 | { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX }, | |
42 | }; | |
43 | ||
44 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; | |
45 | ||
876bdd6d | 46 | #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) |
75a23880 | 47 | int cpu_mmc_init(bd_t *bis) |
876bdd6d | 48 | { |
0689a2ef | 49 | int ret; |
75a23880 | 50 | |
e3913f56 | 51 | ret = omap_mmc_init(0, 0, 0, -1, -1); |
0689a2ef TR |
52 | if (ret) |
53 | return ret; | |
54 | ||
e3913f56 | 55 | return omap_mmc_init(1, 0, 0, -1, -1); |
876bdd6d CN |
56 | } |
57 | #endif | |
8a8f084e CN |
58 | |
59 | void setup_clocks_for_console(void) | |
60 | { | |
61 | /* Not yet implemented */ | |
62 | return; | |
63 | } | |
7df5cf35 IY |
64 | |
65 | /* AM33XX has two MUSB controllers which can be host or gadget */ | |
66 | #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \ | |
67 | (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) | |
68 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | |
69 | ||
70 | /* USB 2.0 PHY Control */ | |
71 | #define CM_PHY_PWRDN (1 << 0) | |
72 | #define CM_PHY_OTG_PWRDN (1 << 1) | |
73 | #define OTGVDET_EN (1 << 19) | |
74 | #define OTGSESSENDEN (1 << 20) | |
75 | ||
76 | static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) | |
77 | { | |
78 | if (on) { | |
79 | clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, | |
80 | OTGVDET_EN | OTGSESSENDEN); | |
81 | } else { | |
82 | clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); | |
83 | } | |
84 | } | |
85 | ||
86 | static struct musb_hdrc_config musb_config = { | |
87 | .multipoint = 1, | |
88 | .dyn_fifo = 1, | |
89 | .num_eps = 16, | |
90 | .ram_bits = 12, | |
91 | }; | |
92 | ||
93 | #ifdef CONFIG_AM335X_USB0 | |
94 | static void am33xx_otg0_set_phy_power(u8 on) | |
95 | { | |
96 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0); | |
97 | } | |
98 | ||
99 | struct omap_musb_board_data otg0_board_data = { | |
100 | .set_phy_power = am33xx_otg0_set_phy_power, | |
101 | }; | |
102 | ||
103 | static struct musb_hdrc_platform_data otg0_plat = { | |
104 | .mode = CONFIG_AM335X_USB0_MODE, | |
105 | .config = &musb_config, | |
106 | .power = 50, | |
107 | .platform_ops = &musb_dsps_ops, | |
108 | .board_data = &otg0_board_data, | |
109 | }; | |
110 | #endif | |
111 | ||
112 | #ifdef CONFIG_AM335X_USB1 | |
113 | static void am33xx_otg1_set_phy_power(u8 on) | |
114 | { | |
115 | am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1); | |
116 | } | |
117 | ||
118 | struct omap_musb_board_data otg1_board_data = { | |
119 | .set_phy_power = am33xx_otg1_set_phy_power, | |
120 | }; | |
121 | ||
122 | static struct musb_hdrc_platform_data otg1_plat = { | |
123 | .mode = CONFIG_AM335X_USB1_MODE, | |
124 | .config = &musb_config, | |
125 | .power = 50, | |
126 | .platform_ops = &musb_dsps_ops, | |
127 | .board_data = &otg1_board_data, | |
128 | }; | |
129 | #endif | |
130 | #endif | |
131 | ||
132 | int arch_misc_init(void) | |
133 | { | |
134 | #ifdef CONFIG_AM335X_USB0 | |
135 | musb_register(&otg0_plat, &otg0_board_data, | |
81df2bab | 136 | (void *)USB0_OTG_BASE); |
7df5cf35 IY |
137 | #endif |
138 | #ifdef CONFIG_AM335X_USB1 | |
139 | musb_register(&otg1_plat, &otg1_board_data, | |
81df2bab | 140 | (void *)USB1_OTG_BASE); |
7df5cf35 IY |
141 | #endif |
142 | return 0; | |
143 | } | |
49f78365 HS |
144 | |
145 | #ifdef CONFIG_SPL_BUILD | |
146 | void rtc32k_enable(void) | |
147 | { | |
148 | struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; | |
149 | ||
150 | /* | |
151 | * Unlock the RTC's registers. For more details please see the | |
152 | * RTC_SS section of the TRM. In order to unlock we need to | |
153 | * write these specific values (keys) in this order. | |
154 | */ | |
155 | writel(0x83e70b13, &rtc->kick0r); | |
156 | writel(0x95a4f1e0, &rtc->kick1r); | |
157 | ||
158 | /* Enable the RTC 32K OSC by setting bits 3 and 6. */ | |
159 | writel((1 << 3) | (1 << 6), &rtc->osc); | |
160 | } | |
7ea7f689 HS |
161 | |
162 | #define UART_RESET (0x1 << 1) | |
163 | #define UART_CLK_RUNNING_MASK 0x1 | |
164 | #define UART_SMART_IDLE_EN (0x1 << 0x3) | |
165 | ||
166 | void uart_soft_reset(void) | |
167 | { | |
168 | struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; | |
169 | u32 regval; | |
170 | ||
171 | regval = readl(&uart_base->uartsyscfg); | |
172 | regval |= UART_RESET; | |
173 | writel(regval, &uart_base->uartsyscfg); | |
174 | while ((readl(&uart_base->uartsyssts) & | |
175 | UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) | |
176 | ; | |
177 | ||
178 | /* Disable smart idle */ | |
179 | regval = readl(&uart_base->uartsyscfg); | |
180 | regval |= UART_SMART_IDLE_EN; | |
181 | writel(regval, &uart_base->uartsyscfg); | |
182 | } | |
49f78365 | 183 | #endif |