[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / am33xx / ddr.c

/*
 * DDR Configuration for AM33xx devices.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>

/**
 * Base address for EMIF instances
 */
static struct emif_reg_struct *emif_reg[2] = {
				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};

/**
 * Base addresses for DDR PHY cmd/data regs
 */
static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
				(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};

static struct ddr_data_regs *ddr_data_reg[2] = {
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
				(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};

/**
 * Base address for ddr io control instances
 */
static struct ddr_cmdtctrl *ioctrl_reg = {
			(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};

/**
 * Configure SDRAM
 */
void config_sdram(const struct emif_regs *regs, int nr)
{
	if (regs->zq_config) {
		/*
		 * A value of 0x2800 for the REF CTRL will give us
		 * about 570us for a delay, which will be long enough
		 * to configure things.
		 */
		writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
		writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
		writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	}
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
}

/**
 * Set SDRAM timings
 */
void set_sdram_timings(const struct emif_regs *regs, int nr)
{
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
}

/**
 * Configure DDR PHY
 */
void config_ddr_phy(const struct emif_regs *regs, int nr)
{
	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	writel(regs->emif_ddr_phy_ctlr_1,
		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
}

/**
 * Configure DDR CMD control registers
 */
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);

	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);

	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}

/**
 * Configure DDR DATA registers
 */
void config_ddr_data(const struct ddr_data *data, int nr)
{
	int i;

	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
		writel(data->datardsratio0,
			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
		writel(data->datawdsratio0,
			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
		writel(data->datawiratio0,
			&(ddr_data_reg[nr]+i)->dt0wiratio0);
		writel(data->datagiratio0,
			&(ddr_data_reg[nr]+i)->dt0giratio0);
		writel(data->datafwsratio0,
			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
		writel(data->datawrsratio0,
			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
		writel(data->datauserank0delay,
			&(ddr_data_reg[nr]+i)->dt0rdelays0);
		writel(data->datadldiff0,
			&(ddr_data_reg[nr]+i)->dt0dldiff0);
	}
}

void config_io_ctrl(unsigned long val)
{
	writel(val, &ioctrl_reg->cm0ioctl);
	writel(val, &ioctrl_reg->cm1ioctl);
	writel(val, &ioctrl_reg->cm2ioctl);
	writel(val, &ioctrl_reg->dt0ioctl);
	writel(val, &ioctrl_reg->dt1ioctl);
}
Commit	Line	Data
62d7fe7c CN	1	/*
	2	* DDR Configuration for AM33xx devices.
	3	*
1a459660	4	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
62d7fe7c	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
62d7fe7c CN	7	*/
	8
	9	#include <asm/arch/cpu.h>
	10	#include <asm/arch/ddr_defs.h>
6995a289	11	#include <asm/arch/sys_proto.h>
62d7fe7c	12	#include <asm/io.h>
7d5eb349	13	#include <asm/emif.h>
62d7fe7c CN	14
	15	/**
	16	* Base address for EMIF instances
	17	*/
3ba65f97 MP	18	static struct emif_reg_struct *emif_reg[2] = {
	19	(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
	20	(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
62d7fe7c CN	21
62d7fe7c CN	22	/**
3ba65f97	23	* Base addresses for DDR PHY cmd/data regs
62d7fe7c	24	*/
3ba65f97 MP	25	static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
	26	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
	27	(struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
	28
	29	static struct ddr_data_regs *ddr_data_reg[2] = {
	30	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
	31	(struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
62d7fe7c CN	32
	33	/**
	34	* Base address for ddr io control instances
	35	*/
	36	static struct ddr_cmdtctrl *ioctrl_reg = {
	37	(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
	38
62d7fe7c CN	39	/**
	40	* Configure SDRAM
	41	*/
3ba65f97	42	void config_sdram(const struct emif_regs *regs, int nr)
62d7fe7c	43	{
1c382ead TR	44	if (regs->zq_config) {
	45	/*
	46	* A value of 0x2800 for the REF CTRL will give us
	47	* about 570us for a delay, which will be long enough
	48	* to configure things.
	49	*/
3ba65f97 MP	50	writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
3ba65f97 MP	51	writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
6995a289	52	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
3ba65f97 MP	53	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
	54	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	55	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
6995a289	56	}
3ba65f97 MP	57	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
	58	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
	59	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
62d7fe7c CN	60	}
	61
	62	/**
	63	* Set SDRAM timings
	64	*/
3ba65f97	65	void set_sdram_timings(const struct emif_regs *regs, int nr)
62d7fe7c	66	{
3ba65f97 MP	67	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
	68	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
	69	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
	70	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
	71	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
	72	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
62d7fe7c CN	73	}
	74
	75	/**
	76	* Configure DDR PHY
	77	*/
3ba65f97	78	void config_ddr_phy(const struct emif_regs *regs, int nr)
62d7fe7c	79	{
3ba65f97 MP	80	writel(regs->emif_ddr_phy_ctlr_1,
	81	&emif_reg[nr]->emif_ddr_phy_ctrl_1);
	82	writel(regs->emif_ddr_phy_ctlr_1,
	83	&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
62d7fe7c CN	84	}
	85
	86	/**
	87	* Configure DDR CMD control registers
	88	*/
3ba65f97	89	void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
62d7fe7c	90	{
3ba65f97 MP	91	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
	92	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
	93	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
62d7fe7c	94
3ba65f97 MP	95	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
	96	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
	97	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
62d7fe7c	98
3ba65f97 MP	99	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
	100	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
	101	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
62d7fe7c CN	102	}
	103
	104	/**
	105	* Configure DDR DATA registers
	106	*/
3ba65f97	107	void config_ddr_data(const struct ddr_data *data, int nr)
62d7fe7c	108	{
3ba65f97 MP	109	int i;
	110
	111	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
	112	writel(data->datardsratio0,
	113	&(ddr_data_reg[nr]+i)->dt0rdsratio0);
	114	writel(data->datawdsratio0,
	115	&(ddr_data_reg[nr]+i)->dt0wdsratio0);
	116	writel(data->datawiratio0,
	117	&(ddr_data_reg[nr]+i)->dt0wiratio0);
	118	writel(data->datagiratio0,
	119	&(ddr_data_reg[nr]+i)->dt0giratio0);
	120	writel(data->datafwsratio0,
	121	&(ddr_data_reg[nr]+i)->dt0fwsratio0);
	122	writel(data->datawrsratio0,
	123	&(ddr_data_reg[nr]+i)->dt0wrsratio0);
	124	writel(data->datauserank0delay,
	125	&(ddr_data_reg[nr]+i)->dt0rdelays0);
	126	writel(data->datadldiff0,
	127	&(ddr_data_reg[nr]+i)->dt0dldiff0);
	128	}
62d7fe7c CN	129	}
62d7fe7c CN	130
5ac3b7ad	131	void config_io_ctrl(unsigned long val)
62d7fe7c	132	{
5ac3b7ad TR	133	writel(val, &ioctrl_reg->cm0ioctl);
	134	writel(val, &ioctrl_reg->cm1ioctl);
	135	writel(val, &ioctrl_reg->cm2ioctl);
	136	writel(val, &ioctrl_reg->dt0ioctl);
	137	writel(val, &ioctrl_reg->dt1ioctl);
62d7fe7c	138	}