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am33xx: refactor emif4/ddr to support multiple EMIF instances
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / am33xx / emif4.c
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1/*
2 * emif4.c
3 *
4 * AM33XX emif4 configuration file
5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <common.h>
20#include <asm/arch/cpu.h>
21#include <asm/arch/ddr_defs.h>
22#include <asm/arch/hardware.h>
23#include <asm/arch/clock.h>
b971dfad 24#include <asm/arch/sys_proto.h>
62d7fe7c 25#include <asm/io.h>
fda35eb9 26#include <asm/emif.h>
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27
28DECLARE_GLOBAL_DATA_PTR;
29
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30int dram_init(void)
31{
32 /* dram_init must store complete ramsize in gd->ram_size */
33 gd->ram_size = get_ram_size(
34 (void *)CONFIG_SYS_SDRAM_BASE,
35 CONFIG_MAX_RAM_BANK_SIZE);
36 return 0;
37}
38
39void dram_init_banksize(void)
40{
41 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
42 gd->bd->bi_dram[0].size = gd->ram_size;
43}
44
45
8a8f084e 46#ifdef CONFIG_SPL_BUILD
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47static struct vtp_reg *vtpreg[2] = {
48 (struct vtp_reg *)VTP0_CTRL_ADDR,
49 (struct vtp_reg *)VTP1_CTRL_ADDR};
50#ifdef CONFIG_AM33XX
942d3f01 51static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
3ba65f97 52#endif
942d3f01 53
3ba65f97 54static void config_vtp(int nr)
62d7fe7c 55{
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56 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
57 &vtpreg[nr]->vtp0ctrlreg);
58 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
59 &vtpreg[nr]->vtp0ctrlreg);
60 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
61 &vtpreg[nr]->vtp0ctrlreg);
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62
63 /* Poll for READY */
3ba65f97 64 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
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65 VTP_CTRL_READY)
66 ;
67}
68
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69void config_ddr(unsigned int pll, unsigned int ioctrl,
70 const struct ddr_data *data, const struct cmd_control *ctrl,
3ba65f97 71 const struct emif_regs *regs, int nr)
62d7fe7c 72{
318f27c9 73 enable_emif_clocks();
c00f69db 74 ddr_pll_config(pll);
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75 config_vtp(nr);
76 config_cmd_ctrl(ctrl, nr);
62d7fe7c 77
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78 config_ddr_data(data, nr);
79#ifdef CONFIG_AM33XX
c00f69db 80 config_io_ctrl(ioctrl);
62d7fe7c 81
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82 /* Set CKE to be controlled by EMIF/DDR PHY */
83 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
3ba65f97 84#endif
62d7fe7c 85
318f27c9 86 /* Program EMIF instance */
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87 config_ddr_phy(regs, nr);
88 set_sdram_timings(regs, nr);
89 config_sdram(regs, nr);
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90}
91#endif