projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3225f34e BS |
1 | /* |
| 2 | * (C) Copyright 2007-2008 | |
| 3 | * Stelian Pop <stelian@popies.net> | |
| 4 | * Lead Tech Design <www.leadtechdesign.com> | |
| 5 | * | |
| 6 | * (C) Copyright 2013 | |
| 7 | * Bo Shen <voice.shen@atmel.com> | |
| 8 | * | |
| 1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
| 3225f34e BS |
10 | */ |
| 11 | ||
| 12 | #include <common.h> | |
| 13 | #include <asm/io.h> | |
| 14 | #include <asm/arch/hardware.h> | |
| 15 | #include <asm/arch/at91_pit.h> | |
| 16 | #include <asm/arch/at91_pmc.h> | |
| 17 | #include <asm/arch/clk.h> | |
| 18 | #include <div64.h> | |
| 19 | ||
| 20 | #if !defined(CONFIG_AT91FAMILY) | |
| 21 | # error You need to define CONFIG_AT91FAMILY in your board config! | |
| 22 | #endif | |
| 23 | ||
| 24 | DECLARE_GLOBAL_DATA_PTR; | |
| 25 | ||
| 26 | /* | |
| 27 | * We're using the SAMA5D3x PITC in 32 bit mode, by | |
| 28 | * setting the 20 bit counter period to its maximum (0xfffff). | |
| 29 | * (See the relevant data sheets to understand that this really works) | |
| 30 | * | |
| 31 | * We do also mimic the typical powerpc way of incrementing | |
| 32 | * two 32 bit registers called tbl and tbu. | |
| 33 | * | |
| 34 | * Those registers increment at 1/16 the main clock rate. | |
| 35 | */ | |
| 36 | ||
| 37 | #define TIMER_LOAD_VAL 0xfffff | |
| 38 | ||
| 39 | static inline unsigned long long tick_to_time(unsigned long long tick) | |
| 40 | { | |
| 41 | tick *= CONFIG_SYS_HZ; | |
| 42 | do_div(tick, gd->arch.timer_rate_hz); | |
| 43 | ||
| 44 | return tick; | |
| 45 | } | |
| 46 | ||
| 47 | static inline unsigned long long usec_to_tick(unsigned long long usec) | |
| 48 | { | |
| 49 | usec *= gd->arch.timer_rate_hz; | |
| 50 | do_div(usec, 1000000); | |
| 51 | ||
| 52 | return usec; | |
| 53 | } | |
| 54 | ||
| 55 | /* | |
| 56 | * Use the PITC in full 32 bit incrementing mode | |
| 57 | */ | |
| 58 | int timer_init(void) | |
| 59 | { | |
| 60 | at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; | |
| 61 | ||
| 62 | /* Enable PITC Clock */ | |
| 63 | at91_periph_clk_enable(ATMEL_ID_SYS); | |
| 64 | ||
| 65 | /* Enable PITC */ | |
| 66 | writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); | |
| 67 | ||
| 68 | gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; | |
| 69 | gd->arch.tbu = 0; | |
| 70 | gd->arch.tbl = 0; | |
| 71 | ||
| 72 | return 0; | |
| 73 | } | |
| 74 | ||
| 75 | /* | |
| 76 | * Get the current 64 bit timer tick count | |
| 77 | */ | |
| 78 | unsigned long long get_ticks(void) | |
| 79 | { | |
| 80 | at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; | |
| 81 | ||
| 82 | ulong now = readl(&pit->piir); | |
| 83 | ||
| 84 | /* increment tbu if tbl has rolled over */ | |
| 85 | if (now < gd->arch.tbl) | |
| 86 | gd->arch.tbu++; | |
| 87 | gd->arch.tbl = now; | |
| 88 | return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; | |
| 89 | } | |
| 90 | ||
| 91 | void __udelay(unsigned long usec) | |
| 92 | { | |
| 93 | unsigned long long start; | |
| 94 | ulong tmo; | |
| 95 | ||
| 96 | start = get_ticks(); /* get current timestamp */ | |
| 97 | tmo = usec_to_tick(usec); /* convert usecs to ticks */ | |
| 98 | while ((get_ticks() - start) < tmo) | |
| 99 | ; /* loop till time has passed */ | |
| 100 | } | |
| 101 | ||
| 102 | /* | |
| 103 | * get_timer(base) can be used to check for timeouts or | |
| 104 | * to measure elasped time relative to an event: | |
| 105 | * | |
| 106 | * ulong start_time = get_timer(0) sets start_time to the current | |
| 107 | * time value. | |
| 108 | * get_timer(start_time) returns the time elapsed since then. | |
| 109 | * | |
| 110 | * The time is used in CONFIG_SYS_HZ units! | |
| 111 | */ | |
| 112 | ulong get_timer(ulong base) | |
| 113 | { | |
| 114 | return tick_to_time(get_ticks()) - base; | |
| 115 | } | |
| 116 | ||
| 117 | /* | |
| 118 | * Return the number of timer ticks per second. | |
| 119 | */ | |
| 120 | ulong get_tbclk(void) | |
| 121 | { | |
| 122 | return gd->arch.timer_rate_hz; | |
| 123 | } |