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0b02b184 DB |
1 | /* |
2 | * (C) Copyright 2008 Texas Insturments | |
3 | * | |
4 | * (C) Copyright 2002 | |
5 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | * Marius Groeger <mgroeger@sysgo.de> | |
7 | * | |
8 | * (C) Copyright 2002 | |
792a09eb | 9 | * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
0b02b184 | 10 | * |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
0b02b184 DB |
12 | */ |
13 | ||
14 | /* | |
15 | * CPU specific code | |
16 | */ | |
17 | ||
18 | #include <common.h> | |
19 | #include <command.h> | |
677e62f4 | 20 | #include <asm/system.h> |
06e758e7 | 21 | #include <asm/cache.h> |
c2dd0d45 | 22 | #include <asm/armv7.h> |
53e6f6a6 | 23 | #include <linux/compiler.h> |
0b02b184 | 24 | |
53e6f6a6 MP |
25 | void __weak cpu_cache_initialization(void){} |
26 | ||
0b02b184 DB |
27 | int cleanup_before_linux(void) |
28 | { | |
0b02b184 DB |
29 | /* |
30 | * this function is called just before we call linux | |
31 | * it prepares the processor for linux | |
32 | * | |
33 | * we turn off caches etc ... | |
34 | */ | |
d460587a | 35 | #ifndef CONFIG_SPL_BUILD |
0b02b184 | 36 | disable_interrupts(); |
d460587a | 37 | #endif |
0b02b184 | 38 | |
c2dd0d45 A |
39 | /* |
40 | * Turn off I-cache and invalidate it | |
41 | */ | |
0b02b184 | 42 | icache_disable(); |
c2dd0d45 | 43 | invalidate_icache_all(); |
0b02b184 | 44 | |
c2dd0d45 A |
45 | /* |
46 | * turn off D-cache | |
47 | * dcache_disable() in turn flushes the d-cache and disables MMU | |
48 | */ | |
49 | dcache_disable(); | |
dc7100f4 | 50 | v7_outer_cache_disable(); |
0b02b184 | 51 | |
c2dd0d45 A |
52 | /* |
53 | * After D-cache is flushed and before it is disabled there may | |
54 | * be some new valid entries brought into the cache. We are sure | |
55 | * that these lines are not dirty and will not affect our execution. | |
56 | * (because unwinding the call-stack and setting a bit in CP15 SCTRL | |
57 | * is all we did during this. We have not pushed anything on to the | |
58 | * stack. Neither have we affected any static data) | |
59 | * So just invalidate the entire d-cache again to avoid coherency | |
60 | * problems for kernel | |
61 | */ | |
62 | invalidate_dcache_all(); | |
0b02b184 | 63 | |
53e6f6a6 MP |
64 | /* |
65 | * Some CPU need more cache attention before starting the kernel. | |
66 | */ | |
67 | cpu_cache_initialization(); | |
68 | ||
0b02b184 DB |
69 | return 0; |
70 | } |