[thirdparty/u-boot.git] / arch / arm / cpu / armv7 / exynos / exynos5_setup.h

/*
 * Machine Specific Values for SMDK5250 board based on EXYNOS5
 *
 * Copyright (C) 2012 Samsung Electronics
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SMDK5250_SETUP_H
#define _SMDK5250_SETUP_H

#include <config.h>
#include <asm/arch/dmc.h>

/* APLL_CON1	*/
#define APLL_CON1_VAL	(0x00203800)

/* MPLL_CON1	*/
#define MPLL_CON1_VAL   (0x00203800)

/* CPLL_CON1	*/
#define CPLL_CON1_VAL	(0x00203800)

/* GPLL_CON1	*/
#define GPLL_CON1_VAL	(0x00203800)

/* EPLL_CON1, CON2	*/
#define EPLL_CON1_VAL	0x00000000
#define EPLL_CON2_VAL	0x00000080

/* VPLL_CON1, CON2	*/
#define VPLL_CON1_VAL	0x00000000
#define VPLL_CON2_VAL	0x00000080

/* BPLL_CON1	*/
#define BPLL_CON1_VAL	0x00203800

/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)

/* CLK_SRC_CPU	*/
/* 0 = MOUTAPLL,  1 = SCLKMPLL	*/
#define MUX_HPM_SEL             0
#define MUX_CPU_SEL             0
#define MUX_APLL_SEL            1

#define CLK_SRC_CPU_VAL		((MUX_HPM_SEL << 20)    \
				| (MUX_CPU_SEL << 16)  \
				| (MUX_APLL_SEL))

/* MEMCONTROL register bit fields */
#define DMC_MEMCONTROL_CLK_STOP_DISABLE	(0 << 0)
#define DMC_MEMCONTROL_DPWRDN_DISABLE	(0 << 1)
#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE	(0 << 2)
#define DMC_MEMCONTROL_TP_DISABLE	(0 << 4)
#define DMC_MEMCONTROL_DSREF_DISABLE	(0 << 5)
#define DMC_MEMCONTROL_DSREF_ENABLE	(1 << 5)
#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x)    (x << 6)

#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3  (7 << 8)
#define DMC_MEMCONTROL_MEM_TYPE_DDR3    (6 << 8)
#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2  (5 << 8)

#define DMC_MEMCONTROL_MEM_WIDTH_32BIT  (2 << 12)

#define DMC_MEMCONTROL_NUM_CHIP_1       (0 << 16)
#define DMC_MEMCONTROL_NUM_CHIP_2       (1 << 16)

#define DMC_MEMCONTROL_BL_8             (3 << 20)
#define DMC_MEMCONTROL_BL_4             (2 << 20)

#define DMC_MEMCONTROL_PZQ_DISABLE      (0 << 24)

#define DMC_MEMCONTROL_MRR_BYTE_7_0     (0 << 25)
#define DMC_MEMCONTROL_MRR_BYTE_15_8    (1 << 25)
#define DMC_MEMCONTROL_MRR_BYTE_23_16   (2 << 25)
#define DMC_MEMCONTROL_MRR_BYTE_31_24   (3 << 25)

/* MEMCONFIG0 register bit fields */
#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED     (1 << 12)
#define DMC_MEMCONFIGX_CHIP_COL_10              (3 << 8)
#define DMC_MEMCONFIGX_CHIP_ROW_14              (2 << 4)
#define DMC_MEMCONFIGX_CHIP_ROW_15              (3 << 4)
#define DMC_MEMCONFIGX_CHIP_BANK_8              (3 << 0)

#define DMC_MEMBASECONFIGX_CHIP_BASE(x)         (x << 16)
#define DMC_MEMBASECONFIGX_CHIP_MASK(x)         (x << 0)
#define DMC_MEMBASECONFIG_VAL(x)        (       \
	DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
	DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
)

#define DMC_MEMBASECONFIG0_VAL  DMC_MEMBASECONFIG_VAL(0x40)
#define DMC_MEMBASECONFIG1_VAL  DMC_MEMBASECONFIG_VAL(0x80)

#define DMC_PRECHCONFIG_VAL             0xFF000000
#define DMC_PWRDNCONFIG_VAL             0xFFFF00FF

#define DMC_CONCONTROL_RESET_VAL	0x0FFF0000
#define DFI_INIT_START		(1 << 28)
#define EMPTY			(1 << 8)
#define AREF_EN			(1 << 5)

#define DFI_INIT_COMPLETE_CHO	(1 << 2)
#define DFI_INIT_COMPLETE_CH1	(1 << 3)

#define RDLVL_COMPLETE_CHO	(1 << 14)
#define RDLVL_COMPLETE_CH1	(1 << 15)

#define CLK_STOP_EN	(1 << 0)
#define DPWRDN_EN	(1 << 1)
#define DSREF_EN	(1 << 5)

/* COJCONTROL register bit fields */
#define DMC_CONCONTROL_IO_PD_CON_DISABLE	(0 << 3)
#define DMC_CONCONTROL_AREF_EN_DISABLE		(0 << 5)
#define DMC_CONCONTROL_EMPTY_DISABLE		(0 << 8)
#define DMC_CONCONTROL_EMPTY_ENABLE		(1 << 8)
#define DMC_CONCONTROL_RD_FETCH_DISABLE		(0x0 << 12)
#define DMC_CONCONTROL_TIMEOUT_LEVEL0		(0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE	(0 << 28)

/* CLK_DIV_CPU0_VAL */
#define CLK_DIV_CPU0_VAL	((ARM2_RATIO << 28)             \
				| (APLL_RATIO << 24)            \
				| (PCLK_DBG_RATIO << 20)        \
				| (ATB_RATIO << 16)             \
				| (PERIPH_RATIO << 12)          \
				| (ACP_RATIO << 8)              \
				| (CPUD_RATIO << 4)             \
				| (ARM_RATIO))


/* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL              0x66666
#define CLK_DIV_FSYS0_VAL	       0x0BB00000

/* CLK_DIV_CPU1	*/
#define HPM_RATIO               0x2
#define COPY_RATIO              0x0

/* CLK_DIV_CPU1 = 0x00000003 */
#define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4)		\
				| (COPY_RATIO))

/* CLK_SRC_CORE0 */
#define CLK_SRC_CORE0_VAL       0x00000000

/* CLK_SRC_CORE1 */
#define CLK_SRC_CORE1_VAL       0x100

/* CLK_DIV_CORE0 */
#define CLK_DIV_CORE0_VAL       0x00120000

/* CLK_DIV_CORE1 */
#define CLK_DIV_CORE1_VAL       0x07070700

/* CLK_DIV_SYSRGT */
#define CLK_DIV_SYSRGT_VAL      0x00000111

/* CLK_DIV_ACP */
#define CLK_DIV_ACP_VAL         0x12

/* CLK_DIV_SYSLFT */
#define CLK_DIV_SYSLFT_VAL      0x00000311

/* CLK_SRC_CDREX */
#define CLK_SRC_CDREX_VAL       0x1

/* CLK_DIV_CDREX */
#define MCLK_CDREX2_RATIO       0x0
#define ACLK_EFCON_RATIO        0x1
#define MCLK_DPHY_RATIO		0x1
#define MCLK_CDREX_RATIO	0x1
#define ACLK_C2C_200_RATIO	0x1
#define C2C_CLK_400_RATIO	0x1
#define PCLK_CDREX_RATIO	0x1
#define ACLK_CDREX_RATIO	0x1

#define CLK_DIV_CDREX_VAL	((MCLK_DPHY_RATIO << 24)        \
				| (C2C_CLK_400_RATIO << 6)	\
				| (PCLK_CDREX_RATIO << 4)	\
				| (ACLK_CDREX_RATIO))

/* CLK_SRC_TOP0	*/
#define MUX_ACLK_300_GSCL_SEL           0x0
#define MUX_ACLK_300_GSCL_MID_SEL       0x0
#define MUX_ACLK_400_G3D_MID_SEL        0x0
#define MUX_ACLK_333_SEL	        0x0
#define MUX_ACLK_300_DISP1_SEL	        0x0
#define MUX_ACLK_300_DISP1_MID_SEL      0x0
#define MUX_ACLK_200_SEL	        0x0
#define MUX_ACLK_166_SEL	        0x0
#define CLK_SRC_TOP0_VAL	((MUX_ACLK_300_GSCL_SEL  << 25)		\
				| (MUX_ACLK_300_GSCL_MID_SEL << 24)	\
				| (MUX_ACLK_400_G3D_MID_SEL << 20)	\
				| (MUX_ACLK_333_SEL << 16)		\
				| (MUX_ACLK_300_DISP1_SEL << 15)	\
				| (MUX_ACLK_300_DISP1_MID_SEL << 14)	\
				| (MUX_ACLK_200_SEL << 12)		\
				| (MUX_ACLK_166_SEL << 8))

/* CLK_SRC_TOP1	*/
#define MUX_ACLK_400_G3D_SEL            0x1
#define MUX_ACLK_400_ISP_SEL            0x0
#define MUX_ACLK_400_IOP_SEL            0x0
#define MUX_ACLK_MIPI_HSI_TXBASE_SEL    0x0
#define MUX_ACLK_300_GSCL_MID1_SEL      0x0
#define MUX_ACLK_300_DISP1_MID1_SEL     0x0
#define CLK_SRC_TOP1_VAL	((MUX_ACLK_400_G3D_SEL << 28)           \
				|(MUX_ACLK_400_ISP_SEL << 24)           \
				|(MUX_ACLK_400_IOP_SEL << 20)           \
				|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16)   \
				|(MUX_ACLK_300_GSCL_MID1_SEL << 12)     \
				|(MUX_ACLK_300_DISP1_MID1_SEL << 8))

/* CLK_SRC_TOP2 */
#define MUX_GPLL_SEL                    0x1
#define MUX_BPLL_USER_SEL               0x0
#define MUX_MPLL_USER_SEL               0x0
#define MUX_VPLL_SEL                    0x1
#define MUX_EPLL_SEL                    0x1
#define MUX_CPLL_SEL                    0x1
#define VPLLSRC_SEL                     0x0
#define CLK_SRC_TOP2_VAL	((MUX_GPLL_SEL << 28)		\
				| (MUX_BPLL_USER_SEL << 24)	\
				| (MUX_MPLL_USER_SEL << 20)	\
				| (MUX_VPLL_SEL << 16)	        \
				| (MUX_EPLL_SEL << 12)	        \
				| (MUX_CPLL_SEL << 8)           \
				| (VPLLSRC_SEL))
/* CLK_SRC_TOP3 */
#define MUX_ACLK_333_SUB_SEL            0x1
#define MUX_ACLK_400_SUB_SEL            0x1
#define MUX_ACLK_266_ISP_SUB_SEL        0x1
#define MUX_ACLK_266_GPS_SUB_SEL        0x0
#define MUX_ACLK_300_GSCL_SUB_SEL       0x1
#define MUX_ACLK_266_GSCL_SUB_SEL       0x1
#define MUX_ACLK_300_DISP1_SUB_SEL      0x1
#define MUX_ACLK_200_DISP1_SUB_SEL      0x1
#define CLK_SRC_TOP3_VAL	((MUX_ACLK_333_SUB_SEL << 24)	        \
				| (MUX_ACLK_400_SUB_SEL << 20)	        \
				| (MUX_ACLK_266_ISP_SUB_SEL << 16)	\
				| (MUX_ACLK_266_GPS_SUB_SEL << 12)      \
				| (MUX_ACLK_300_GSCL_SUB_SEL << 10)     \
				| (MUX_ACLK_266_GSCL_SUB_SEL << 8)      \
				| (MUX_ACLK_300_DISP1_SUB_SEL << 6)     \
				| (MUX_ACLK_200_DISP1_SUB_SEL << 4))

/* CLK_DIV_TOP0	*/
#define ACLK_300_DISP1_RATIO	0x2
#define ACLK_400_G3D_RATIO	0x0
#define ACLK_333_RATIO		0x0
#define ACLK_266_RATIO		0x2
#define ACLK_200_RATIO		0x3
#define ACLK_166_RATIO		0x1
#define ACLK_133_RATIO		0x1
#define ACLK_66_RATIO		0x5

#define CLK_DIV_TOP0_VAL	((ACLK_300_DISP1_RATIO << 28)	\
				| (ACLK_400_G3D_RATIO << 24)	\
				| (ACLK_333_RATIO  << 20)	\
				| (ACLK_266_RATIO << 16)	\
				| (ACLK_200_RATIO << 12)	\
				| (ACLK_166_RATIO << 8)		\
				| (ACLK_133_RATIO << 4)		\
				| (ACLK_66_RATIO))

/* CLK_DIV_TOP1	*/
#define ACLK_MIPI_HSI_TX_BASE_RATIO     0x3
#define ACLK_66_PRE_RATIO               0x1
#define ACLK_400_ISP_RATIO              0x1
#define ACLK_400_IOP_RATIO              0x1
#define ACLK_300_GSCL_RATIO             0x2

#define CLK_DIV_TOP1_VAL	((ACLK_MIPI_HSI_TX_BASE_RATIO << 28)	\
				| (ACLK_66_PRE_RATIO << 24)		\
				| (ACLK_400_ISP_RATIO  << 20)		\
				| (ACLK_400_IOP_RATIO << 16)		\
				| (ACLK_300_GSCL_RATIO << 12))

/* APLL_LOCK	*/
#define APLL_LOCK_VAL	(0x546)
/* MPLL_LOCK	*/
#define MPLL_LOCK_VAL	(0x546)
/* CPLL_LOCK	*/
#define CPLL_LOCK_VAL	(0x546)
/* GPLL_LOCK	*/
#define GPLL_LOCK_VAL	(0x546)
/* EPLL_LOCK	*/
#define EPLL_LOCK_VAL	(0x3A98)
/* VPLL_LOCK	*/
#define VPLL_LOCK_VAL	(0x3A98)
/* BPLL_LOCK	*/
#define BPLL_LOCK_VAL	(0x546)

#define MUX_APLL_SEL_MASK	(1 << 0)
#define MUX_MPLL_SEL_MASK	(1 << 8)
#define MPLL_SEL_MOUT_MPLLFOUT	(2 << 8)
#define MUX_CPLL_SEL_MASK	(1 << 8)
#define MUX_EPLL_SEL_MASK	(1 << 12)
#define MUX_VPLL_SEL_MASK	(1 << 16)
#define MUX_GPLL_SEL_MASK	(1 << 28)
#define MUX_BPLL_SEL_MASK	(1 << 0)
#define MUX_HPM_SEL_MASK	(1 << 20)
#define HPM_SEL_SCLK_MPLL	(1 << 21)
#define APLL_CON0_LOCKED	(1 << 29)
#define MPLL_CON0_LOCKED	(1 << 29)
#define BPLL_CON0_LOCKED	(1 << 29)
#define CPLL_CON0_LOCKED	(1 << 29)
#define EPLL_CON0_LOCKED	(1 << 29)
#define GPLL_CON0_LOCKED	(1 << 29)
#define VPLL_CON0_LOCKED	(1 << 29)
#define CLK_REG_DISABLE		0x0
#define TOP2_VAL		0x0110000

/* CLK_SRC_PERIC0 */
#define PWM_SEL		6
#define UART3_SEL	6
#define UART2_SEL	6
#define UART1_SEL	6
#define UART0_SEL	6
/* SRC_CLOCK = SCLK_MPLL */
#define CLK_SRC_PERIC0_VAL	((PWM_SEL << 24)        \
				| (UART3_SEL << 12)     \
				| (UART2_SEL << 8)       \
				| (UART1_SEL << 4)      \
				| (UART0_SEL))

/* CLK_SRC_PERIC1 */
/* SRC_CLOCK = SCLK_MPLL */
#define SPI0_SEL		6
#define SPI1_SEL		6
#define SPI2_SEL		6
#define CLK_SRC_PERIC1_VAL	((SPI2_SEL << 24) \
				| (SPI1_SEL << 20) \
				| (SPI0_SEL << 16))

/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
#define SPI0_ISP_SEL		6
#define SPI1_ISP_SEL		6
#define SCLK_SRC_ISP_VAL	(SPI1_ISP_SEL << 4) \
				| (SPI0_ISP_SEL << 0)

/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
#define SPI0_ISP_RATIO		0xf
#define SPI1_ISP_RATIO		0xf
#define SCLK_DIV_ISP_VAL	(SPI1_ISP_RATIO << 12) \
				| (SPI0_ISP_RATIO << 0)

/* CLK_DIV_PERIL0	*/
#define UART5_RATIO	7
#define UART4_RATIO	7
#define UART3_RATIO	7
#define UART2_RATIO	7
#define UART1_RATIO	7
#define UART0_RATIO	7

#define CLK_DIV_PERIC0_VAL	((UART3_RATIO << 12)    \
				| (UART2_RATIO << 8)    \
				| (UART1_RATIO << 4)    \
				| (UART0_RATIO))
/* CLK_DIV_PERIC1 */
#define SPI1_RATIO		0x7
#define SPI0_RATIO		0xf
#define SPI1_SUB_RATIO		0x0
#define SPI0_SUB_RATIO		0x0
#define CLK_DIV_PERIC1_VAL	((SPI1_SUB_RATIO << 24) \
				| ((SPI1_RATIO << 16) \
				| (SPI0_SUB_RATIO << 8) \
				| (SPI0_RATIO << 0)))

/* CLK_DIV_PERIC2 */
#define SPI2_RATIO		0xf
#define SPI2_SUB_RATIO		0x0
#define CLK_DIV_PERIC2_VAL	((SPI2_SUB_RATIO << 8) \
				| (SPI2_RATIO << 0))

/* CLK_DIV_PERIC3 */
#define PWM_RATIO		8
#define CLK_DIV_PERIC3_VAL	(PWM_RATIO << 0)

/* CLK_DIV_FSYS2 */
#define MMC2_RATIO_MASK		0xf
#define MMC2_RATIO_VAL		0x3
#define MMC2_RATIO_OFFSET	0

#define MMC2_PRE_RATIO_MASK	0xff
#define MMC2_PRE_RATIO_VAL	0x9
#define MMC2_PRE_RATIO_OFFSET	8

#define MMC3_RATIO_MASK		0xf
#define MMC3_RATIO_VAL		0x1
#define MMC3_RATIO_OFFSET	16

#define MMC3_PRE_RATIO_MASK	0xff
#define MMC3_PRE_RATIO_VAL	0x0
#define MMC3_PRE_RATIO_OFFSET	24

/* CLK_SRC_LEX */
#define CLK_SRC_LEX_VAL         0x0

/* CLK_DIV_LEX */
#define CLK_DIV_LEX_VAL         0x10

/* CLK_DIV_R0X */
#define CLK_DIV_R0X_VAL         0x10

/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL         0x10

/* CLK_DIV_ISP0 */
#define CLK_DIV_ISP0_VAL        0x31

/* CLK_DIV_ISP1 */
#define CLK_DIV_ISP1_VAL        0x0

/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL        0x1

/* CLK_SRC_DISP1_0 */
#define CLK_SRC_DISP1_0_VAL	0x6

/*
 * DIV_DISP1_0
 * For DP, divisor should be 2
 */
#define CLK_DIV_DISP1_0_FIMD1	(2 << 0)

/* CLK_GATE_IP_DISP1 */
#define CLK_GATE_DP1_ALLOW	(1 << 4)

#define DDR3PHY_CTRL_PHY_RESET	(1 << 0)
#define DDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)

#define PHY_CON0_RESET_VAL	0x17020a40
#define P0_CMD_EN		(1 << 14)
#define BYTE_RDLVL_EN		(1 << 13)
#define CTRL_SHGATE		(1 << 8)

#define PHY_CON1_RESET_VAL	0x09210100
#define CTRL_GATEDURADJ_MASK	(0xf << 20)

#define PHY_CON2_RESET_VAL	0x00010004
#define INIT_DESKEW_EN		(1 << 6)
#define RDLVL_GATE_EN		(1 << 24)

/*ZQ Configurations */
#define PHY_CON16_RESET_VAL	0x08000304

#define ZQ_CLK_DIV_EN		(1 << 18)
#define ZQ_MANUAL_STR		(1 << 1)
#define ZQ_DONE			(1 << 0)

#define CTRL_RDLVL_GATE_ENABLE	1
#define CTRL_RDLVL_GATE_DISABLE	1

/* Direct Command */
#define DIRECT_CMD_NOP			0x07000000
#define DIRECT_CMD_PALL			0x01000000
#define DIRECT_CMD_ZQINIT		0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT	28
#define DIRECT_CMD_CHIP_SHIFT		20

/* DMC PHY Control0 register */
#define PHY_CONTROL0_RESET_VAL	0x0
#define MEM_TERM_EN	(1 << 31)	/* Termination enable for memory */
#define PHY_TERM_EN	(1 << 30)	/* Termination enable for PHY */
#define DMC_CTRL_SHGATE	(1 << 29)	/* Duration of DQS gating signal */
#define FP_RSYNC	(1 << 3)	/* Force DLL resyncronization */

/* Driver strength for CK, CKE, CS & CA */
#define IMP_OUTPUT_DRV_40_OHM	0x5
#define IMP_OUTPUT_DRV_30_OHM	0x7
#define CA_CK_DRVR_DS_OFFSET	9
#define CA_CKE_DRVR_DS_OFFSET	6
#define CA_CS_DRVR_DS_OFFSET	3
#define CA_ADR_DRVR_DS_OFFSET	0

#define PHY_CON42_CTRL_BSTLEN_SHIFT	8
#define PHY_CON42_CTRL_RDLAT_SHIFT	0

struct mem_timings;

/* Errors that we can encourter in low-level setup */
enum {
	SETUP_ERR_OK,
	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
};

/*
 * Memory variant specific initialization code
 *
 * @param mem		Memory timings for this memory type.
 * @param mem_iv_size	Memory interleaving size is a configurable parameter
 *			which the DMC uses to decide how to split a memory
 *			chunk into smaller chunks to support concurrent
 *			accesses; may vary across boards.
 * @param reset         Reset DDR PHY during initialization.
 * @return 0 if ok, SETUP_ERR_... if there is a problem
 */
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
			int reset);

/*
 * Configure ZQ I/O interface
 *
 * @param mem		Memory timings for this memory type.
 * @param phy0_ctrl	Pointer to struct containing PHY0 control reg
 * @param phy1_ctrl	Pointer to struct containing PHY1 control reg
 * @return 0 if ok, -1 on error
 */
int dmc_config_zq(struct mem_timings *mem,
		  struct exynos5_phy_control *phy0_ctrl,
		  struct exynos5_phy_control *phy1_ctrl);

/*
 * Send NOP and MRS/EMRS Direct commands
 *
 * @param mem		Memory timings for this memory type.
 * @param dmc		Pointer to struct of DMC registers
 */
void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc);

/*
 * Send PALL Direct commands
 *
 * @param mem		Memory timings for this memory type.
 * @param dmc		Pointer to struct of DMC registers
 */
void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);

/*
 * Configure the memconfig and membaseconfig registers
 *
 * @param mem		Memory timings for this memory type.
 * @param exynos5_dmc	Pointer to struct of DMC registers
 */
void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);

/*
 * Reset the DLL. This function is common between DDR3 and LPDDR2.
 * However, the reset value is different. So we are passing a flag
 * ddr_mode to distinguish between LPDDR2 and DDR3.
 *
 * @param exynos5_dmc	Pointer to struct of DMC registers
 * @param ddr_mode	Type of DDR memory
 */
void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
#endif
Commit	Line	Data
0aee53ba	1	/*
998e5d39	2	* Machine Specific Values for SMDK5250 board based on EXYNOS5
0aee53ba CK	3	*
	4	* Copyright (C) 2012 Samsung Electronics
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
0aee53ba CK	7	*/
	8
	9	#ifndef _SMDK5250_SETUP_H
	10	#define _SMDK5250_SETUP_H
	11
	12	#include <config.h>
998e5d39	13	#include <asm/arch/dmc.h>
0aee53ba	14
998e5d39	15	/* APLL_CON1 */
0aee53ba CK	16	#define APLL_CON1_VAL (0x00203800)
0aee53ba CK	17
998e5d39 RS	18	/* MPLL_CON1 */
998e5d39 RS	19	#define MPLL_CON1_VAL (0x00203800)
0aee53ba	20
998e5d39	21	/* CPLL_CON1 */
0aee53ba CK	22	#define CPLL_CON1_VAL (0x00203800)
0aee53ba CK	23
998e5d39 RS	24	/* GPLL_CON1 */
998e5d39 RS	25	#define GPLL_CON1_VAL (0x00203800)
0aee53ba	26
998e5d39	27	/* EPLL_CON1, CON2 */
0aee53ba CK	28	#define EPLL_CON1_VAL 0x00000000
	29	#define EPLL_CON2_VAL 0x00000080
	30
998e5d39	31	/* VPLL_CON1, CON2 */
0aee53ba CK	32	#define VPLL_CON1_VAL 0x00000000
	33	#define VPLL_CON2_VAL 0x00000080
	34
998e5d39	35	/* BPLL_CON1 */
0aee53ba CK	36	#define BPLL_CON1_VAL 0x00203800
	37
	38	/* Set PLL */
	39	#define set_pll(mdiv, pdiv, sdiv) (1<<31 \| mdiv<<16 \| pdiv<<8 \| sdiv)
	40
998e5d39 RS	41	/* CLK_SRC_CPU */
	42	/* 0 = MOUTAPLL, 1 = SCLKMPLL */
	43	#define MUX_HPM_SEL 0
	44	#define MUX_CPU_SEL 0
	45	#define MUX_APLL_SEL 1
	46
	47	#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
	48	\| (MUX_CPU_SEL << 16) \
	49	\| (MUX_APLL_SEL))
	50
	51	/* MEMCONTROL register bit fields */
	52	#define DMC_MEMCONTROL_CLK_STOP_DISABLE (0 << 0)
	53	#define DMC_MEMCONTROL_DPWRDN_DISABLE (0 << 1)
	54	#define DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE (0 << 2)
	55	#define DMC_MEMCONTROL_TP_DISABLE (0 << 4)
	56	#define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5)
	57	#define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5)
	58	#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
	59
	60	#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8)
	61	#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8)
	62	#define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
	63
	64	#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
	65
	66	#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16)
	67	#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
	68
	69	#define DMC_MEMCONTROL_BL_8 (3 << 20)
	70	#define DMC_MEMCONTROL_BL_4 (2 << 20)
	71
	72	#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
	73
	74	#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25)
	75	#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25)
	76	#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25)
	77	#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
	78
	79	/* MEMCONFIG0 register bit fields */
643be9c0 RS	80	#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12)
	81	#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8)
	82	#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4)
	83	#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4)
	84	#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)
	85
	86	#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16)
	87	#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0)
998e5d39	88	#define DMC_MEMBASECONFIG_VAL(x) ( \
643be9c0 RS	89	DMC_MEMBASECONFIGX_CHIP_BASE(x) \| \
643be9c0 RS	90	DMC_MEMBASECONFIGX_CHIP_MASK(0x780) \
998e5d39 RS	91	)
	92
	93	#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40)
	94	#define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
	95
	96	#define DMC_PRECHCONFIG_VAL 0xFF000000
	97	#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
	98
	99	#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000
	100	#define DFI_INIT_START (1 << 28)
	101	#define EMPTY (1 << 8)
	102	#define AREF_EN (1 << 5)
	103
	104	#define DFI_INIT_COMPLETE_CHO (1 << 2)
	105	#define DFI_INIT_COMPLETE_CH1 (1 << 3)
	106
	107	#define RDLVL_COMPLETE_CHO (1 << 14)
	108	#define RDLVL_COMPLETE_CH1 (1 << 15)
	109
	110	#define CLK_STOP_EN (1 << 0)
	111	#define DPWRDN_EN (1 << 1)
	112	#define DSREF_EN (1 << 5)
	113
	114	/* COJCONTROL register bit fields */
	115	#define DMC_CONCONTROL_IO_PD_CON_DISABLE (0 << 3)
	116	#define DMC_CONCONTROL_AREF_EN_DISABLE (0 << 5)
	117	#define DMC_CONCONTROL_EMPTY_DISABLE (0 << 8)
	118	#define DMC_CONCONTROL_EMPTY_ENABLE (1 << 8)
	119	#define DMC_CONCONTROL_RD_FETCH_DISABLE (0x0 << 12)
	120	#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
	121	#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
	122
	123	/* CLK_DIV_CPU0_VAL */
	124	#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
	125	\| (APLL_RATIO << 24) \
	126	\| (PCLK_DBG_RATIO << 20) \
	127	\| (ATB_RATIO << 16) \
	128	\| (PERIPH_RATIO << 12) \
	129	\| (ACP_RATIO << 8) \
	130	\| (CPUD_RATIO << 4) \
	131	\| (ARM_RATIO))
	132
	133
	134	/* CLK_FSYS */
	135	#define CLK_SRC_FSYS0_VAL 0x66666
	136	#define CLK_DIV_FSYS0_VAL 0x0BB00000
	137
	138	/* CLK_DIV_CPU1 */
	139	#define HPM_RATIO 0x2
	140	#define COPY_RATIO 0x0
	141
	142	/* CLK_DIV_CPU1 = 0x00000003 */
	143	#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
	144	\| (COPY_RATIO))
0aee53ba CK	145
0aee53ba CK	146	/* CLK_SRC_CORE0 */
998e5d39	147	#define CLK_SRC_CORE0_VAL 0x00000000
0aee53ba CK	148
0aee53ba CK	149	/* CLK_SRC_CORE1 */
998e5d39	150	#define CLK_SRC_CORE1_VAL 0x100
0aee53ba CK	151
0aee53ba CK	152	/* CLK_DIV_CORE0 */
998e5d39	153	#define CLK_DIV_CORE0_VAL 0x00120000
0aee53ba CK	154
0aee53ba CK	155	/* CLK_DIV_CORE1 */
998e5d39 RS	156	#define CLK_DIV_CORE1_VAL 0x07070700
	157
	158	/* CLK_DIV_SYSRGT */
	159	#define CLK_DIV_SYSRGT_VAL 0x00000111
	160
	161	/* CLK_DIV_ACP */
	162	#define CLK_DIV_ACP_VAL 0x12
	163
	164	/* CLK_DIV_SYSLFT */
	165	#define CLK_DIV_SYSLFT_VAL 0x00000311
0aee53ba CK	166
0aee53ba CK	167	/* CLK_SRC_CDREX */
998e5d39	168	#define CLK_SRC_CDREX_VAL 0x1
0aee53ba CK	169
0aee53ba CK	170	/* CLK_DIV_CDREX */
998e5d39 RS	171	#define MCLK_CDREX2_RATIO 0x0
	172	#define ACLK_EFCON_RATIO 0x1
	173	#define MCLK_DPHY_RATIO 0x1
	174	#define MCLK_CDREX_RATIO 0x1
0aee53ba CK	175	#define ACLK_C2C_200_RATIO 0x1
0aee53ba CK	176	#define C2C_CLK_400_RATIO 0x1
998e5d39	177	#define PCLK_CDREX_RATIO 0x1
0aee53ba	178	#define ACLK_CDREX_RATIO 0x1
0aee53ba	179
998e5d39 RS	180	#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
	181	\| (C2C_CLK_400_RATIO << 6) \
	182	\| (PCLK_CDREX_RATIO << 4) \
	183	\| (ACLK_CDREX_RATIO))
0aee53ba	184
998e5d39 RS	185	/* CLK_SRC_TOP0 */
	186	#define MUX_ACLK_300_GSCL_SEL 0x0
	187	#define MUX_ACLK_300_GSCL_MID_SEL 0x0
	188	#define MUX_ACLK_400_G3D_MID_SEL 0x0
	189	#define MUX_ACLK_333_SEL 0x0
	190	#define MUX_ACLK_300_DISP1_SEL 0x0
	191	#define MUX_ACLK_300_DISP1_MID_SEL 0x0
	192	#define MUX_ACLK_200_SEL 0x0
	193	#define MUX_ACLK_166_SEL 0x0
	194	#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
	195	\| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
	196	\| (MUX_ACLK_400_G3D_MID_SEL << 20) \
	197	\| (MUX_ACLK_333_SEL << 16) \
	198	\| (MUX_ACLK_300_DISP1_SEL << 15) \
0aee53ba	199	\| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
998e5d39	200	\| (MUX_ACLK_200_SEL << 12) \
0aee53ba CK	201	\| (MUX_ACLK_166_SEL << 8))
0aee53ba CK	202
998e5d39 RS	203	/* CLK_SRC_TOP1 */
	204	#define MUX_ACLK_400_G3D_SEL 0x1
	205	#define MUX_ACLK_400_ISP_SEL 0x0
	206	#define MUX_ACLK_400_IOP_SEL 0x0
	207	#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
	208	#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
	209	#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
	210	#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
	211	\|(MUX_ACLK_400_ISP_SEL << 24) \
	212	\|(MUX_ACLK_400_IOP_SEL << 20) \
	213	\|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
	214	\|(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
	215	\|(MUX_ACLK_300_DISP1_MID1_SEL << 8))
0aee53ba CK	216
0aee53ba CK	217	/* CLK_SRC_TOP2 */
998e5d39 RS	218	#define MUX_GPLL_SEL 0x1
	219	#define MUX_BPLL_USER_SEL 0x0
	220	#define MUX_MPLL_USER_SEL 0x0
	221	#define MUX_VPLL_SEL 0x1
	222	#define MUX_EPLL_SEL 0x1
	223	#define MUX_CPLL_SEL 0x1
	224	#define VPLLSRC_SEL 0x0
	225	#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
	226	\| (MUX_BPLL_USER_SEL << 24) \
	227	\| (MUX_MPLL_USER_SEL << 20) \
	228	\| (MUX_VPLL_SEL << 16) \
	229	\| (MUX_EPLL_SEL << 12) \
	230	\| (MUX_CPLL_SEL << 8) \
0aee53ba CK	231	\| (VPLLSRC_SEL))
0aee53ba CK	232	/* CLK_SRC_TOP3 */
998e5d39 RS	233	#define MUX_ACLK_333_SUB_SEL 0x1
	234	#define MUX_ACLK_400_SUB_SEL 0x1
	235	#define MUX_ACLK_266_ISP_SUB_SEL 0x1
	236	#define MUX_ACLK_266_GPS_SUB_SEL 0x0
	237	#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
	238	#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
	239	#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
	240	#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
	241	#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
	242	\| (MUX_ACLK_400_SUB_SEL << 20) \
	243	\| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
	244	\| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
	245	\| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
	246	\| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
	247	\| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
	248	\| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
	249
	250	/* CLK_DIV_TOP0 */
	251	#define ACLK_300_DISP1_RATIO 0x2
	252	#define ACLK_400_G3D_RATIO 0x0
	253	#define ACLK_333_RATIO 0x0
0aee53ba CK	254	#define ACLK_266_RATIO 0x2
0aee53ba CK	255	#define ACLK_200_RATIO 0x3
998e5d39	256	#define ACLK_166_RATIO 0x1
0aee53ba CK	257	#define ACLK_133_RATIO 0x1
0aee53ba CK	258	#define ACLK_66_RATIO 0x5
998e5d39 RS	259
	260	#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
	261	\| (ACLK_400_G3D_RATIO << 24) \
	262	\| (ACLK_333_RATIO << 20) \
	263	\| (ACLK_266_RATIO << 16) \
	264	\| (ACLK_200_RATIO << 12) \
	265	\| (ACLK_166_RATIO << 8) \
	266	\| (ACLK_133_RATIO << 4) \
0aee53ba CK	267	\| (ACLK_66_RATIO))
0aee53ba CK	268
998e5d39 RS	269	/* CLK_DIV_TOP1 */
	270	#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
	271	#define ACLK_66_PRE_RATIO 0x1
	272	#define ACLK_400_ISP_RATIO 0x1
	273	#define ACLK_400_IOP_RATIO 0x1
	274	#define ACLK_300_GSCL_RATIO 0x2
	275
	276	#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
	277	\| (ACLK_66_PRE_RATIO << 24) \
	278	\| (ACLK_400_ISP_RATIO << 20) \
	279	\| (ACLK_400_IOP_RATIO << 16) \
	280	\| (ACLK_300_GSCL_RATIO << 12))
	281
	282	/* APLL_LOCK */
	283	#define APLL_LOCK_VAL (0x546)
	284	/* MPLL_LOCK */
	285	#define MPLL_LOCK_VAL (0x546)
	286	/* CPLL_LOCK */
	287	#define CPLL_LOCK_VAL (0x546)
	288	/* GPLL_LOCK */
	289	#define GPLL_LOCK_VAL (0x546)
	290	/* EPLL_LOCK */
	291	#define EPLL_LOCK_VAL (0x3A98)
	292	/* VPLL_LOCK */
	293	#define VPLL_LOCK_VAL (0x3A98)
	294	/* BPLL_LOCK */
	295	#define BPLL_LOCK_VAL (0x546)
	296
	297	#define MUX_APLL_SEL_MASK (1 << 0)
	298	#define MUX_MPLL_SEL_MASK (1 << 8)
	299	#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
	300	#define MUX_CPLL_SEL_MASK (1 << 8)
	301	#define MUX_EPLL_SEL_MASK (1 << 12)
	302	#define MUX_VPLL_SEL_MASK (1 << 16)
	303	#define MUX_GPLL_SEL_MASK (1 << 28)
	304	#define MUX_BPLL_SEL_MASK (1 << 0)
	305	#define MUX_HPM_SEL_MASK (1 << 20)
	306	#define HPM_SEL_SCLK_MPLL (1 << 21)
	307	#define APLL_CON0_LOCKED (1 << 29)
	308	#define MPLL_CON0_LOCKED (1 << 29)
	309	#define BPLL_CON0_LOCKED (1 << 29)
	310	#define CPLL_CON0_LOCKED (1 << 29)
	311	#define EPLL_CON0_LOCKED (1 << 29)
	312	#define GPLL_CON0_LOCKED (1 << 29)
	313	#define VPLL_CON0_LOCKED (1 << 29)
	314	#define CLK_REG_DISABLE 0x0
	315	#define TOP2_VAL 0x0110000
0aee53ba CK	316
0aee53ba CK	317	/* CLK_SRC_PERIC0 */
f9e4d046	318	#define PWM_SEL 6
998e5d39 RS	319	#define UART3_SEL 6
	320	#define UART2_SEL 6
	321	#define UART1_SEL 6
	322	#define UART0_SEL 6
	323	/* SRC_CLOCK = SCLK_MPLL */
	324	#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
	325	\| (UART3_SEL << 12) \
	326	\| (UART2_SEL << 8) \
	327	\| (UART1_SEL << 4) \
	328	\| (UART0_SEL))
	329
	330	/* CLK_SRC_PERIC1 */
0aee53ba	331	/* SRC_CLOCK = SCLK_MPLL */
998e5d39 RS	332	#define SPI0_SEL 6
	333	#define SPI1_SEL 6
	334	#define SPI2_SEL 6
	335	#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
	336	\| (SPI1_SEL << 20) \
	337	\| (SPI0_SEL << 16))
	338
	339	/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
	340	#define SPI0_ISP_SEL 6
	341	#define SPI1_ISP_SEL 6
	342	#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
	343	\| (SPI0_ISP_SEL << 0)
	344
	345	/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
	346	#define SPI0_ISP_RATIO 0xf
	347	#define SPI1_ISP_RATIO 0xf
	348	#define SCLK_DIV_ISP_VAL (SPI1_ISP_RATIO << 12) \
	349	\| (SPI0_ISP_RATIO << 0)
	350
	351	/* CLK_DIV_PERIL0 */
	352	#define UART5_RATIO 7
	353	#define UART4_RATIO 7
	354	#define UART3_RATIO 7
	355	#define UART2_RATIO 7
	356	#define UART1_RATIO 7
	357	#define UART0_RATIO 7
	358
	359	#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
	360	\| (UART2_RATIO << 8) \
	361	\| (UART1_RATIO << 4) \
	362	\| (UART0_RATIO))
	363	/* CLK_DIV_PERIC1 */
	364	#define SPI1_RATIO 0x7
	365	#define SPI0_RATIO 0xf
	366	#define SPI1_SUB_RATIO 0x0
	367	#define SPI0_SUB_RATIO 0x0
	368	#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
	369	\| ((SPI1_RATIO << 16) \
	370	\| (SPI0_SUB_RATIO << 8) \
	371	\| (SPI0_RATIO << 0)))
	372
	373	/* CLK_DIV_PERIC2 */
	374	#define SPI2_RATIO 0xf
	375	#define SPI2_SUB_RATIO 0x0
	376	#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
	377	\| (SPI2_RATIO << 0))
0aee53ba CK	378
	379	/* CLK_DIV_PERIC3 */
	380	#define PWM_RATIO 8
	381	#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
	382
998e5d39 RS	383	/* CLK_DIV_FSYS2 */
	384	#define MMC2_RATIO_MASK 0xf
	385	#define MMC2_RATIO_VAL 0x3
	386	#define MMC2_RATIO_OFFSET 0
	387
	388	#define MMC2_PRE_RATIO_MASK 0xff
	389	#define MMC2_PRE_RATIO_VAL 0x9
	390	#define MMC2_PRE_RATIO_OFFSET 8
	391
	392	#define MMC3_RATIO_MASK 0xf
	393	#define MMC3_RATIO_VAL 0x1
	394	#define MMC3_RATIO_OFFSET 16
	395
	396	#define MMC3_PRE_RATIO_MASK 0xff
	397	#define MMC3_PRE_RATIO_VAL 0x0
	398	#define MMC3_PRE_RATIO_OFFSET 24
	399
0aee53ba	400	/* CLK_SRC_LEX */
998e5d39	401	#define CLK_SRC_LEX_VAL 0x0
0aee53ba CK	402
0aee53ba CK	403	/* CLK_DIV_LEX */
998e5d39	404	#define CLK_DIV_LEX_VAL 0x10
0aee53ba CK	405
0aee53ba CK	406	/* CLK_DIV_R0X */
998e5d39	407	#define CLK_DIV_R0X_VAL 0x10
0aee53ba CK	408
0aee53ba CK	409	/* CLK_DIV_L0X */
998e5d39	410	#define CLK_DIV_R1X_VAL 0x10
0aee53ba	411
0aee53ba	412	/* CLK_DIV_ISP0 */
998e5d39	413	#define CLK_DIV_ISP0_VAL 0x31
0aee53ba CK	414
0aee53ba CK	415	/* CLK_DIV_ISP1 */
998e5d39	416	#define CLK_DIV_ISP1_VAL 0x0
0aee53ba CK	417
0aee53ba CK	418	/* CLK_DIV_ISP2 */
998e5d39 RS	419	#define CLK_DIV_ISP2_VAL 0x1
	420
	421	/* CLK_SRC_DISP1_0 */
	422	#define CLK_SRC_DISP1_0_VAL 0x6
0aee53ba	423
998e5d39 RS	424	/*
	425	* DIV_DISP1_0
	426	* For DP, divisor should be 2
	427	*/
	428	#define CLK_DIV_DISP1_0_FIMD1 (2 << 0)
	429
	430	/* CLK_GATE_IP_DISP1 */
	431	#define CLK_GATE_DP1_ALLOW (1 << 4)
0aee53ba	432
998e5d39 RS	433	#define DDR3PHY_CTRL_PHY_RESET (1 << 0)
998e5d39 RS	434	#define DDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
0aee53ba	435
998e5d39 RS	436	#define PHY_CON0_RESET_VAL 0x17020a40
998e5d39 RS	437	#define P0_CMD_EN (1 << 14)
0aee53ba	438	#define BYTE_RDLVL_EN (1 << 13)
998e5d39	439	#define CTRL_SHGATE (1 << 8)
0aee53ba	440
998e5d39 RS	441	#define PHY_CON1_RESET_VAL 0x09210100
998e5d39 RS	442	#define CTRL_GATEDURADJ_MASK (0xf << 20)
0aee53ba CK	443
0aee53ba CK	444	#define PHY_CON2_RESET_VAL 0x00010004
998e5d39 RS	445	#define INIT_DESKEW_EN (1 << 6)
998e5d39 RS	446	#define RDLVL_GATE_EN (1 << 24)
0aee53ba	447
998e5d39 RS	448	/ZQ Configurations /
998e5d39 RS	449	#define PHY_CON16_RESET_VAL 0x08000304
0aee53ba	450
998e5d39 RS	451	#define ZQ_CLK_DIV_EN (1 << 18)
	452	#define ZQ_MANUAL_STR (1 << 1)
	453	#define ZQ_DONE (1 << 0)
	454
	455	#define CTRL_RDLVL_GATE_ENABLE 1
	456	#define CTRL_RDLVL_GATE_DISABLE 1
	457
	458	/* Direct Command */
	459	#define DIRECT_CMD_NOP 0x07000000
	460	#define DIRECT_CMD_PALL 0x01000000
	461	#define DIRECT_CMD_ZQINIT 0x0a000000
	462	#define DIRECT_CMD_CHANNEL_SHIFT 28
	463	#define DIRECT_CMD_CHIP_SHIFT 20
	464
	465	/* DMC PHY Control0 register */
	466	#define PHY_CONTROL0_RESET_VAL 0x0
	467	#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
	468	#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
	469	#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
	470	#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
	471
	472	/* Driver strength for CK, CKE, CS & CA */
	473	#define IMP_OUTPUT_DRV_40_OHM 0x5
	474	#define IMP_OUTPUT_DRV_30_OHM 0x7
	475	#define CA_CK_DRVR_DS_OFFSET 9
	476	#define CA_CKE_DRVR_DS_OFFSET 6
	477	#define CA_CS_DRVR_DS_OFFSET 3
	478	#define CA_ADR_DRVR_DS_OFFSET 0
	479
	480	#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
	481	#define PHY_CON42_CTRL_RDLAT_SHIFT 0
	482
	483	struct mem_timings;
	484
	485	/* Errors that we can encourter in low-level setup */
	486	enum {
	487	SETUP_ERR_OK,
	488	SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
	489	SETUP_ERR_ZQ_CALIBRATION_FAILURE = -2,
	490	};
0aee53ba	491
87f2e079 RS	492	/*
	493	* Memory variant specific initialization code
	494	*
	495	* @param mem Memory timings for this memory type.
	496	* @param mem_iv_size Memory interleaving size is a configurable parameter
	497	* which the DMC uses to decide how to split a memory
	498	* chunk into smaller chunks to support concurrent
	499	* accesses; may vary across boards.
643be9c0	500	* @param reset Reset DDR PHY during initialization.
87f2e079 RS	501	* @return 0 if ok, SETUP_ERR_... if there is a problem
87f2e079 RS	502	*/
643be9c0 RS	503	int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
643be9c0 RS	504	int reset);
87f2e079 RS	505
	506	/*
	507	* Configure ZQ I/O interface
	508	*
	509	* @param mem Memory timings for this memory type.
	510	* @param phy0_ctrl Pointer to struct containing PHY0 control reg
	511	* @param phy1_ctrl Pointer to struct containing PHY1 control reg
	512	* @return 0 if ok, -1 on error
	513	*/
	514	int dmc_config_zq(struct mem_timings *mem,
	515	struct exynos5_phy_control *phy0_ctrl,
	516	struct exynos5_phy_control *phy1_ctrl);
	517
	518	/*
	519	* Send NOP and MRS/EMRS Direct commands
	520	*
	521	* @param mem Memory timings for this memory type.
	522	* @param dmc Pointer to struct of DMC registers
	523	*/
	524	void dmc_config_mrs(struct mem_timings mem, struct exynos5_dmc dmc);
	525
	526	/*
	527	* Send PALL Direct commands
	528	*
	529	* @param mem Memory timings for this memory type.
	530	* @param dmc Pointer to struct of DMC registers
	531	*/
	532	void dmc_config_prech(struct mem_timings mem, struct exynos5_dmc dmc);
	533
	534	/*
	535	* Configure the memconfig and membaseconfig registers
	536	*
	537	* @param mem Memory timings for this memory type.
	538	* @param exynos5_dmc Pointer to struct of DMC registers
	539	*/
	540	void dmc_config_memory(struct mem_timings mem, struct exynos5_dmc dmc);
	541
	542	/*
	543	* Reset the DLL. This function is common between DDR3 and LPDDR2.
	544	* However, the reset value is different. So we are passing a flag
	545	* ddr_mode to distinguish between LPDDR2 and DDR3.
	546	*
	547	* @param exynos5_dmc Pointer to struct of DMC registers
	548	* @param ddr_mode Type of DDR memory
	549	*/
	550	void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);
0aee53ba	551	#endif