[people/ms/u-boot.git] / arch / arm / cpu / armv7 / keystone / clock.c

/*
 * Keystone2: pll initialization
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <asm-generic/errno.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>

static void wait_for_completion(const struct pll_init_data *data)
{
	int i;
	for (i = 0; i < 100; i++) {
		sdelay(450);
		if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
			break;
	}
}

struct pll_regs {
	u32	reg0, reg1;
};

static const struct pll_regs pll_regs[] = {
	[CORE_PLL]	= { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
	[PASS_PLL]	= { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
	[TETRIS_PLL]	= { KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
	[DDR3A_PLL]	= { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
	[DDR3B_PLL]	= { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};

/* Fout = Fref * NF(mult) / NR(prediv) / OD */
static unsigned long pll_freq_get(int pll)
{
	unsigned long mult = 1, prediv = 1, output_div = 2;
	unsigned long ret;
	u32 tmp, reg;

	if (pll == CORE_PLL) {
		ret = external_clk[sys_clk];
		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
			/* PLL mode */
			tmp = __raw_readl(KS2_MAINPLLCTL0);
			prediv = (tmp & PLL_DIV_MASK) + 1;
			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
				(pllctl_reg_read(pll, mult) &
				 PLLM_MULT_LO_MASK)) + 1;
			output_div = ((pllctl_reg_read(pll, secctl) >>
				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;

			ret = ret / prediv / output_div * mult;
		}
	} else {
		switch (pll) {
		case PASS_PLL:
			ret = external_clk[pa_clk];
			reg = KS2_PASSPLLCTL0;
			break;
		case TETRIS_PLL:
			ret = external_clk[tetris_clk];
			reg = KS2_ARMPLLCTL0;
			break;
		case DDR3A_PLL:
			ret = external_clk[ddr3a_clk];
			reg = KS2_DDR3APLLCTL0;
			break;
		case DDR3B_PLL:
			ret = external_clk[ddr3b_clk];
			reg = KS2_DDR3BPLLCTL0;
			break;
		default:
			return 0;
		}

		tmp = __raw_readl(reg);

		if (!(tmp & PLLCTL_BYPASS)) {
			/* Bypass disabled */
			prediv = (tmp & PLL_DIV_MASK) + 1;
			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
				      PLL_CLKOD_MASK) + 1;
			ret = ((ret / prediv) * mult) / output_div;
		}
	}

	return ret;
}

unsigned long clk_get_rate(unsigned int clk)
{
	switch (clk) {
	case core_pll_clk:	return pll_freq_get(CORE_PLL);
	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
	case sys_clk0_1_clk:
	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
	default:
		break;
	}
	return 0;
}

void init_pll(const struct pll_init_data *data)
{
	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;

	pllm = data->pll_m - 1;
	plld = (data->pll_d - 1) & PLL_DIV_MASK;
	pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;

	if (data->pll == MAIN_PLL) {
		/* The requered delay before main PLL configuration */
		sdelay(210000);

		tmp = pllctl_reg_read(data->pll, secctl);

		if (tmp & (PLLCTL_BYPASS)) {
			setbits_le32(pll_regs[data->pll].reg1,
				     BIT(MAIN_ENSAT_OFFSET));

			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
					   PLLCTL_PLLENSRC);
			sdelay(340);

			pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
			pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
			sdelay(21000);

			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
		} else {
			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
					   PLLCTL_PLLENSRC);
			sdelay(340);
		}

		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);

		clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
				(pllm << 6));

		/* Set the BWADJ     (12 bit field)  */
		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
		clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
				(tmp_ctl >> 8));

		/*
		 * Set the pll divider (6 bit field) *
		 * PLLD[5:0] is located in MAINPLLCTL0
		 */
		clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);

		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
			       (pllod << PLL_CLKOD_SHIFT));
		wait_for_completion(data);

		pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
		pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
		pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
		pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
		pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);

		pllctl_reg_setbits(data->pll, alnctl, 0x1f);

		/*
		 * Set GOSET bit in PLLCMD to initiate the GO operation
		 * to change the divide
		 */
		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
		sdelay(1500); /* wait for the phase adj */
		wait_for_completion(data);

		/* Reset PLL */
		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
		sdelay(21000);	/* Wait for a minimum of 7 us*/
		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
		sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */

		pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);

		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);

	} else if (data->pll == TETRIS_PLL) {
		bwadj = pllm >> 1;
		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
		setbits_le32(pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
		/*
		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
		 * only applicable for Kepler
		 */
		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
		setbits_le32(pll_regs[data->pll].reg1 ,
			     PLL_PLLRST | PLLCTL_ENSAT);

		/*
		 * 3 Program PLLM and PLLD in PLLCTL0 register
		 * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
		 * PLLCTL1 register. BWADJ value must be set
		 * to ((PLLM + 1) >> 1) – 1)
		 */
		tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
			(pllm << 6) |
			(plld & PLL_DIV_MASK) |
			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
		__raw_writel(tmp, pll_regs[data->pll].reg0);

		/* Set BWADJ[11:8] bits */
		tmp = __raw_readl(pll_regs[data->pll].reg1);
		tmp &= ~(PLL_BWADJ_HI_MASK);
		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
		__raw_writel(tmp, pll_regs[data->pll].reg1);
		/*
		 * 5 Wait for at least 5 us based on the reference
		 * clock (PLL reset time)
		 */
		sdelay(21000);	/* Wait for a minimum of 7 us*/

		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
		clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
		/*
		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
		 * (PLL lock time)
		 */
		sdelay(105000);
		/* 8 disable bypass */
		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
		/*
		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
		 * only applicable for Kepler
		 */
		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
	} else {
		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
		/*
		 * process keeps state of Bypass bit while programming
		 * all other DDR PLL settings
		 */
		tmp = __raw_readl(pll_regs[data->pll].reg0);
		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */

		/*
		 * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
		 * bypass disabled
		 */
		bwadj = pllm >> 1;
		tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
			(pllm << PLL_MULT_SHIFT) |
			(plld & PLL_DIV_MASK) |
			(pllod << PLL_CLKOD_SHIFT);
		__raw_writel(tmp, pll_regs[data->pll].reg0);

		/* Set BWADJ[11:8] bits */
		tmp = __raw_readl(pll_regs[data->pll].reg1);
		tmp &= ~(PLL_BWADJ_HI_MASK);
		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);

		/* set PLL Select (bit 13) for PASS PLL */
		if (data->pll == PASS_PLL)
			tmp |= PLLCTL_PAPLL;

		__raw_writel(tmp, pll_regs[data->pll].reg1);

		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
		tmp = PLL_PLLRST;
		/* Set RESET bit = 1 */
		setbits_le32(pll_regs[data->pll].reg1, tmp);
		/* Wait for a minimum of 7 us*/
		sdelay(21000);
		/* Clear RESET bit */
		clrbits_le32(pll_regs[data->pll].reg1, tmp);
		sdelay(105000);

		/* clear BYPASS (Enable PLL Mode) */
		clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
		sdelay(21000);	/* Wait for a minimum of 7 us*/
	}

	/*
	 * This is required to provide a delay between multiple
	 * consequent PPL configurations
	 */
	sdelay(210000);
}

void init_plls(int num_pll, struct pll_init_data *config)
{
	int i;

	for (i = 0; i < num_pll; i++)
		init_pll(&config[i]);
}
Commit	Line	Data
ef509b90 VA	1	/*
	2	* Keystone2: pll initialization
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#include <common.h>
	11	#include <asm-generic/errno.h>
	12	#include <asm/io.h>
	13	#include <asm/processor.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/clock_defs.h>
	16
	17	static void wait_for_completion(const struct pll_init_data *data)
	18	{
	19	int i;
	20	for (i = 0; i < 100; i++) {
	21	sdelay(450);
	22	if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
	23	break;
	24	}
	25	}
	26
	27	struct pll_regs {
	28	u32 reg0, reg1;
	29	};
	30
	31	static const struct pll_regs pll_regs[] = {
3d315386 KI	32	[CORE_PLL] = { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
	33	[PASS_PLL] = { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
	34	[TETRIS_PLL] = { KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
	35	[DDR3A_PLL] = { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
	36	[DDR3B_PLL] = { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
ef509b90 VA	37	};
	38
	39	/* Fout = Fref * NF(mult) / NR(prediv) / OD */
	40	static unsigned long pll_freq_get(int pll)
	41	{
	42	unsigned long mult = 1, prediv = 1, output_div = 2;
	43	unsigned long ret;
	44	u32 tmp, reg;
	45
	46	if (pll == CORE_PLL) {
	47	ret = external_clk[sys_clk];
	48	if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
	49	/* PLL mode */
3d315386	50	tmp = __raw_readl(KS2_MAINPLLCTL0);
ef509b90 VA	51	prediv = (tmp & PLL_DIV_MASK) + 1;
	52	mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) \|
	53	(pllctl_reg_read(pll, mult) &
	54	PLLM_MULT_LO_MASK)) + 1;
	55	output_div = ((pllctl_reg_read(pll, secctl) >>
	56	PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
	57
	58	ret = ret / prediv / output_div * mult;
	59	}
	60	} else {
	61	switch (pll) {
	62	case PASS_PLL:
	63	ret = external_clk[pa_clk];
3d315386	64	reg = KS2_PASSPLLCTL0;
ef509b90 VA	65	break;
	66	case TETRIS_PLL:
	67	ret = external_clk[tetris_clk];
3d315386	68	reg = KS2_ARMPLLCTL0;
ef509b90 VA	69	break;
	70	case DDR3A_PLL:
	71	ret = external_clk[ddr3a_clk];
3d315386	72	reg = KS2_DDR3APLLCTL0;
ef509b90 VA	73	break;
	74	case DDR3B_PLL:
	75	ret = external_clk[ddr3b_clk];
3d315386	76	reg = KS2_DDR3BPLLCTL0;
ef509b90 VA	77	break;
	78	default:
	79	return 0;
	80	}
	81
	82	tmp = __raw_readl(reg);
	83
	84	if (!(tmp & PLLCTL_BYPASS)) {
	85	/* Bypass disabled */
	86	prediv = (tmp & PLL_DIV_MASK) + 1;
	87	mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
	88	output_div = ((tmp >> PLL_CLKOD_SHIFT) &
	89	PLL_CLKOD_MASK) + 1;
	90	ret = ((ret / prediv) * mult) / output_div;
	91	}
	92	}
	93
	94	return ret;
	95	}
	96
	97	unsigned long clk_get_rate(unsigned int clk)
	98	{
	99	switch (clk) {
	100	case core_pll_clk: return pll_freq_get(CORE_PLL);
	101	case pass_pll_clk: return pll_freq_get(PASS_PLL);
	102	case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
	103	case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
	104	case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
	105	case sys_clk0_1_clk:
	106	case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
	107	case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
	108	case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
	109	case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
	110	case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
	111	case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
	112	case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
	113	case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
	114	case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
	115	case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
	116	case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
	117	case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
	118	case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
	119	case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
	120	case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
	121	default:
	122	break;
	123	}
	124	return 0;
	125	}
	126
	127	void init_pll(const struct pll_init_data *data)
	128	{
	129	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
	130
	131	pllm = data->pll_m - 1;
	132	plld = (data->pll_d - 1) & PLL_DIV_MASK;
	133	pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
	134
	135	if (data->pll == MAIN_PLL) {
	136	/* The requered delay before main PLL configuration */
	137	sdelay(210000);
	138
	139	tmp = pllctl_reg_read(data->pll, secctl);
	140
141	if (tmp & (PLLCTL_BYPASS)) {
142	setbits_le32(pll_regs[data->pll].reg1,
143	BIT(MAIN_ENSAT_OFFSET));
144
145	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN \|
146	PLLCTL_PLLENSRC);
147	sdelay(340);
148
149	pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
150	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
151	sdelay(21000);
152
153	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
154	} else {
155	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN \|
156	PLLCTL_PLLENSRC);
157	sdelay(340);
158	}
159
160	pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
161
162	clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
163	(pllm << 6));
164
165	/* Set the BWADJ (12 bit field) */
166	tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
167	clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
168	(tmp_ctl << PLL_BWADJ_LO_SHIFT));
169	clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
170	(tmp_ctl >> 8));
171
172	/*
173	* Set the pll divider (6 bit field) *
174	* PLLD[5:0] is located in MAINPLLCTL0
175	*/
176	clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
177
178	/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
179	pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
180	(pllod << PLL_CLKOD_SHIFT));
181	wait_for_completion(data);
182
183	pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
184	pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
185	pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
186	pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
187	pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
188
189	pllctl_reg_setbits(data->pll, alnctl, 0x1f);
190
191	/*
192	* Set GOSET bit in PLLCMD to initiate the GO operation
193	* to change the divide
194	*/
195	pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
196	sdelay(1500); /* wait for the phase adj */
197	wait_for_completion(data);
198
199	/* Reset PLL */
200	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
201	sdelay(21000); /* Wait for a minimum of 7 us*/
202	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
203	sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
204
205	pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
206
207	tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
208
209	} else if (data->pll == TETRIS_PLL) {
210	bwadj = pllm >> 1;
211	/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
212	setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
213	/*
214	* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
215	* only applicable for Kepler
216	*/
3d315386	217	clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
ef509b90 VA	218	/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
	219	setbits_le32(pll_regs[data->pll].reg1 ,
	220	PLL_PLLRST \| PLLCTL_ENSAT);
	221
	222	/*
	223	* 3 Program PLLM and PLLD in PLLCTL0 register
	224	* 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
	225	* PLLCTL1 register. BWADJ value must be set
	226	* to ((PLLM + 1) >> 1) – 1)
	227	*/
	228	tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) \|
	229	(pllm << 6) \|
	230	(plld & PLL_DIV_MASK) \|
	231	(pllod << PLL_CLKOD_SHIFT) \| PLLCTL_BYPASS;
	232	__raw_writel(tmp, pll_regs[data->pll].reg0);
	233
	234	/* Set BWADJ[11:8] bits */
	235	tmp = __raw_readl(pll_regs[data->pll].reg1);
	236	tmp &= ~(PLL_BWADJ_HI_MASK);
	237	tmp \|= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
	238	__raw_writel(tmp, pll_regs[data->pll].reg1);
	239	/*
	240	* 5 Wait for at least 5 us based on the reference
	241	* clock (PLL reset time)
	242	*/
	243	sdelay(21000); /* Wait for a minimum of 7 us*/
	244
	245	/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
	246	clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
	247	/*
	248	* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
	249	* (PLL lock time)
	250	*/
	251	sdelay(105000);
	252	/* 8 disable bypass */
	253	clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
	254	/*
	255	* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
	256	* only applicable for Kepler
	257	*/
3d315386	258	setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
ef509b90 VA	259	} else {
	260	setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
	261	/*
	262	* process keeps state of Bypass bit while programming
	263	* all other DDR PLL settings
	264	*/
	265	tmp = __raw_readl(pll_regs[data->pll].reg0);
	266	tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
	267
	268	/*
	269	* Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
	270	* bypass disabled
	271	*/
	272	bwadj = pllm >> 1;
	273	tmp \|= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) \|
	274	(pllm << PLL_MULT_SHIFT) \|
	275	(plld & PLL_DIV_MASK) \|
	276	(pllod << PLL_CLKOD_SHIFT);
	277	__raw_writel(tmp, pll_regs[data->pll].reg0);
	278
	279	/* Set BWADJ[11:8] bits */
	280	tmp = __raw_readl(pll_regs[data->pll].reg1);
	281	tmp &= ~(PLL_BWADJ_HI_MASK);
	282	tmp \|= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
	283
	284	/* set PLL Select (bit 13) for PASS PLL */
	285	if (data->pll == PASS_PLL)
	286	tmp \|= PLLCTL_PAPLL;
	287
	288	__raw_writel(tmp, pll_regs[data->pll].reg1);
	289
	290	/* Reset bit: bit 14 for both DDR3 & PASS PLL */
	291	tmp = PLL_PLLRST;
	292	/* Set RESET bit = 1 */
	293	setbits_le32(pll_regs[data->pll].reg1, tmp);
	294	/* Wait for a minimum of 7 us*/
	295	sdelay(21000);
	296	/* Clear RESET bit */
	297	clrbits_le32(pll_regs[data->pll].reg1, tmp);
	298	sdelay(105000);
	299
	300	/* clear BYPASS (Enable PLL Mode) */
	301	clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
	302	sdelay(21000); /* Wait for a minimum of 7 us*/
	303	}
	304
	305	/*
	306	* This is required to provide a delay between multiple
	307	* consequent PPL configurations
	308	*/
	309	sdelay(210000);
	310	}
	311
	312	void init_plls(int num_pll, struct pll_init_data *config)
	313	{
	314	int i;
	315
	316	for (i = 0; i < num_pll; i++)
	317	init_pll(&config[i]);
	318	}