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ef509b90 VA |
1 | /* |
2 | * Keystone2: Architecture initialization | |
3 | * | |
4 | * (C) Copyright 2012-2014 | |
5 | * Texas Instruments Incorporated, <www.ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/clock.h> | |
13 | #include <asm/arch/hardware.h> | |
14 | ||
15 | void chip_configuration_unlock(void) | |
16 | { | |
17 | __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0); | |
18 | __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1); | |
19 | } | |
20 | ||
21 | int arch_cpu_init(void) | |
22 | { | |
23 | chip_configuration_unlock(); | |
24 | icache_enable(); | |
25 | ||
26 | #ifdef CONFIG_SOC_K2HK | |
27 | share_all_segments(8); | |
28 | share_all_segments(9); | |
29 | share_all_segments(10); /* QM PDSP */ | |
30 | share_all_segments(11); /* PCIE */ | |
31 | #endif | |
32 | ||
33 | return 0; | |
34 | } | |
35 | ||
36 | void reset_cpu(ulong addr) | |
37 | { | |
38 | volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); | |
39 | u32 tmp; | |
40 | ||
41 | tmp = *rstctrl & KS2_RSTCTRL_MASK; | |
42 | *rstctrl = tmp | KS2_RSTCTRL_KEY; | |
43 | ||
44 | *rstctrl &= KS2_RSTCTRL_SWRST; | |
45 | ||
46 | for (;;) | |
47 | ; | |
48 | } | |
49 | ||
50 | void enable_caches(void) | |
51 | { | |
52 | #ifndef CONFIG_SYS_DCACHE_OFF | |
53 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
54 | dcache_enable(); | |
55 | #endif | |
56 | } |