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Commit | Line | Data |
---|---|---|
0a37cf8f | 1 | config ARCH_LS1021A |
4a444176 | 2 | bool |
ba1b6fb5 YS |
3 | select SYS_FSL_ERRATUM_A008378 |
4 | select SYS_FSL_ERRATUM_A008407 | |
5 | select SYS_FSL_ERRATUM_A009663 | |
6 | select SYS_FSL_ERRATUM_A009942 | |
0a37cf8f | 7 | select SYS_FSL_ERRATUM_A010315 |
f534b8f5 YS |
8 | select SYS_FSL_SRDS_1 |
9 | select SYS_HAS_SERDES | |
d26e34c4 YS |
10 | select SYS_FSL_DDR_BE if SYS_FSL_DDR |
11 | select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR | |
12 | select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR | |
13 | select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR | |
2c2e2c9e YS |
14 | select SYS_FSL_HAS_SEC |
15 | select SYS_FSL_SEC_COMPAT_5 | |
90b80386 | 16 | select SYS_FSL_SEC_LE |
5e8bd7e1 | 17 | |
fb2bf8c2 YS |
18 | menu "LS102xA architecture" |
19 | depends on ARCH_LS1021A | |
20 | ||
19538f30 HZ |
21 | config FSL_PCIE_COMPAT |
22 | string "PCIe compatible of Kernel DT" | |
23 | depends on PCIE_LAYERSCAPE | |
24 | default "fsl,ls1021a-pcie" if ARCH_LS1021A | |
25 | help | |
26 | This compatible is used to find pci controller node in Kernel DT | |
27 | to complete fixup. | |
28 | ||
5e8bd7e1 | 29 | config LS1_DEEP_SLEEP |
4a444176 YS |
30 | bool "Deep sleep" |
31 | depends on ARCH_LS1021A | |
fb2bf8c2 | 32 | |
b4b60d06 YS |
33 | config MAX_CPUS |
34 | int "Maximum number of CPUs permitted for LS102xA" | |
35 | depends on ARCH_LS1021A | |
36 | default 2 | |
37 | help | |
38 | Set this number to the maximum number of possible CPUs in the SoC. | |
39 | SoCs may have multiple clusters with each cluster may have multiple | |
40 | ports. If some ports are reserved but higher ports are used for | |
41 | cores, count the reserved ports. This will allocate enough memory | |
42 | in spin table to properly handle all cores. | |
43 | ||
72ccd31e YS |
44 | config SECURE_BOOT |
45 | bool "Secure Boot" | |
46 | help | |
47 | Enable Freescale Secure Boot feature. Normally selected | |
48 | by defconfig. If unsure, do not change. | |
49 | ||
fb2bf8c2 YS |
50 | config SYS_FSL_ERRATUM_A010315 |
51 | bool "Workaround for PCIe erratum A010315" | |
52 | ||
f534b8f5 YS |
53 | config SYS_FSL_SRDS_1 |
54 | bool | |
55 | ||
56 | config SYS_FSL_SRDS_2 | |
57 | bool | |
58 | ||
59 | config SYS_HAS_SERDES | |
60 | bool | |
61 | ||
25af7dc1 YS |
62 | config SYS_FSL_IFC_BANK_COUNT |
63 | int "Maximum banks of Integrated flash controller" | |
64 | depends on ARCH_LS1021A | |
65 | default 8 | |
66 | ||
ba1b6fb5 YS |
67 | config SYS_FSL_ERRATUM_A008407 |
68 | bool | |
69 | ||
fb2bf8c2 | 70 | endmenu |