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Commit | Line | Data |
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64fdf452 SB |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
64fdf452 SB |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/io.h> | |
1221ce45 | 12 | #include <linux/errno.h> |
64fdf452 SB |
13 | #include <asm/arch/imx-regs.h> |
14 | #include <asm/arch/crm_regs.h> | |
e4d34492 | 15 | #include <asm/arch/clock.h> |
bf2eaf51 | 16 | #include <div64.h> |
6a376046 | 17 | #include <asm/arch/sys_proto.h> |
64fdf452 SB |
18 | |
19 | enum pll_clocks { | |
20 | PLL1_CLOCK = 0, | |
21 | PLL2_CLOCK, | |
22 | PLL3_CLOCK, | |
649dc8ab | 23 | #ifdef CONFIG_MX53 |
bf2eaf51 | 24 | PLL4_CLOCK, |
649dc8ab | 25 | #endif |
64fdf452 SB |
26 | PLL_CLOCKS, |
27 | }; | |
28 | ||
29 | struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { | |
30 | [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, | |
31 | [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, | |
32 | [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, | |
bf2eaf51 MV |
33 | #ifdef CONFIG_MX53 |
34 | [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, | |
35 | #endif | |
64fdf452 SB |
36 | }; |
37 | ||
70cc86a6 FE |
38 | #define AHB_CLK_ROOT 133333333 |
39 | #define SZ_DEC_1M 1000000 | |
40 | #define PLL_PD_MAX 16 /* Actual pd+1 */ | |
41 | #define PLL_MFI_MAX 15 | |
42 | #define PLL_MFI_MIN 5 | |
43 | #define ARM_DIV_MAX 8 | |
44 | #define IPG_DIV_MAX 4 | |
45 | #define AHB_DIV_MAX 8 | |
46 | #define EMI_DIV_MAX 8 | |
47 | #define NFC_DIV_MAX 8 | |
48 | ||
49 | #define MX5_CBCMR 0x00015154 | |
50 | #define MX5_CBCDR 0x02888945 | |
51 | ||
52 | struct fixed_pll_mfd { | |
53 | u32 ref_clk_hz; | |
54 | u32 mfd; | |
55 | }; | |
56 | ||
57 | const struct fixed_pll_mfd fixed_mfd[] = { | |
833b6435 | 58 | {MXC_HCLK, 24 * 16}, |
70cc86a6 FE |
59 | }; |
60 | ||
61 | struct pll_param { | |
62 | u32 pd; | |
63 | u32 mfi; | |
64 | u32 mfn; | |
65 | u32 mfd; | |
66 | }; | |
67 | ||
68 | #define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) | |
69 | #define PLL_FREQ_MIN(ref_clk) \ | |
70 | ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) | |
71 | #define MAX_DDR_CLK 420000000 | |
72 | #define NFC_CLK_MAX 34000000 | |
73 | ||
e4d34492 | 74 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; |
64fdf452 | 75 | |
5d2947a3 WG |
76 | void set_usboh3_clk(void) |
77 | { | |
846b3898 BT |
78 | clrsetbits_le32(&mxc_ccm->cscmr1, |
79 | MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK, | |
80 | MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1)); | |
81 | clrsetbits_le32(&mxc_ccm->cscdr1, | |
82 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK | | |
83 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK, | |
84 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) | | |
85 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1)); | |
5d2947a3 WG |
86 | } |
87 | ||
76b6b196 | 88 | void enable_usboh3_clk(bool enable) |
5d2947a3 | 89 | { |
248cdf0b BT |
90 | unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; |
91 | ||
92 | clrsetbits_le32(&mxc_ccm->CCGR2, | |
93 | MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK), | |
94 | MXC_CCM_CCGR2_USBOH3_60M(cg)); | |
5d2947a3 WG |
95 | } |
96 | ||
fac96408 | 97 | #ifdef CONFIG_SYS_I2C_MXC |
be2f93b1 | 98 | /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */ |
cc54a0f7 TK |
99 | int enable_i2c_clk(unsigned char enable, unsigned i2c_num) |
100 | { | |
cc54a0f7 TK |
101 | u32 mask; |
102 | ||
be2f93b1 BT |
103 | #if defined(CONFIG_MX51) |
104 | if (i2c_num > 1) | |
105 | #elif defined(CONFIG_MX53) | |
cc54a0f7 | 106 | if (i2c_num > 2) |
be2f93b1 | 107 | #endif |
cc54a0f7 | 108 | return -EINVAL; |
1f5e4ee0 BT |
109 | mask = MXC_CCM_CCGR_CG_MASK << |
110 | (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1)); | |
cc54a0f7 | 111 | if (enable) |
846b3898 | 112 | setbits_le32(&mxc_ccm->CCGR1, mask); |
cc54a0f7 | 113 | else |
846b3898 | 114 | clrbits_le32(&mxc_ccm->CCGR1, mask); |
cc54a0f7 TK |
115 | return 0; |
116 | } | |
117 | #endif | |
118 | ||
414e1660 | 119 | void set_usb_phy_clk(void) |
5d2947a3 | 120 | { |
846b3898 | 121 | clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); |
5d2947a3 WG |
122 | } |
123 | ||
414e1660 | 124 | #if defined(CONFIG_MX51) |
76b6b196 | 125 | void enable_usb_phy1_clk(bool enable) |
5d2947a3 | 126 | { |
248cdf0b BT |
127 | unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; |
128 | ||
414e1660 BT |
129 | clrsetbits_le32(&mxc_ccm->CCGR2, |
130 | MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK), | |
131 | MXC_CCM_CCGR2_USB_PHY(cg)); | |
5d2947a3 WG |
132 | } |
133 | ||
76b6b196 | 134 | void enable_usb_phy2_clk(bool enable) |
5d2947a3 | 135 | { |
414e1660 BT |
136 | /* i.MX51 has a single USB PHY clock, so do nothing here. */ |
137 | } | |
138 | #elif defined(CONFIG_MX53) | |
76b6b196 | 139 | void enable_usb_phy1_clk(bool enable) |
414e1660 BT |
140 | { |
141 | unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; | |
142 | ||
143 | clrsetbits_le32(&mxc_ccm->CCGR4, | |
144 | MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK), | |
145 | MXC_CCM_CCGR4_USB_PHY1(cg)); | |
5d2947a3 WG |
146 | } |
147 | ||
76b6b196 | 148 | void enable_usb_phy2_clk(bool enable) |
5d2947a3 | 149 | { |
248cdf0b BT |
150 | unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; |
151 | ||
152 | clrsetbits_le32(&mxc_ccm->CCGR4, | |
153 | MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK), | |
154 | MXC_CCM_CCGR4_USB_PHY2(cg)); | |
5d2947a3 | 155 | } |
414e1660 | 156 | #endif |
5d2947a3 | 157 | |
64fdf452 | 158 | /* |
bf2eaf51 | 159 | * Calculate the frequency of PLLn. |
64fdf452 | 160 | */ |
bf2eaf51 | 161 | static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) |
64fdf452 | 162 | { |
bf2eaf51 MV |
163 | uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret; |
164 | uint64_t refclk, temp; | |
165 | int32_t mfn_abs; | |
166 | ||
167 | ctrl = readl(&pll->ctrl); | |
168 | ||
169 | if (ctrl & MXC_DPLLC_CTL_HFSM) { | |
846b3898 BT |
170 | mfn = readl(&pll->hfs_mfn); |
171 | mfd = readl(&pll->hfs_mfd); | |
172 | op = readl(&pll->hfs_op); | |
bf2eaf51 | 173 | } else { |
846b3898 BT |
174 | mfn = readl(&pll->mfn); |
175 | mfd = readl(&pll->mfd); | |
176 | op = readl(&pll->op); | |
bf2eaf51 | 177 | } |
64fdf452 | 178 | |
bf2eaf51 MV |
179 | mfd &= MXC_DPLLC_MFD_MFD_MASK; |
180 | mfn &= MXC_DPLLC_MFN_MFN_MASK; | |
181 | pdf = op & MXC_DPLLC_OP_PDF_MASK; | |
846b3898 | 182 | mfi = MXC_DPLLC_OP_MFI_RD(op); |
bf2eaf51 MV |
183 | |
184 | /* 21.2.3 */ | |
185 | if (mfi < 5) | |
186 | mfi = 5; | |
187 | ||
188 | /* Sign extend */ | |
189 | if (mfn >= 0x04000000) { | |
190 | mfn |= 0xfc000000; | |
191 | mfn_abs = -mfn; | |
192 | } else | |
193 | mfn_abs = mfn; | |
194 | ||
195 | refclk = infreq * 2; | |
196 | if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) | |
197 | refclk *= 2; | |
198 | ||
5acc9072 | 199 | do_div(refclk, pdf + 1); |
bf2eaf51 MV |
200 | temp = refclk * mfn_abs; |
201 | do_div(temp, mfd + 1); | |
202 | ret = refclk * mfi; | |
203 | ||
204 | if ((int)mfn < 0) | |
205 | ret -= temp; | |
206 | else | |
207 | ret += temp; | |
64fdf452 | 208 | |
bf2eaf51 | 209 | return ret; |
64fdf452 SB |
210 | } |
211 | ||
b9479298 BT |
212 | #ifdef CONFIG_MX51 |
213 | /* | |
214 | * This function returns the Frequency Pre-Multiplier clock. | |
215 | */ | |
216 | static u32 get_fpm(void) | |
217 | { | |
218 | u32 mult; | |
219 | u32 ccr = readl(&mxc_ccm->ccr); | |
220 | ||
221 | if (ccr & MXC_CCM_CCR_FPM_MULT) | |
222 | mult = 1024; | |
223 | else | |
224 | mult = 512; | |
225 | ||
226 | return MXC_CLK32 * mult; | |
227 | } | |
228 | #endif | |
229 | ||
55c8df0c BT |
230 | /* |
231 | * This function returns the low power audio clock. | |
232 | */ | |
233 | static u32 get_lp_apm(void) | |
234 | { | |
235 | u32 ret_val = 0; | |
236 | u32 ccsr = readl(&mxc_ccm->ccsr); | |
237 | ||
238 | if (ccsr & MXC_CCM_CCSR_LP_APM) | |
239 | #if defined(CONFIG_MX51) | |
240 | ret_val = get_fpm(); | |
241 | #elif defined(CONFIG_MX53) | |
242 | ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); | |
243 | #endif | |
244 | else | |
245 | ret_val = MXC_HCLK; | |
246 | ||
247 | return ret_val; | |
248 | } | |
249 | ||
64fdf452 SB |
250 | /* |
251 | * Get mcu main rate | |
252 | */ | |
253 | u32 get_mcu_main_clk(void) | |
254 | { | |
255 | u32 reg, freq; | |
256 | ||
846b3898 | 257 | reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr)); |
833b6435 | 258 | freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); |
64fdf452 SB |
259 | return freq / (reg + 1); |
260 | } | |
261 | ||
262 | /* | |
263 | * Get the rate of peripheral's root clock. | |
264 | */ | |
6a376046 | 265 | u32 get_periph_clk(void) |
64fdf452 SB |
266 | { |
267 | u32 reg; | |
268 | ||
846b3898 | 269 | reg = readl(&mxc_ccm->cbcdr); |
64fdf452 | 270 | if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) |
833b6435 | 271 | return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); |
846b3898 BT |
272 | reg = readl(&mxc_ccm->cbcmr); |
273 | switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) { | |
64fdf452 | 274 | case 0: |
833b6435 | 275 | return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); |
64fdf452 | 276 | case 1: |
833b6435 | 277 | return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); |
55c8df0c BT |
278 | case 2: |
279 | return get_lp_apm(); | |
64fdf452 SB |
280 | default: |
281 | return 0; | |
282 | } | |
283 | /* NOTREACHED */ | |
284 | } | |
285 | ||
286 | /* | |
287 | * Get the rate of ipg clock. | |
288 | */ | |
289 | static u32 get_ipg_clk(void) | |
290 | { | |
95c0eb19 MV |
291 | uint32_t freq, reg, div; |
292 | ||
293 | freq = get_ahb_clk(); | |
294 | ||
846b3898 BT |
295 | reg = readl(&mxc_ccm->cbcdr); |
296 | div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1; | |
95c0eb19 MV |
297 | |
298 | return freq / div; | |
64fdf452 SB |
299 | } |
300 | ||
301 | /* | |
302 | * Get the rate of ipg_per clock. | |
303 | */ | |
304 | static u32 get_ipg_per_clk(void) | |
305 | { | |
f124e718 | 306 | u32 freq, pred1, pred2, podf; |
64fdf452 | 307 | |
846b3898 | 308 | if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) |
64fdf452 | 309 | return get_ipg_clk(); |
f124e718 BT |
310 | |
311 | if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) | |
312 | freq = get_lp_apm(); | |
313 | else | |
314 | freq = get_periph_clk(); | |
846b3898 BT |
315 | podf = readl(&mxc_ccm->cbcdr); |
316 | pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf); | |
317 | pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf); | |
318 | podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf); | |
f124e718 | 319 | return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); |
64fdf452 SB |
320 | } |
321 | ||
08028b11 BT |
322 | /* Get the output clock rate of a standard PLL MUX for peripherals. */ |
323 | static u32 get_standard_pll_sel_clk(u32 clk_sel) | |
64fdf452 | 324 | { |
01968b96 | 325 | u32 freq = 0; |
64fdf452 | 326 | |
08028b11 BT |
327 | switch (clk_sel & 0x3) { |
328 | case 0: | |
833b6435 | 329 | freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); |
64fdf452 | 330 | break; |
08028b11 | 331 | case 1: |
833b6435 | 332 | freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); |
64fdf452 | 333 | break; |
08028b11 | 334 | case 2: |
833b6435 | 335 | freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); |
64fdf452 | 336 | break; |
08028b11 BT |
337 | case 3: |
338 | freq = get_lp_apm(); | |
339 | break; | |
64fdf452 SB |
340 | } |
341 | ||
08028b11 BT |
342 | return freq; |
343 | } | |
344 | ||
345 | /* | |
346 | * Get the rate of uart clk. | |
347 | */ | |
348 | static u32 get_uart_clk(void) | |
349 | { | |
350 | unsigned int clk_sel, freq, reg, pred, podf; | |
351 | ||
352 | reg = readl(&mxc_ccm->cscmr1); | |
353 | clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); | |
354 | freq = get_standard_pll_sel_clk(clk_sel); | |
355 | ||
846b3898 BT |
356 | reg = readl(&mxc_ccm->cscdr1); |
357 | pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg); | |
358 | podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg); | |
64fdf452 SB |
359 | freq /= (pred + 1) * (podf + 1); |
360 | ||
361 | return freq; | |
362 | } | |
363 | ||
64fdf452 SB |
364 | /* |
365 | * get cspi clock rate. | |
366 | */ | |
70cc86a6 | 367 | static u32 imx_get_cspiclk(void) |
64fdf452 | 368 | { |
3cbd107b | 369 | u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; |
846b3898 BT |
370 | u32 cscmr1 = readl(&mxc_ccm->cscmr1); |
371 | u32 cscdr2 = readl(&mxc_ccm->cscdr2); | |
64fdf452 | 372 | |
846b3898 BT |
373 | pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2); |
374 | pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2); | |
375 | clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1); | |
3cbd107b BT |
376 | freq = get_standard_pll_sel_clk(clk_sel); |
377 | ret_val = freq / ((pre_pdf + 1) * (pdf + 1)); | |
64fdf452 SB |
378 | return ret_val; |
379 | } | |
380 | ||
32384656 BT |
381 | /* |
382 | * get esdhc clock rate. | |
383 | */ | |
384 | static u32 get_esdhc_clk(u32 port) | |
385 | { | |
386 | u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; | |
387 | u32 cscmr1 = readl(&mxc_ccm->cscmr1); | |
388 | u32 cscdr1 = readl(&mxc_ccm->cscdr1); | |
389 | ||
390 | switch (port) { | |
391 | case 0: | |
392 | clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1); | |
393 | pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1); | |
394 | podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1); | |
395 | break; | |
396 | case 1: | |
397 | clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1); | |
398 | pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1); | |
399 | podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1); | |
400 | break; | |
401 | case 2: | |
402 | if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL) | |
403 | return get_esdhc_clk(1); | |
404 | else | |
405 | return get_esdhc_clk(0); | |
406 | case 3: | |
407 | if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL) | |
408 | return get_esdhc_clk(1); | |
409 | else | |
410 | return get_esdhc_clk(0); | |
411 | default: | |
412 | break; | |
413 | } | |
414 | ||
415 | freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1)); | |
416 | return freq; | |
417 | } | |
418 | ||
70cc86a6 FE |
419 | static u32 get_axi_a_clk(void) |
420 | { | |
846b3898 BT |
421 | u32 cbcdr = readl(&mxc_ccm->cbcdr); |
422 | u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr); | |
70cc86a6 FE |
423 | |
424 | return get_periph_clk() / (pdf + 1); | |
425 | } | |
426 | ||
427 | static u32 get_axi_b_clk(void) | |
428 | { | |
846b3898 BT |
429 | u32 cbcdr = readl(&mxc_ccm->cbcdr); |
430 | u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr); | |
70cc86a6 FE |
431 | |
432 | return get_periph_clk() / (pdf + 1); | |
433 | } | |
434 | ||
435 | static u32 get_emi_slow_clk(void) | |
436 | { | |
846b3898 | 437 | u32 cbcdr = readl(&mxc_ccm->cbcdr); |
70cc86a6 | 438 | u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; |
846b3898 | 439 | u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr); |
70cc86a6 FE |
440 | |
441 | if (emi_clk_sel) | |
442 | return get_ahb_clk() / (pdf + 1); | |
443 | ||
444 | return get_periph_clk() / (pdf + 1); | |
445 | } | |
446 | ||
447 | static u32 get_ddr_clk(void) | |
448 | { | |
449 | u32 ret_val = 0; | |
846b3898 BT |
450 | u32 cbcmr = readl(&mxc_ccm->cbcmr); |
451 | u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); | |
70cc86a6 | 452 | #ifdef CONFIG_MX51 |
846b3898 | 453 | u32 cbcdr = readl(&mxc_ccm->cbcdr); |
70cc86a6 | 454 | if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { |
846b3898 | 455 | u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr); |
70cc86a6 | 456 | |
833b6435 | 457 | ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); |
70cc86a6 FE |
458 | ret_val /= ddr_clk_podf + 1; |
459 | ||
460 | return ret_val; | |
461 | } | |
462 | #endif | |
463 | switch (ddr_clk_sel) { | |
464 | case 0: | |
465 | ret_val = get_axi_a_clk(); | |
466 | break; | |
467 | case 1: | |
468 | ret_val = get_axi_b_clk(); | |
469 | break; | |
470 | case 2: | |
471 | ret_val = get_emi_slow_clk(); | |
472 | break; | |
473 | case 3: | |
474 | ret_val = get_ahb_clk(); | |
475 | break; | |
476 | default: | |
477 | break; | |
478 | } | |
479 | ||
480 | return ret_val; | |
481 | } | |
482 | ||
64fdf452 | 483 | /* |
70cc86a6 | 484 | * The API of get mxc clocks. |
64fdf452 SB |
485 | */ |
486 | unsigned int mxc_get_clock(enum mxc_clock clk) | |
487 | { | |
488 | switch (clk) { | |
489 | case MXC_ARM_CLK: | |
490 | return get_mcu_main_clk(); | |
491 | case MXC_AHB_CLK: | |
95c0eb19 | 492 | return get_ahb_clk(); |
64fdf452 SB |
493 | case MXC_IPG_CLK: |
494 | return get_ipg_clk(); | |
495 | case MXC_IPG_PERCLK: | |
e7bed5c2 | 496 | case MXC_I2C_CLK: |
64fdf452 SB |
497 | return get_ipg_per_clk(); |
498 | case MXC_UART_CLK: | |
499 | return get_uart_clk(); | |
500 | case MXC_CSPI_CLK: | |
501 | return imx_get_cspiclk(); | |
32384656 BT |
502 | case MXC_ESDHC_CLK: |
503 | return get_esdhc_clk(0); | |
504 | case MXC_ESDHC2_CLK: | |
505 | return get_esdhc_clk(1); | |
506 | case MXC_ESDHC3_CLK: | |
507 | return get_esdhc_clk(2); | |
508 | case MXC_ESDHC4_CLK: | |
509 | return get_esdhc_clk(3); | |
64fdf452 | 510 | case MXC_FEC_CLK: |
d5fe220d | 511 | return get_ipg_clk(); |
d87c85ce SB |
512 | case MXC_SATA_CLK: |
513 | return get_ahb_clk(); | |
70cc86a6 FE |
514 | case MXC_DDR_CLK: |
515 | return get_ddr_clk(); | |
64fdf452 SB |
516 | default: |
517 | break; | |
518 | } | |
70cc86a6 | 519 | return -EINVAL; |
64fdf452 SB |
520 | } |
521 | ||
522 | u32 imx_get_uartclk(void) | |
523 | { | |
524 | return get_uart_clk(); | |
525 | } | |
526 | ||
64fdf452 SB |
527 | u32 imx_get_fecclk(void) |
528 | { | |
d5fe220d | 529 | return get_ipg_clk(); |
64fdf452 SB |
530 | } |
531 | ||
70cc86a6 FE |
532 | static int gcd(int m, int n) |
533 | { | |
534 | int t; | |
535 | while (m > 0) { | |
536 | if (n > m) { | |
537 | t = m; | |
538 | m = n; | |
539 | n = t; | |
540 | } /* swap */ | |
541 | m -= n; | |
542 | } | |
543 | return n; | |
544 | } | |
545 | ||
546 | /* | |
547 | * This is to calculate various parameters based on reference clock and | |
548 | * targeted clock based on the equation: | |
549 | * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) | |
550 | * This calculation is based on a fixed MFD value for simplicity. | |
551 | */ | |
552 | static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) | |
553 | { | |
554 | u64 pd, mfi = 1, mfn, mfd, t1; | |
555 | u32 n_target = target; | |
556 | u32 n_ref = ref, i; | |
557 | ||
558 | /* | |
559 | * Make sure targeted freq is in the valid range. | |
560 | * Otherwise the following calculation might be wrong!!! | |
561 | */ | |
562 | if (n_target < PLL_FREQ_MIN(ref) || | |
563 | n_target > PLL_FREQ_MAX(ref)) { | |
564 | printf("Targeted peripheral clock should be" | |
565 | "within [%d - %d]\n", | |
566 | PLL_FREQ_MIN(ref) / SZ_DEC_1M, | |
567 | PLL_FREQ_MAX(ref) / SZ_DEC_1M); | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { | |
572 | if (fixed_mfd[i].ref_clk_hz == ref) { | |
573 | mfd = fixed_mfd[i].mfd; | |
574 | break; | |
575 | } | |
576 | } | |
577 | ||
578 | if (i == ARRAY_SIZE(fixed_mfd)) | |
579 | return -EINVAL; | |
580 | ||
581 | /* Use n_target and n_ref to avoid overflow */ | |
582 | for (pd = 1; pd <= PLL_PD_MAX; pd++) { | |
583 | t1 = n_target * pd; | |
584 | do_div(t1, (4 * n_ref)); | |
585 | mfi = t1; | |
586 | if (mfi > PLL_MFI_MAX) | |
587 | return -EINVAL; | |
588 | else if (mfi < 5) | |
589 | continue; | |
590 | break; | |
591 | } | |
592 | /* | |
593 | * Now got pd and mfi already | |
594 | * | |
595 | * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; | |
596 | */ | |
597 | t1 = n_target * pd; | |
598 | do_div(t1, 4); | |
599 | t1 -= n_ref * mfi; | |
600 | t1 *= mfd; | |
601 | do_div(t1, n_ref); | |
602 | mfn = t1; | |
603 | debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", | |
604 | ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); | |
605 | i = 1; | |
606 | if (mfn != 0) | |
607 | i = gcd(mfd, mfn); | |
608 | pll->pd = (u32)pd; | |
609 | pll->mfi = (u32)mfi; | |
610 | do_div(mfn, i); | |
611 | pll->mfn = (u32)mfn; | |
612 | do_div(mfd, i); | |
613 | pll->mfd = (u32)mfd; | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | #define calc_div(tgt_clk, src_clk, limit) ({ \ | |
619 | u32 v = 0; \ | |
620 | if (((src_clk) % (tgt_clk)) <= 100) \ | |
621 | v = (src_clk) / (tgt_clk); \ | |
622 | else \ | |
623 | v = ((src_clk) / (tgt_clk)) + 1;\ | |
624 | if (v > limit) \ | |
625 | v = limit; \ | |
626 | (v - 1); \ | |
627 | }) | |
628 | ||
629 | #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ | |
630 | { \ | |
846b3898 BT |
631 | writel(0x1232, &pll->ctrl); \ |
632 | writel(0x2, &pll->config); \ | |
633 | writel((((pd) - 1) << 0) | ((fi) << 4), \ | |
634 | &pll->op); \ | |
635 | writel(fn, &(pll->mfn)); \ | |
636 | writel((fd) - 1, &pll->mfd); \ | |
637 | writel((((pd) - 1) << 0) | ((fi) << 4), \ | |
638 | &pll->hfs_op); \ | |
639 | writel(fn, &pll->hfs_mfn); \ | |
640 | writel((fd) - 1, &pll->hfs_mfd); \ | |
641 | writel(0x1232, &pll->ctrl); \ | |
642 | while (!readl(&pll->ctrl) & 0x1) \ | |
70cc86a6 FE |
643 | ;\ |
644 | } | |
645 | ||
646 | static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) | |
647 | { | |
846b3898 | 648 | u32 ccsr = readl(&mxc_ccm->ccsr); |
70cc86a6 FE |
649 | struct mxc_pll_reg *pll = mxc_plls[index]; |
650 | ||
651 | switch (index) { | |
652 | case PLL1_CLOCK: | |
653 | /* Switch ARM to PLL2 clock */ | |
649dc8ab BT |
654 | writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL, |
655 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
656 | CHANGE_PLL_SETTINGS(pll, pll_param->pd, |
657 | pll_param->mfi, pll_param->mfn, | |
658 | pll_param->mfd); | |
659 | /* Switch back */ | |
649dc8ab BT |
660 | writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL, |
661 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
662 | break; |
663 | case PLL2_CLOCK: | |
664 | /* Switch to pll2 bypass clock */ | |
649dc8ab BT |
665 | writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, |
666 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
667 | CHANGE_PLL_SETTINGS(pll, pll_param->pd, |
668 | pll_param->mfi, pll_param->mfn, | |
669 | pll_param->mfd); | |
670 | /* Switch back */ | |
649dc8ab BT |
671 | writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, |
672 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
673 | break; |
674 | case PLL3_CLOCK: | |
675 | /* Switch to pll3 bypass clock */ | |
649dc8ab BT |
676 | writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL, |
677 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
678 | CHANGE_PLL_SETTINGS(pll, pll_param->pd, |
679 | pll_param->mfi, pll_param->mfn, | |
680 | pll_param->mfd); | |
681 | /* Switch back */ | |
649dc8ab BT |
682 | writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL, |
683 | &mxc_ccm->ccsr); | |
70cc86a6 | 684 | break; |
649dc8ab | 685 | #ifdef CONFIG_MX53 |
70cc86a6 FE |
686 | case PLL4_CLOCK: |
687 | /* Switch to pll4 bypass clock */ | |
649dc8ab BT |
688 | writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL, |
689 | &mxc_ccm->ccsr); | |
70cc86a6 FE |
690 | CHANGE_PLL_SETTINGS(pll, pll_param->pd, |
691 | pll_param->mfi, pll_param->mfn, | |
692 | pll_param->mfd); | |
693 | /* Switch back */ | |
649dc8ab BT |
694 | writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL, |
695 | &mxc_ccm->ccsr); | |
70cc86a6 | 696 | break; |
649dc8ab | 697 | #endif |
70cc86a6 FE |
698 | default: |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | /* Config CPU clock */ | |
706 | static int config_core_clk(u32 ref, u32 freq) | |
707 | { | |
708 | int ret = 0; | |
709 | struct pll_param pll_param; | |
710 | ||
711 | memset(&pll_param, 0, sizeof(struct pll_param)); | |
712 | ||
713 | /* The case that periph uses PLL1 is not considered here */ | |
714 | ret = calc_pll_params(ref, freq, &pll_param); | |
715 | if (ret != 0) { | |
716 | printf("Error:Can't find pll parameters: %d\n", ret); | |
717 | return ret; | |
718 | } | |
719 | ||
720 | return config_pll_clk(PLL1_CLOCK, &pll_param); | |
721 | } | |
722 | ||
723 | static int config_nfc_clk(u32 nfc_clk) | |
724 | { | |
70cc86a6 | 725 | u32 parent_rate = get_emi_slow_clk(); |
f399f636 | 726 | u32 div; |
70cc86a6 | 727 | |
f399f636 | 728 | if (nfc_clk == 0) |
70cc86a6 | 729 | return -EINVAL; |
f399f636 | 730 | div = parent_rate / nfc_clk; |
70cc86a6 FE |
731 | if (div == 0) |
732 | div++; | |
733 | if (parent_rate / div > NFC_CLK_MAX) | |
734 | div++; | |
846b3898 BT |
735 | clrsetbits_le32(&mxc_ccm->cbcdr, |
736 | MXC_CCM_CBCDR_NFC_PODF_MASK, | |
737 | MXC_CCM_CBCDR_NFC_PODF(div - 1)); | |
738 | while (readl(&mxc_ccm->cdhipr) != 0) | |
70cc86a6 FE |
739 | ; |
740 | return 0; | |
741 | } | |
742 | ||
f399f636 MV |
743 | void enable_nfc_clk(unsigned char enable) |
744 | { | |
745 | unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF; | |
746 | ||
747 | clrsetbits_le32(&mxc_ccm->CCGR5, | |
748 | MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK), | |
749 | MXC_CCM_CCGR5_EMI_ENFC(cg)); | |
750 | } | |
751 | ||
4611d5ba SA |
752 | #ifdef CONFIG_FSL_IIM |
753 | void enable_efuse_prog_supply(bool enable) | |
754 | { | |
755 | if (enable) | |
756 | setbits_le32(&mxc_ccm->cgpr, | |
757 | MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); | |
758 | else | |
759 | clrbits_le32(&mxc_ccm->cgpr, | |
760 | MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE); | |
761 | } | |
762 | #endif | |
763 | ||
70cc86a6 FE |
764 | /* Config main_bus_clock for periphs */ |
765 | static int config_periph_clk(u32 ref, u32 freq) | |
766 | { | |
767 | int ret = 0; | |
768 | struct pll_param pll_param; | |
769 | ||
770 | memset(&pll_param, 0, sizeof(struct pll_param)); | |
771 | ||
846b3898 | 772 | if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { |
70cc86a6 FE |
773 | ret = calc_pll_params(ref, freq, &pll_param); |
774 | if (ret != 0) { | |
775 | printf("Error:Can't find pll parameters: %d\n", | |
776 | ret); | |
777 | return ret; | |
778 | } | |
846b3898 BT |
779 | switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD( |
780 | readl(&mxc_ccm->cbcmr))) { | |
70cc86a6 FE |
781 | case 0: |
782 | return config_pll_clk(PLL1_CLOCK, &pll_param); | |
783 | break; | |
784 | case 1: | |
785 | return config_pll_clk(PLL3_CLOCK, &pll_param); | |
786 | break; | |
787 | default: | |
788 | return -EINVAL; | |
789 | } | |
790 | } | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static int config_ddr_clk(u32 emi_clk) | |
796 | { | |
797 | u32 clk_src; | |
798 | s32 shift = 0, clk_sel, div = 1; | |
846b3898 | 799 | u32 cbcmr = readl(&mxc_ccm->cbcmr); |
70cc86a6 FE |
800 | |
801 | if (emi_clk > MAX_DDR_CLK) { | |
802 | printf("Warning:DDR clock should not exceed %d MHz\n", | |
803 | MAX_DDR_CLK / SZ_DEC_1M); | |
804 | emi_clk = MAX_DDR_CLK; | |
805 | } | |
806 | ||
807 | clk_src = get_periph_clk(); | |
808 | /* Find DDR clock input */ | |
846b3898 | 809 | clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); |
70cc86a6 FE |
810 | switch (clk_sel) { |
811 | case 0: | |
812 | shift = 16; | |
813 | break; | |
814 | case 1: | |
815 | shift = 19; | |
816 | break; | |
817 | case 2: | |
818 | shift = 22; | |
819 | break; | |
820 | case 3: | |
821 | shift = 10; | |
822 | break; | |
823 | default: | |
824 | return -EINVAL; | |
825 | } | |
826 | ||
827 | if ((clk_src % emi_clk) < 10000000) | |
828 | div = clk_src / emi_clk; | |
829 | else | |
830 | div = (clk_src / emi_clk) + 1; | |
831 | if (div > 8) | |
832 | div = 8; | |
833 | ||
846b3898 BT |
834 | clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift); |
835 | while (readl(&mxc_ccm->cdhipr) != 0) | |
70cc86a6 | 836 | ; |
846b3898 | 837 | writel(0x0, &mxc_ccm->ccdr); |
70cc86a6 FE |
838 | |
839 | return 0; | |
840 | } | |
841 | ||
842 | /* | |
843 | * This function assumes the expected core clock has to be changed by | |
844 | * modifying the PLL. This is NOT true always but for most of the times, | |
845 | * it is. So it assumes the PLL output freq is the same as the expected | |
846 | * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. | |
847 | * In the latter case, it will try to increase the presc value until | |
848 | * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to | |
849 | * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based | |
850 | * on the targeted PLL and reference input clock to the PLL. Lastly, | |
851 | * it sets the register based on these values along with the dividers. | |
852 | * Note 1) There is no value checking for the passed-in divider values | |
853 | * so the caller has to make sure those values are sensible. | |
854 | * 2) Also adjust the NFC divider such that the NFC clock doesn't | |
855 | * exceed NFC_CLK_MAX. | |
856 | * 3) IPU HSP clock is independent of AHB clock. Even it can go up to | |
857 | * 177MHz for higher voltage, this function fixes the max to 133MHz. | |
858 | * 4) This function should not have allowed diag_printf() calls since | |
859 | * the serial driver has been stoped. But leave then here to allow | |
860 | * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). | |
861 | */ | |
862 | int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) | |
863 | { | |
864 | freq *= SZ_DEC_1M; | |
865 | ||
866 | switch (clk) { | |
867 | case MXC_ARM_CLK: | |
868 | if (config_core_clk(ref, freq)) | |
869 | return -EINVAL; | |
870 | break; | |
871 | case MXC_PERIPH_CLK: | |
872 | if (config_periph_clk(ref, freq)) | |
873 | return -EINVAL; | |
874 | break; | |
875 | case MXC_DDR_CLK: | |
876 | if (config_ddr_clk(freq)) | |
877 | return -EINVAL; | |
878 | break; | |
879 | case MXC_NFC_CLK: | |
880 | if (config_nfc_clk(freq)) | |
881 | return -EINVAL; | |
882 | break; | |
883 | default: | |
884 | printf("Warning:Unsupported or invalid clock type\n"); | |
885 | } | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
8c38b5d0 SB |
890 | #ifdef CONFIG_MX53 |
891 | /* | |
892 | * The clock for the external interface can be set to use internal clock | |
893 | * if fuse bank 4, row 3, bit 2 is set. | |
894 | * This is an undocumented feature and it was confirmed by Freescale's support: | |
895 | * Fuses (but not pins) may be used to configure SATA clocks. | |
896 | * Particularly the i.MX53 Fuse_Map contains the next information | |
897 | * about configuring SATA clocks : SATA_ALT_REF_CLK[1:0] (offset 0x180C) | |
898 | * '00' - 100MHz (External) | |
899 | * '01' - 50MHz (External) | |
900 | * '10' - 120MHz, internal (USB PHY) | |
901 | * '11' - Reserved | |
902 | */ | |
903 | void mxc_set_sata_internal_clock(void) | |
904 | { | |
905 | u32 *tmp_base = | |
906 | (u32 *)(IIM_BASE_ADDR + 0x180c); | |
907 | ||
414e1660 | 908 | set_usb_phy_clk(); |
8c38b5d0 | 909 | |
846b3898 | 910 | clrsetbits_le32(tmp_base, 0x6, 0x4); |
8c38b5d0 SB |
911 | } |
912 | #endif | |
913 | ||
64fdf452 SB |
914 | /* |
915 | * Dump some core clockes. | |
916 | */ | |
9a004418 | 917 | int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
64fdf452 SB |
918 | { |
919 | u32 freq; | |
920 | ||
833b6435 | 921 | freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); |
37a6d208 | 922 | printf("PLL1 %8d MHz\n", freq / 1000000); |
833b6435 | 923 | freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); |
37a6d208 | 924 | printf("PLL2 %8d MHz\n", freq / 1000000); |
833b6435 | 925 | freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); |
37a6d208 | 926 | printf("PLL3 %8d MHz\n", freq / 1000000); |
bf2eaf51 | 927 | #ifdef CONFIG_MX53 |
833b6435 | 928 | freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); |
37a6d208 | 929 | printf("PLL4 %8d MHz\n", freq / 1000000); |
bf2eaf51 | 930 | #endif |
37a6d208 MV |
931 | |
932 | printf("\n"); | |
933 | printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); | |
934 | printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); | |
935 | printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); | |
70cc86a6 | 936 | printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); |
081237c1 FE |
937 | #ifdef CONFIG_MXC_SPI |
938 | printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); | |
939 | #endif | |
64fdf452 SB |
940 | return 0; |
941 | } | |
942 | ||
943 | /***************************************************/ | |
944 | ||
945 | U_BOOT_CMD( | |
7acec259 SB |
946 | clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, |
947 | "display clocks", | |
64fdf452 SB |
948 | "" |
949 | ); |