[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>

/*
 * L2CC Cache setup/invalidation/disable
 */
.macro init_l2cc
	/* explicitly disable L2 cache */
	mrc 15, 0, r0, c1, c0, 1
	bic r0, r0, #0x2
	mcr 15, 0, r0, c1, c0, 1

	/* reconfigure L2 cache aux control reg */
	mov r0, #0xC0			/* tag RAM */
	add r0, r0, #0x4		/* data RAM */
	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
	orr r0, r0, #(1 << 22)		/* disable write allocate */

#if defined(CONFIG_MX51)
	ldr r1, =0x0
	ldr r3, [r1, #ROM_SI_REV]
	cmp r3, #0x10

	/* disable write combine for TO 2 and lower revs */
	orrls r0, r0, #(1 << 25)
#endif

	mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */

/* AIPS setup - Only setup MPROTx registers.
 * The PACR default values are good.*/
.macro init_aips
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	ldr r0, =AIPS1_BASE_ADDR
	ldr r1, =0x77777777
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	ldr r0, =AIPS2_BASE_ADDR
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	/*
	 * Clear the on and off peripheral modules Supervisor Protect bit
	 * for SDMA to access them. Did not change the AIPS control registers
	 * (offset 0x20) access type
	 */
.endm /* init_aips */

/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
	/* VPU and IPU given higher priority (0x4)
	 * IPU accesses with ID=0x1 given highest priority (=0xA)
	 */
	ldr r0, =M4IF_BASE_ADDR

	ldr r1, =0x00000203
	str r1, [r0, #0x40]

	ldr r1, =0x0
	str r1, [r0, #0x44]

	ldr r1, =0x00120125
	str r1, [r0, #0x9C]

	ldr r1, =0x001901A3
	str r1, [r0, #0x48]

#endif
.endm /* init_m4if */

.macro setup_pll pll, freq
	ldr r0, =\pll
	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
	mov r1, #0x2
	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */

	ldr r1, W_DP_OP_\freq
	str r1, [r0, #PLL_DP_OP]
	str r1, [r0, #PLL_DP_HFS_OP]

	ldr r1,	W_DP_MFD_\freq
	str r1, [r0, #PLL_DP_MFD]
	str r1, [r0, #PLL_DP_HFS_MFD]

	ldr r1,  W_DP_MFN_\freq
	str r1, [r0, #PLL_DP_MFN]
	str r1, [r0, #PLL_DP_HFS_MFN]

	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL]
1:	ldr r1, [r0, #PLL_DP_CTL]
	ands r1, r1, #0x1
	beq 1b
.endm

.macro setup_pll_errata pll, freq
	ldr r2, =\pll
	mov r1, #0x0
	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	ldr r1, =0x00001236
	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
	ands r1, r1, #0x1
	beq 1b

	ldr r5, \freq
	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
	str r5, [r2, #PLL_DP_HFS_MFN]

	mov r1, #0x1
	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */

2:	ldr r1, [r2, #PLL_DP_CONFIG]
	tst r1, #1
	bne 2b

	ldr r1, =100		     /* Wait at least 4 us */
3:	subs r1, r1, #1
	bge 3b

	mov r1, #0x2
	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm

.macro init_clock
	ldr r0, =CCM_BASE_ADDR

#if defined(CONFIG_MX51)
	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	ldr r1, =0x0
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]

	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x00000300
	str r1, [r0, #CLKCTL_CCGR6]

	/* Disable IPU and HSC dividers */
	mov r1, #0x60000
	str r1, [r0, #CLKCTL_CCDR]

	/* Make sure to switch the DDR away from PLL 1 */
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b
#else
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	ldr r1, =0x0
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR7]

	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x0F00030F
	str r1, [r0, #CLKCTL_CCGR6]
#endif

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51_PLL_ERRATA)
	setup_pll PLL1_BASE_ADDR, 864
	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
	setup_pll PLL1_BASE_ADDR, 800
#endif

#if defined(CONFIG_MX51)
	setup_pll PLL3_BASE_ADDR, 665

	/* Switch peripheral to PLL 3 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x000010C0
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	ldr r1, =0x13239145
	str r1, [r0, #CLKCTL_CBCDR]
	setup_pll PLL2_BASE_ADDR, 665

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	ldr r1, =0x000020C0
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
#endif
	setup_pll PLL3_BASE_ADDR, 216

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000725
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR

#if defined(CONFIG_MX51)
	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	ldr r1, =0x0
	ldr r3, [r1, #ROM_SI_REV]
	cmp r3, #0x10
	movls r1, #0x1
	movhi r1, #0
#else
	mov r1, #0

#endif
	str r1, [r0, #CLKCTL_CACRR]
	/* Switch ARM back to PLL 1 */
	mov r1, #0
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51)
	/* setup the rest */
	/* Use lp_apm (24MHz) source for perclk */
	ldr r1, =0x000020C2
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
	str r1, [r0, #CLKCTL_CBCDR]
#endif

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]
#if defined(CONFIG_MX53)
	str r1, [r0, #CLKCTL_CCGR7]
#endif

#if defined(CONFIG_MX51)
	/* Use PLL 2 for UART's, get 66.5MHz from it */
	ldr r1, =0xA5A2A020
	str r1, [r0, #CLKCTL_CSCMR1]
	ldr r1, =0x00C30321
	str r1, [r0, #CLKCTL_CSCDR1]
#elif defined(CONFIG_MX53)
	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x00808145
	orr r1, r1, #(2 << 10)
	orr r1, r1, #(0 << 16)
	orr r1, r1, #(1 << 19)
	str r1, [r0, #CLKCTL_CBCDR]

	ldr r1, =0x00016154
	str r1, [r0, #CLKCTL_CBCMR]
	/* Change uart clk parent to pll2*/
	ldr r1, [r0, #CLKCTL_CSCMR1]
	and r1, r1, #0xfcffffff
	orr r1, r1, #0x01000000
	str r1, [r0, #CLKCTL_CSCMR1]
	ldr r1, [r0, #CLKCTL_CSCDR1]
	and r1, r1, #0xffffffc0
	orr r1, r1, #0x0a
	str r1, [r0, #CLKCTL_CSCDR1]
#endif
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	mov r1, #0x0
	str r1, [r0, #CLKCTL_CCDR]

	/* for cko - for ARM div by 8 */
	mov r1, #0x000A0000
	add r1, r1, #0x00000F0
	str r1, [r0, #CLKCTL_CCOSR]
.endm

.macro setup_wdog
	ldr r0, =WDOG1_BASE_ADDR
	mov r1, #0x30
	strh r1, [r0]
.endm

.section ".text.init", "x"

ENTRY(lowlevel_init)
#if defined(CONFIG_MX51)
	ldr r0, =GPIO1_BASE_ADDR
	ldr r1, [r0, #0x0]
	orr r1, r1, #(1 << 23)
	str r1, [r0, #0x0]
	ldr r1, [r0, #0x4]
	orr r1, r1, #(1 << 23)
	str r1, [r0, #0x4]
#endif

	init_l2cc

	init_aips

	init_m4if

	init_clock

	/* r12 saved upper lr*/
	mov pc,lr
ENDPROC(lowlevel_init)

/* Board level setting value */
W_DP_OP_864:              .word DP_OP_864
W_DP_MFD_864:             .word DP_MFD_864
W_DP_MFN_864:             .word DP_MFN_864
W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
W_DP_OP_800:              .word DP_OP_800
W_DP_MFD_800:             .word DP_MFD_800
W_DP_MFN_800:             .word DP_MFN_800
W_DP_OP_665:              .word DP_OP_665
W_DP_MFD_665:             .word DP_MFD_665
W_DP_MFN_665:             .word DP_MFN_665
W_DP_OP_216:              .word DP_OP_216
W_DP_MFD_216:             .word DP_MFD_216
W_DP_MFN_216:             .word DP_MFN_216
Commit	Line	Data
64fdf452 SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <config.h>
	23	#include <asm/arch/imx-regs.h>
a4814a69	24	#include <generated/asm-offsets.h>
74236aca	25	#include <linux/linkage.h>
64fdf452 SB	26
	27	/*
	28	* L2CC Cache setup/invalidation/disable
	29	*/
	30	.macro init_l2cc
	31	/* explicitly disable L2 cache */
	32	mrc 15, 0, r0, c1, c0, 1
	33	bic r0, r0, #0x2
	34	mcr 15, 0, r0, c1, c0, 1
	35
	36	/* reconfigure L2 cache aux control reg */
93910edb WD	37	mov r0, #0xC0 /* tag RAM */
	38	add r0, r0, #0x4 /* data RAM */
	39	orr r0, r0, #(1 << 24) /* disable write allocate delay */
	40	orr r0, r0, #(1 << 23) /* disable write allocate combine */
	41	orr r0, r0, #(1 << 22) /* disable write allocate */
64fdf452	42
6e25b6ce DJ	43	#if defined(CONFIG_MX51)
	44	ldr r1, =0x0
	45	ldr r3, [r1, #ROM_SI_REV]
	46	cmp r3, #0x10
64fdf452 SB	47
	48	/* disable write combine for TO 2 and lower revs */
	49	orrls r0, r0, #(1 << 25)
6e25b6ce	50	#endif
64fdf452 SB	51
	52	mcr 15, 1, r0, c9, c0, 2
	53	.endm /* init_l2cc */
	54
	55	/* AIPS setup - Only setup MPROTx registers.
	56	* The PACR default values are good.*/
	57	.macro init_aips
	58	/*
	59	* Set all MPROTx to be non-bufferable, trusted for R/W,
	60	* not forced to user-mode.
	61	*/
	62	ldr r0, =AIPS1_BASE_ADDR
	63	ldr r1, =0x77777777
	64	str r1, [r0, #0x0]
	65	str r1, [r0, #0x4]
	66	ldr r0, =AIPS2_BASE_ADDR
	67	str r1, [r0, #0x0]
	68	str r1, [r0, #0x4]
	69	/*
	70	* Clear the on and off peripheral modules Supervisor Protect bit
	71	* for SDMA to access them. Did not change the AIPS control registers
	72	* (offset 0x20) access type
	73	*/
	74	.endm /* init_aips */
	75
	76	/* M4IF setup */
	77	.macro init_m4if
595f3e56	78	#ifdef CONFIG_MX51
64fdf452 SB	79	/* VPU and IPU given higher priority (0x4)
	80	* IPU accesses with ID=0x1 given highest priority (=0xA)
	81	*/
	82	ldr r0, =M4IF_BASE_ADDR
	83
	84	ldr r1, =0x00000203
	85	str r1, [r0, #0x40]
	86
	87	ldr r1, =0x0
	88	str r1, [r0, #0x44]
	89
	90	ldr r1, =0x00120125
	91	str r1, [r0, #0x9C]
	92
	93	ldr r1, =0x001901A3
	94	str r1, [r0, #0x48]
	95
595f3e56	96	#endif
64fdf452 SB	97	.endm /* init_m4if */
	98
	99	.macro setup_pll pll, freq
595f3e56	100	ldr r0, =\pll
64fdf452	101	ldr r1, =0x00001232
595f3e56	102	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
64fdf452	103	mov r1, #0x2
595f3e56	104	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
64fdf452	105
595f3e56 LHR	106	ldr r1, W_DP_OP_\freq
	107	str r1, [r0, #PLL_DP_OP]
	108	str r1, [r0, #PLL_DP_HFS_OP]
64fdf452	109
595f3e56 LHR	110	ldr r1, W_DP_MFD_\freq
	111	str r1, [r0, #PLL_DP_MFD]
	112	str r1, [r0, #PLL_DP_HFS_MFD]
64fdf452	113
595f3e56 LHR	114	ldr r1, W_DP_MFN_\freq
	115	str r1, [r0, #PLL_DP_MFN]
	116	str r1, [r0, #PLL_DP_HFS_MFN]
64fdf452 SB	117
64fdf452 SB	118	ldr r1, =0x00001232
595f3e56 LHR	119	str r1, [r0, #PLL_DP_CTL]
595f3e56 LHR	120	1: ldr r1, [r0, #PLL_DP_CTL]
64fdf452 SB	121	ands r1, r1, #0x1
	122	beq 1b
	123	.endm
	124
9db1bfa1 DJ	125	.macro setup_pll_errata pll, freq
	126	ldr r2, =\pll
	127	mov r1, #0x0
	128	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	129	ldr r1, =0x00001236
	130	str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
	131	1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
	132	ands r1, r1, #0x1
	133	beq 1b
	134
	135	ldr r5, \freq
	136	str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
	137	str r5, [r2, #PLL_DP_HFS_MFN]
	138
	139	mov r1, #0x1
	140	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
	141
	142	2: ldr r1, [r2, #PLL_DP_CONFIG]
	143	tst r1, #1
	144	bne 2b
	145
	146	ldr r1, =100 /* Wait at least 4 us */
	147	3: subs r1, r1, #1
	148	bge 3b
	149
	150	mov r1, #0x2
	151	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
	152	.endm
	153
64fdf452 SB	154	.macro init_clock
	155	ldr r0, =CCM_BASE_ADDR
	156
595f3e56	157	#if defined(CONFIG_MX51)
64fdf452 SB	158	/* Gate of clocks to the peripherals first */
	159	ldr r1, =0x3FFFFFFF
	160	str r1, [r0, #CLKCTL_CCGR0]
	161	ldr r1, =0x0
	162	str r1, [r0, #CLKCTL_CCGR1]
	163	str r1, [r0, #CLKCTL_CCGR2]
	164	str r1, [r0, #CLKCTL_CCGR3]
	165
	166	ldr r1, =0x00030000
	167	str r1, [r0, #CLKCTL_CCGR4]
	168	ldr r1, =0x00FFF030
	169	str r1, [r0, #CLKCTL_CCGR5]
	170	ldr r1, =0x00000300
	171	str r1, [r0, #CLKCTL_CCGR6]
	172
	173	/* Disable IPU and HSC dividers */
	174	mov r1, #0x60000
	175	str r1, [r0, #CLKCTL_CCDR]
	176
	177	/* Make sure to switch the DDR away from PLL 1 */
	178	ldr r1, =0x19239145
	179	str r1, [r0, #CLKCTL_CBCDR]
	180	/* make sure divider effective */
	181	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	182	cmp r1, #0x0
	183	bne 1b
41c881c0 FE	184	#else
	185	ldr r1, =0x3FFFFFFF
	186	str r1, [r0, #CLKCTL_CCGR0]
	187	ldr r1, =0x0
	188	str r1, [r0, #CLKCTL_CCGR1]
	189	str r1, [r0, #CLKCTL_CCGR2]
	190	str r1, [r0, #CLKCTL_CCGR3]
	191	str r1, [r0, #CLKCTL_CCGR7]
	192
	193	ldr r1, =0x00030000
	194	str r1, [r0, #CLKCTL_CCGR4]
	195	ldr r1, =0x00FFF030
	196	str r1, [r0, #CLKCTL_CCGR5]
	197	ldr r1, =0x0F00030F
	198	str r1, [r0, #CLKCTL_CCGR6]
595f3e56	199	#endif
64fdf452 SB	200
	201	/* Switch ARM to step clock */
	202	mov r1, #0x4
	203	str r1, [r0, #CLKCTL_CCSR]
64fdf452	204
9db1bfa1 DJ	205	#if defined(CONFIG_MX51_PLL_ERRATA)
	206	setup_pll PLL1_BASE_ADDR, 864
	207	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
	208	#else
595f3e56	209	setup_pll PLL1_BASE_ADDR, 800
9db1bfa1	210	#endif
595f3e56 LHR	211
	212	#if defined(CONFIG_MX51)
	213	setup_pll PLL3_BASE_ADDR, 665
64fdf452 SB	214
	215	/* Switch peripheral to PLL 3 */
	216	ldr r0, =CCM_BASE_ADDR
93910edb	217	ldr r1, =0x000010C0
5e1fe88f	218	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	219	str r1, [r0, #CLKCTL_CBCMR]
	220	ldr r1, =0x13239145
	221	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	222	setup_pll PLL2_BASE_ADDR, 665
64fdf452 SB	223
	224	/* Switch peripheral to PLL2 */
	225	ldr r0, =CCM_BASE_ADDR
	226	ldr r1, =0x19239145
	227	str r1, [r0, #CLKCTL_CBCDR]
	228	ldr r1, =0x000020C0
5e1fe88f	229	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452	230	str r1, [r0, #CLKCTL_CBCMR]
595f3e56 LHR	231	#endif
595f3e56 LHR	232	setup_pll PLL3_BASE_ADDR, 216
64fdf452 SB	233
	234	/* Set the platform clock dividers */
	235	ldr r0, =ARM_BASE_ADDR
	236	ldr r1, =0x00000725
	237	str r1, [r0, #0x14]
	238
	239	ldr r0, =CCM_BASE_ADDR
	240
595f3e56	241	#if defined(CONFIG_MX51)
64fdf452 SB	242	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	243	ldr r1, =0x0
	244	ldr r3, [r1, #ROM_SI_REV]
	245	cmp r3, #0x10
	246	movls r1, #0x1
	247	movhi r1, #0
595f3e56 LHR	248	#else
595f3e56 LHR	249	mov r1, #0
64fdf452	250
595f3e56 LHR	251	#endif
595f3e56 LHR	252	str r1, [r0, #CLKCTL_CACRR]
64fdf452 SB	253	/* Switch ARM back to PLL 1 */
	254	mov r1, #0
	255	str r1, [r0, #CLKCTL_CCSR]
	256
595f3e56	257	#if defined(CONFIG_MX51)
64fdf452 SB	258	/* setup the rest */
	259	/* Use lp_apm (24MHz) source for perclk */
	260	ldr r1, =0x000020C2
5e1fe88f	261	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	262	str r1, [r0, #CLKCTL_CBCMR]
64fdf452 SB	263	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
5e1fe88f	264	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
64fdf452	265	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	266	#endif
64fdf452 SB	267
	268	/* Restore the default values in the Gate registers */
	269	ldr r1, =0xFFFFFFFF
	270	str r1, [r0, #CLKCTL_CCGR0]
	271	str r1, [r0, #CLKCTL_CCGR1]
	272	str r1, [r0, #CLKCTL_CCGR2]
	273	str r1, [r0, #CLKCTL_CCGR3]
	274	str r1, [r0, #CLKCTL_CCGR4]
	275	str r1, [r0, #CLKCTL_CCGR5]
	276	str r1, [r0, #CLKCTL_CCGR6]
595f3e56 LHR	277	#if defined(CONFIG_MX53)
	278	str r1, [r0, #CLKCTL_CCGR7]
	279	#endif
64fdf452	280
595f3e56	281	#if defined(CONFIG_MX51)
64fdf452 SB	282	/* Use PLL 2 for UART's, get 66.5MHz from it */
	283	ldr r1, =0xA5A2A020
	284	str r1, [r0, #CLKCTL_CSCMR1]
	285	ldr r1, =0x00C30321
	286	str r1, [r0, #CLKCTL_CSCDR1]
595f3e56	287	#elif defined(CONFIG_MX53)
67ee3dd3 FE	288	/* Switch peripheral to PLL2 */
	289	ldr r0, =CCM_BASE_ADDR
	290	ldr r1, =0x00808145
	291	orr r1, r1, #(2 << 10)
	292	orr r1, r1, #(0 << 16)
	293	orr r1, r1, #(1 << 19)
	294	str r1, [r0, #CLKCTL_CBCDR]
	295
	296	ldr r1, =0x00016154
	297	str r1, [r0, #CLKCTL_CBCMR]
	298	/* Change uart clk parent to pll2*/
	299	ldr r1, [r0, #CLKCTL_CSCMR1]
	300	and r1, r1, #0xfcffffff
	301	orr r1, r1, #0x01000000
	302	str r1, [r0, #CLKCTL_CSCMR1]
595f3e56	303	ldr r1, [r0, #CLKCTL_CSCDR1]
67ee3dd3 FE	304	and r1, r1, #0xffffffc0
67ee3dd3 FE	305	orr r1, r1, #0x0a
595f3e56 LHR	306	str r1, [r0, #CLKCTL_CSCDR1]
595f3e56 LHR	307	#endif
64fdf452 SB	308	/* make sure divider effective */
	309	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	310	cmp r1, #0x0
	311	bne 1b
	312
	313	mov r1, #0x0
	314	str r1, [r0, #CLKCTL_CCDR]
	315
	316	/* for cko - for ARM div by 8 */
	317	mov r1, #0x000A0000
	318	add r1, r1, #0x00000F0
	319	str r1, [r0, #CLKCTL_CCOSR]
	320	.endm
	321
	322	.macro setup_wdog
	323	ldr r0, =WDOG1_BASE_ADDR
	324	mov r1, #0x30
	325	strh r1, [r0]
	326	.endm
	327
	328	.section ".text.init", "x"
	329
74236aca	330	ENTRY(lowlevel_init)
595f3e56	331	#if defined(CONFIG_MX51)
64fdf452 SB	332	ldr r0, =GPIO1_BASE_ADDR
	333	ldr r1, [r0, #0x0]
	334	orr r1, r1, #(1 << 23)
	335	str r1, [r0, #0x0]
	336	ldr r1, [r0, #0x4]
	337	orr r1, r1, #(1 << 23)
	338	str r1, [r0, #0x4]
595f3e56	339	#endif
64fdf452	340
64fdf452 SB	341	init_l2cc
	342
	343	init_aips
	344
	345	init_m4if
	346
	347	init_clock
	348
64fdf452 SB	349	/* r12 saved upper lr*/
64fdf452 SB	350	mov pc,lr
74236aca	351	ENDPROC(lowlevel_init)
64fdf452 SB	352
64fdf452 SB	353	/* Board level setting value */
9db1bfa1 DJ	354	W_DP_OP_864: .word DP_OP_864
	355	W_DP_MFD_864: .word DP_MFD_864
	356	W_DP_MFN_864: .word DP_MFN_864
	357	W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
595f3e56 LHR	358	W_DP_OP_800: .word DP_OP_800
	359	W_DP_MFD_800: .word DP_MFD_800
	360	W_DP_MFN_800: .word DP_MFN_800
	361	W_DP_OP_665: .word DP_OP_665
	362	W_DP_MFD_665: .word DP_MFD_665
	363	W_DP_MFN_665: .word DP_MFN_665
	364	W_DP_OP_216: .word DP_OP_216
	365	W_DP_MFD_216: .word DP_MFD_216
	366	W_DP_MFN_216: .word DP_MFN_216