[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/asm-offsets.h>

/*
 * L2CC Cache setup/invalidation/disable
 */
.macro init_l2cc
	/* explicitly disable L2 cache */
	mrc 15, 0, r0, c1, c0, 1
	bic r0, r0, #0x2
	mcr 15, 0, r0, c1, c0, 1

	/* reconfigure L2 cache aux control reg */
	mov r0, #0xC0			/* tag RAM */
	add r0, r0, #0x4		/* data RAM */
	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
	orr r0, r0, #(1 << 22)		/* disable write allocate */

#if defined(CONFIG_MX51)
	ldr r1, =0x0
	ldr r3, [r1, #ROM_SI_REV]
	cmp r3, #0x10

	/* disable write combine for TO 2 and lower revs */
	orrls r0, r0, #(1 << 25)
#endif

	mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */

/* AIPS setup - Only setup MPROTx registers.
 * The PACR default values are good.*/
.macro init_aips
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	ldr r0, =AIPS1_BASE_ADDR
	ldr r1, =0x77777777
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	ldr r0, =AIPS2_BASE_ADDR
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	/*
	 * Clear the on and off peripheral modules Supervisor Protect bit
	 * for SDMA to access them. Did not change the AIPS control registers
	 * (offset 0x20) access type
	 */
.endm /* init_aips */

/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
	/* VPU and IPU given higher priority (0x4)
	 * IPU accesses with ID=0x1 given highest priority (=0xA)
	 */
	ldr r0, =M4IF_BASE_ADDR

	ldr r1, =0x00000203
	str r1, [r0, #0x40]

	ldr r1, =0x0
	str r1, [r0, #0x44]

	ldr r1, =0x00120125
	str r1, [r0, #0x9C]

	ldr r1, =0x001901A3
	str r1, [r0, #0x48]

#endif
.endm /* init_m4if */

.macro setup_pll pll, freq
	ldr r0, =\pll
	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
	mov r1, #0x2
	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */

	ldr r1, W_DP_OP_\freq
	str r1, [r0, #PLL_DP_OP]
	str r1, [r0, #PLL_DP_HFS_OP]

	ldr r1,	W_DP_MFD_\freq
	str r1, [r0, #PLL_DP_MFD]
	str r1, [r0, #PLL_DP_HFS_MFD]

	ldr r1,  W_DP_MFN_\freq
	str r1, [r0, #PLL_DP_MFN]
	str r1, [r0, #PLL_DP_HFS_MFN]

	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL]
1:	ldr r1, [r0, #PLL_DP_CTL]
	ands r1, r1, #0x1
	beq 1b
.endm

.macro setup_pll_errata pll, freq
	ldr r2, =\pll
	mov r1, #0x0
	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	ldr r1, =0x00001236
	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
	ands r1, r1, #0x1
	beq 1b

	ldr r5, \freq
	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
	str r5, [r2, #PLL_DP_HFS_MFN]

	mov r1, #0x1
	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */

2:	ldr r1, [r2, #PLL_DP_CONFIG]
	tst r1, #1
	bne 2b

	ldr r1, =100		     /* Wait at least 4 us */
3:	subs r1, r1, #1
	bge 3b

	mov r1, #0x2
	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm

.macro init_clock
	ldr r0, =CCM_BASE_ADDR

#if defined(CONFIG_MX51)
	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	ldr r1, =0x0
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]

	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x00000300
	str r1, [r0, #CLKCTL_CCGR6]

	/* Disable IPU and HSC dividers */
	mov r1, #0x60000
	str r1, [r0, #CLKCTL_CCDR]

	/* Make sure to switch the DDR away from PLL 1 */
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b
#endif

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51_PLL_ERRATA)
	setup_pll PLL1_BASE_ADDR, 864
	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
	setup_pll PLL1_BASE_ADDR, 800
#endif

#if defined(CONFIG_MX51)
	setup_pll PLL3_BASE_ADDR, 665

	/* Switch peripheral to PLL 3 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x000010C0
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	ldr r1, =0x13239145
	str r1, [r0, #CLKCTL_CBCDR]
	setup_pll PLL2_BASE_ADDR, 665

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	ldr r1, =0x000020C0
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
#endif
	setup_pll PLL3_BASE_ADDR, 216

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000725
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR

#if defined(CONFIG_MX51)
	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	ldr r1, =0x0
	ldr r3, [r1, #ROM_SI_REV]
	cmp r3, #0x10
	movls r1, #0x1
	movhi r1, #0
#else
	mov r1, #0

#endif
	str r1, [r0, #CLKCTL_CACRR]
	/* Switch ARM back to PLL 1 */
	mov r1, #0
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51)
	/* setup the rest */
	/* Use lp_apm (24MHz) source for perclk */
	ldr r1, =0x000020C2
	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
	str r1, [r0, #CLKCTL_CBCDR]
#endif

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]
#if defined(CONFIG_MX53)
	str r1, [r0, #CLKCTL_CCGR7]
#endif

#if defined(CONFIG_MX51)
	/* Use PLL 2 for UART's, get 66.5MHz from it */
	ldr r1, =0xA5A2A020
	str r1, [r0, #CLKCTL_CSCMR1]
	ldr r1, =0x00C30321
	str r1, [r0, #CLKCTL_CSCDR1]
#elif defined(CONFIG_MX53)
	ldr r1, [r0, #CLKCTL_CSCDR1]
	orr r1, r1, #0x3f
	eor r1, r1, #0x3f
	orr r1, r1, #0x21
	str r1, [r0, #CLKCTL_CSCDR1]
#endif
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	mov r1, #0x0
	str r1, [r0, #CLKCTL_CCDR]

	/* for cko - for ARM div by 8 */
	mov r1, #0x000A0000
	add r1, r1, #0x00000F0
	str r1, [r0, #CLKCTL_CCOSR]
.endm

.macro setup_wdog
	ldr r0, =WDOG1_BASE_ADDR
	mov r1, #0x30
	strh r1, [r0]
.endm

.section ".text.init", "x"

.globl lowlevel_init
lowlevel_init:
#if defined(CONFIG_MX51)
	ldr r0, =GPIO1_BASE_ADDR
	ldr r1, [r0, #0x0]
	orr r1, r1, #(1 << 23)
	str r1, [r0, #0x0]
	ldr r1, [r0, #0x4]
	orr r1, r1, #(1 << 23)
	str r1, [r0, #0x4]
#endif

	init_l2cc

	init_aips

	init_m4if

	init_clock

	/* r12 saved upper lr*/
	mov pc,lr

/* Board level setting value */
W_DP_OP_864:              .word DP_OP_864
W_DP_MFD_864:             .word DP_MFD_864
W_DP_MFN_864:             .word DP_MFN_864
W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
W_DP_OP_800:              .word DP_OP_800
W_DP_MFD_800:             .word DP_MFD_800
W_DP_MFN_800:             .word DP_MFN_800
W_DP_OP_665:              .word DP_OP_665
W_DP_MFD_665:             .word DP_MFD_665
W_DP_MFN_665:             .word DP_MFN_665
W_DP_OP_216:              .word DP_OP_216
W_DP_MFD_216:             .word DP_MFD_216
W_DP_MFN_216:             .word DP_MFN_216
Commit	Line	Data
64fdf452 SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <config.h>
	23	#include <asm/arch/imx-regs.h>
	24	#include <asm/arch/asm-offsets.h>
	25
	26	/*
	27	* L2CC Cache setup/invalidation/disable
	28	*/
	29	.macro init_l2cc
	30	/* explicitly disable L2 cache */
	31	mrc 15, 0, r0, c1, c0, 1
	32	bic r0, r0, #0x2
	33	mcr 15, 0, r0, c1, c0, 1
	34
	35	/* reconfigure L2 cache aux control reg */
93910edb WD	36	mov r0, #0xC0 /* tag RAM */
	37	add r0, r0, #0x4 /* data RAM */
	38	orr r0, r0, #(1 << 24) /* disable write allocate delay */
	39	orr r0, r0, #(1 << 23) /* disable write allocate combine */
	40	orr r0, r0, #(1 << 22) /* disable write allocate */
64fdf452	41
6e25b6ce DJ	42	#if defined(CONFIG_MX51)
	43	ldr r1, =0x0
	44	ldr r3, [r1, #ROM_SI_REV]
	45	cmp r3, #0x10
64fdf452 SB	46
	47	/* disable write combine for TO 2 and lower revs */
	48	orrls r0, r0, #(1 << 25)
6e25b6ce	49	#endif
64fdf452 SB	50
	51	mcr 15, 1, r0, c9, c0, 2
	52	.endm /* init_l2cc */
	53
	54	/* AIPS setup - Only setup MPROTx registers.
	55	* The PACR default values are good.*/
	56	.macro init_aips
	57	/*
	58	* Set all MPROTx to be non-bufferable, trusted for R/W,
	59	* not forced to user-mode.
	60	*/
	61	ldr r0, =AIPS1_BASE_ADDR
	62	ldr r1, =0x77777777
	63	str r1, [r0, #0x0]
	64	str r1, [r0, #0x4]
	65	ldr r0, =AIPS2_BASE_ADDR
	66	str r1, [r0, #0x0]
	67	str r1, [r0, #0x4]
	68	/*
	69	* Clear the on and off peripheral modules Supervisor Protect bit
	70	* for SDMA to access them. Did not change the AIPS control registers
	71	* (offset 0x20) access type
	72	*/
	73	.endm /* init_aips */
	74
	75	/* M4IF setup */
	76	.macro init_m4if
595f3e56	77	#ifdef CONFIG_MX51
64fdf452 SB	78	/* VPU and IPU given higher priority (0x4)
	79	* IPU accesses with ID=0x1 given highest priority (=0xA)
	80	*/
	81	ldr r0, =M4IF_BASE_ADDR
	82
	83	ldr r1, =0x00000203
	84	str r1, [r0, #0x40]
	85
	86	ldr r1, =0x0
	87	str r1, [r0, #0x44]
	88
	89	ldr r1, =0x00120125
	90	str r1, [r0, #0x9C]
	91
	92	ldr r1, =0x001901A3
	93	str r1, [r0, #0x48]
	94
595f3e56	95	#endif
64fdf452 SB	96	.endm /* init_m4if */
	97
	98	.macro setup_pll pll, freq
595f3e56	99	ldr r0, =\pll
64fdf452	100	ldr r1, =0x00001232
595f3e56	101	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
64fdf452	102	mov r1, #0x2
595f3e56	103	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
64fdf452	104
595f3e56 LHR	105	ldr r1, W_DP_OP_\freq
	106	str r1, [r0, #PLL_DP_OP]
	107	str r1, [r0, #PLL_DP_HFS_OP]
64fdf452	108
595f3e56 LHR	109	ldr r1, W_DP_MFD_\freq
	110	str r1, [r0, #PLL_DP_MFD]
	111	str r1, [r0, #PLL_DP_HFS_MFD]
64fdf452	112
595f3e56 LHR	113	ldr r1, W_DP_MFN_\freq
	114	str r1, [r0, #PLL_DP_MFN]
	115	str r1, [r0, #PLL_DP_HFS_MFN]
64fdf452 SB	116
64fdf452 SB	117	ldr r1, =0x00001232
595f3e56 LHR	118	str r1, [r0, #PLL_DP_CTL]
595f3e56 LHR	119	1: ldr r1, [r0, #PLL_DP_CTL]
64fdf452 SB	120	ands r1, r1, #0x1
	121	beq 1b
	122	.endm
	123
9db1bfa1 DJ	124	.macro setup_pll_errata pll, freq
	125	ldr r2, =\pll
	126	mov r1, #0x0
	127	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	128	ldr r1, =0x00001236
	129	str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
	130	1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
	131	ands r1, r1, #0x1
	132	beq 1b
	133
	134	ldr r5, \freq
	135	str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
	136	str r5, [r2, #PLL_DP_HFS_MFN]
	137
	138	mov r1, #0x1
	139	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
	140
	141	2: ldr r1, [r2, #PLL_DP_CONFIG]
	142	tst r1, #1
	143	bne 2b
	144
	145	ldr r1, =100 /* Wait at least 4 us */
	146	3: subs r1, r1, #1
	147	bge 3b
	148
	149	mov r1, #0x2
	150	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
	151	.endm
	152
64fdf452 SB	153	.macro init_clock
	154	ldr r0, =CCM_BASE_ADDR
	155
595f3e56	156	#if defined(CONFIG_MX51)
64fdf452 SB	157	/* Gate of clocks to the peripherals first */
	158	ldr r1, =0x3FFFFFFF
	159	str r1, [r0, #CLKCTL_CCGR0]
	160	ldr r1, =0x0
	161	str r1, [r0, #CLKCTL_CCGR1]
	162	str r1, [r0, #CLKCTL_CCGR2]
	163	str r1, [r0, #CLKCTL_CCGR3]
	164
	165	ldr r1, =0x00030000
	166	str r1, [r0, #CLKCTL_CCGR4]
	167	ldr r1, =0x00FFF030
	168	str r1, [r0, #CLKCTL_CCGR5]
	169	ldr r1, =0x00000300
	170	str r1, [r0, #CLKCTL_CCGR6]
	171
	172	/* Disable IPU and HSC dividers */
	173	mov r1, #0x60000
	174	str r1, [r0, #CLKCTL_CCDR]
	175
	176	/* Make sure to switch the DDR away from PLL 1 */
	177	ldr r1, =0x19239145
	178	str r1, [r0, #CLKCTL_CBCDR]
	179	/* make sure divider effective */
	180	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	181	cmp r1, #0x0
	182	bne 1b
595f3e56	183	#endif
64fdf452 SB	184
	185	/* Switch ARM to step clock */
	186	mov r1, #0x4
	187	str r1, [r0, #CLKCTL_CCSR]
64fdf452	188
9db1bfa1 DJ	189	#if defined(CONFIG_MX51_PLL_ERRATA)
	190	setup_pll PLL1_BASE_ADDR, 864
	191	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
	192	#else
595f3e56	193	setup_pll PLL1_BASE_ADDR, 800
9db1bfa1	194	#endif
595f3e56 LHR	195
	196	#if defined(CONFIG_MX51)
	197	setup_pll PLL3_BASE_ADDR, 665
64fdf452 SB	198
	199	/* Switch peripheral to PLL 3 */
	200	ldr r0, =CCM_BASE_ADDR
93910edb	201	ldr r1, =0x000010C0
5e1fe88f	202	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	203	str r1, [r0, #CLKCTL_CBCMR]
	204	ldr r1, =0x13239145
	205	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	206	setup_pll PLL2_BASE_ADDR, 665
64fdf452 SB	207
	208	/* Switch peripheral to PLL2 */
	209	ldr r0, =CCM_BASE_ADDR
	210	ldr r1, =0x19239145
	211	str r1, [r0, #CLKCTL_CBCDR]
	212	ldr r1, =0x000020C0
5e1fe88f	213	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452	214	str r1, [r0, #CLKCTL_CBCMR]
595f3e56 LHR	215	#endif
595f3e56 LHR	216	setup_pll PLL3_BASE_ADDR, 216
64fdf452 SB	217
	218	/* Set the platform clock dividers */
	219	ldr r0, =ARM_BASE_ADDR
	220	ldr r1, =0x00000725
	221	str r1, [r0, #0x14]
	222
	223	ldr r0, =CCM_BASE_ADDR
	224
595f3e56	225	#if defined(CONFIG_MX51)
64fdf452 SB	226	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	227	ldr r1, =0x0
	228	ldr r3, [r1, #ROM_SI_REV]
	229	cmp r3, #0x10
	230	movls r1, #0x1
	231	movhi r1, #0
595f3e56 LHR	232	#else
595f3e56 LHR	233	mov r1, #0
64fdf452	234
595f3e56 LHR	235	#endif
595f3e56 LHR	236	str r1, [r0, #CLKCTL_CACRR]
64fdf452 SB	237	/* Switch ARM back to PLL 1 */
	238	mov r1, #0
	239	str r1, [r0, #CLKCTL_CCSR]
	240
595f3e56	241	#if defined(CONFIG_MX51)
64fdf452 SB	242	/* setup the rest */
	243	/* Use lp_apm (24MHz) source for perclk */
	244	ldr r1, =0x000020C2
5e1fe88f	245	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	246	str r1, [r0, #CLKCTL_CBCMR]
64fdf452 SB	247	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
5e1fe88f	248	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
64fdf452	249	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	250	#endif
64fdf452 SB	251
	252	/* Restore the default values in the Gate registers */
	253	ldr r1, =0xFFFFFFFF
	254	str r1, [r0, #CLKCTL_CCGR0]
	255	str r1, [r0, #CLKCTL_CCGR1]
	256	str r1, [r0, #CLKCTL_CCGR2]
	257	str r1, [r0, #CLKCTL_CCGR3]
	258	str r1, [r0, #CLKCTL_CCGR4]
	259	str r1, [r0, #CLKCTL_CCGR5]
	260	str r1, [r0, #CLKCTL_CCGR6]
595f3e56 LHR	261	#if defined(CONFIG_MX53)
	262	str r1, [r0, #CLKCTL_CCGR7]
	263	#endif
64fdf452	264
595f3e56	265	#if defined(CONFIG_MX51)
64fdf452 SB	266	/* Use PLL 2 for UART's, get 66.5MHz from it */
	267	ldr r1, =0xA5A2A020
	268	str r1, [r0, #CLKCTL_CSCMR1]
	269	ldr r1, =0x00C30321
	270	str r1, [r0, #CLKCTL_CSCDR1]
595f3e56 LHR	271	#elif defined(CONFIG_MX53)
	272	ldr r1, [r0, #CLKCTL_CSCDR1]
	273	orr r1, r1, #0x3f
	274	eor r1, r1, #0x3f
	275	orr r1, r1, #0x21
	276	str r1, [r0, #CLKCTL_CSCDR1]
	277	#endif
64fdf452 SB	278	/* make sure divider effective */
	279	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	280	cmp r1, #0x0
	281	bne 1b
	282
	283	mov r1, #0x0
	284	str r1, [r0, #CLKCTL_CCDR]
	285
	286	/* for cko - for ARM div by 8 */
	287	mov r1, #0x000A0000
	288	add r1, r1, #0x00000F0
	289	str r1, [r0, #CLKCTL_CCOSR]
	290	.endm
	291
	292	.macro setup_wdog
	293	ldr r0, =WDOG1_BASE_ADDR
	294	mov r1, #0x30
	295	strh r1, [r0]
	296	.endm
	297
	298	.section ".text.init", "x"
	299
	300	.globl lowlevel_init
	301	lowlevel_init:
595f3e56	302	#if defined(CONFIG_MX51)
64fdf452 SB	303	ldr r0, =GPIO1_BASE_ADDR
	304	ldr r1, [r0, #0x0]
	305	orr r1, r1, #(1 << 23)
	306	str r1, [r0, #0x0]
	307	ldr r1, [r0, #0x4]
	308	orr r1, r1, #(1 << 23)
	309	str r1, [r0, #0x4]
595f3e56	310	#endif
64fdf452	311
64fdf452 SB	312	init_l2cc
	313
	314	init_aips
	315
	316	init_m4if
	317
	318	init_clock
	319
64fdf452 SB	320	/* r12 saved upper lr*/
	321	mov pc,lr
	322
	323	/* Board level setting value */
9db1bfa1 DJ	324	W_DP_OP_864: .word DP_OP_864
	325	W_DP_MFD_864: .word DP_MFD_864
	326	W_DP_MFN_864: .word DP_MFN_864
	327	W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
595f3e56 LHR	328	W_DP_OP_800: .word DP_OP_800
	329	W_DP_MFD_800: .word DP_MFD_800
	330	W_DP_MFN_800: .word DP_MFN_800
	331	W_DP_OP_665: .word DP_OP_665
	332	W_DP_MFD_665: .word DP_MFD_665
	333	W_DP_MFN_665: .word DP_MFN_665
	334	W_DP_OP_216: .word DP_OP_216
	335	W_DP_MFD_216: .word DP_MFD_216
	336	W_DP_MFN_216: .word DP_MFN_216