[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx5 / lowlevel_init.S

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <linux/linkage.h>

.section ".text.init", "x"

.macro init_arm_erratum
	/* ARM erratum ID #468414 */
	mrc 15, 0, r1, c1, c0, 1
	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
	mcr 15, 0, r1, c1, c0, 1
.endm

/*
 * L2CC Cache setup/invalidation/disable
 */
.macro init_l2cc
	/* explicitly disable L2 cache */
	mrc 15, 0, r0, c1, c0, 1
	bic r0, r0, #0x2
	mcr 15, 0, r0, c1, c0, 1

	/* reconfigure L2 cache aux control reg */
	ldr r0, =0xC0 |			/* tag RAM */ \
	         0x4 |			/* data RAM */ \
	         1 << 24 |		/* disable write allocate delay */ \
	         1 << 23 |		/* disable write allocate combine */ \
	         1 << 22		/* disable write allocate */

#if defined(CONFIG_MX51)
	ldr r3, [r4, #ROM_SI_REV]
	cmp r3, #0x10

	/* disable write combine for TO 2 and lower revs */
	orrls r0, r0, #1 << 25
#endif

	mcr 15, 1, r0, c9, c0, 2
.endm /* init_l2cc */

/* AIPS setup - Only setup MPROTx registers.
 * The PACR default values are good.*/
.macro init_aips
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	ldr r0, =AIPS1_BASE_ADDR
	ldr r1, =0x77777777
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	ldr r0, =AIPS2_BASE_ADDR
	str r1, [r0, #0x0]
	str r1, [r0, #0x4]
	/*
	 * Clear the on and off peripheral modules Supervisor Protect bit
	 * for SDMA to access them. Did not change the AIPS control registers
	 * (offset 0x20) access type
	 */
.endm /* init_aips */

/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
	/* VPU and IPU given higher priority (0x4)
	 * IPU accesses with ID=0x1 given highest priority (=0xA)
	 */
	ldr r0, =M4IF_BASE_ADDR

	ldr r1, =0x00000203
	str r1, [r0, #0x40]

	str r4, [r0, #0x44]

	ldr r1, =0x00120125
	str r1, [r0, #0x9C]

	ldr r1, =0x001901A3
	str r1, [r0, #0x48]

#endif
.endm /* init_m4if */

.macro setup_pll pll, freq
	ldr r0, =\pll
	adr r2, W_DP_\freq
	bl setup_pll_func
.endm

#define W_DP_OP		0
#define W_DP_MFD	4
#define W_DP_MFN	8

setup_pll_func:
	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
	mov r1, #0x2
	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */

	ldr r1, [r2, #W_DP_OP]
	str r1, [r0, #PLL_DP_OP]
	str r1, [r0, #PLL_DP_HFS_OP]

	ldr r1, [r2, #W_DP_MFD]
	str r1, [r0, #PLL_DP_MFD]
	str r1, [r0, #PLL_DP_HFS_MFD]

	ldr r1, [r2, #W_DP_MFN]
	str r1, [r0, #PLL_DP_MFN]
	str r1, [r0, #PLL_DP_HFS_MFN]

	ldr r1, =0x00001232
	str r1, [r0, #PLL_DP_CTL]
1:	ldr r1, [r0, #PLL_DP_CTL]
	ands r1, r1, #0x1
	beq 1b

	/* r10 saved upper lr */
	mov pc, lr

.macro setup_pll_errata pll, freq
	ldr r2, =\pll
	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
	ldr r1, =0x00001236
	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */
	ands r1, r1, #0x1
	beq 1b

	ldr r5, \freq
	str r5, [r2, #PLL_DP_MFN]    /* Modify MFN value */
	str r5, [r2, #PLL_DP_HFS_MFN]

	mov r1, #0x1
	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */

2:	ldr r1, [r2, #PLL_DP_CONFIG]
	tst r1, #1
	bne 2b

	ldr r1, =100		     /* Wait at least 4 us */
3:	subs r1, r1, #1
	bge 3b

	mov r1, #0x2
	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm

.macro init_clock
#if defined (CONFIG_MX51)
	ldr r0, =CCM_BASE_ADDR

	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r4, [r0, #CLKCTL_CCGR1]
	str r4, [r0, #CLKCTL_CCGR2]
	str r4, [r0, #CLKCTL_CCGR3]

	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x00000300
	str r1, [r0, #CLKCTL_CCGR6]

	/* Disable IPU and HSC dividers */
	mov r1, #0x60000
	str r1, [r0, #CLKCTL_CCDR]

	/* Make sure to switch the DDR away from PLL 1 */
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

#if defined(CONFIG_MX51_PLL_ERRATA)
	setup_pll PLL1_BASE_ADDR, 864
	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
	setup_pll PLL1_BASE_ADDR, 800
#endif

	setup_pll PLL3_BASE_ADDR, 665

	/* Switch peripheral to PLL 3 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	ldr r1, =0x13239145
	str r1, [r0, #CLKCTL_CBCDR]
	setup_pll PLL2_BASE_ADDR, 665

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x19239145
	str r1, [r0, #CLKCTL_CBCDR]
	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]

	setup_pll PLL3_BASE_ADDR, 216

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000725
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR

	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
	ldr r3, [r4, #ROM_SI_REV]
	cmp r3, #0x10
	movls r1, #0x1
	movhi r1, #0

	str r1, [r0, #CLKCTL_CACRR]

	/* Switch ARM back to PLL 1 */
	str r4, [r0, #CLKCTL_CCSR]

	/* setup the rest */
	/* Use lp_apm (24MHz) source for perclk */
	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
	str r1, [r0, #CLKCTL_CBCMR]
	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
	str r1, [r0, #CLKCTL_CBCDR]

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]

	/* Use PLL 2 for UART's, get 66.5MHz from it */
	ldr r1, =0xA5A2A020
	str r1, [r0, #CLKCTL_CSCMR1]
	ldr r1, =0x00C30321
	str r1, [r0, #CLKCTL_CSCDR1]
	/* make sure divider effective */
1:	ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

	str r4, [r0, #CLKCTL_CCDR]

	/* for cko - for ARM div by 8 */
	mov r1, #0x000A0000
	add r1, r1, #0x00000F0
	str r1, [r0, #CLKCTL_CCOSR]
#else	/* CONFIG_MX53 */
	ldr r0, =CCM_BASE_ADDR

	/* Gate of clocks to the peripherals first */
	ldr r1, =0x3FFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r4, [r0, #CLKCTL_CCGR1]
	str r4, [r0, #CLKCTL_CCGR2]
	str r4, [r0, #CLKCTL_CCGR3]
	str r4, [r0, #CLKCTL_CCGR7]
	ldr r1, =0x00030000
	str r1, [r0, #CLKCTL_CCGR4]
	ldr r1, =0x00FFF030
	str r1, [r0, #CLKCTL_CCGR5]
	ldr r1, =0x0F00030F
	str r1, [r0, #CLKCTL_CCGR6]

	/* Switch ARM to step clock */
	mov r1, #0x4
	str r1, [r0, #CLKCTL_CCSR]

	setup_pll PLL1_BASE_ADDR, 800

        setup_pll PLL3_BASE_ADDR, 400

        /* Switch peripheral to PLL3 */
        ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00015154
        str r1, [r0, #CLKCTL_CBCMR]
        ldr r1, =0x02888945
        orr r1, r1, #(1 << 16)
        str r1, [r0, #CLKCTL_CBCDR]
        /* make sure change is effective */
1:      ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b

        setup_pll PLL2_BASE_ADDR, 400

	/* Switch peripheral to PLL2 */
	ldr r0, =CCM_BASE_ADDR
	ldr r1, =0x00808145
	orr r1, r1, #(2 << 10)
	orr r1, r1, #(0 << 16)
	orr r1, r1, #(1 << 19)
	str r1, [r0, #CLKCTL_CBCDR]

	ldr r1, =0x00016154
	str r1, [r0, #CLKCTL_CBCMR]

	/*change uart clk parent to pll2*/
	ldr r1, [r0, #CLKCTL_CSCMR1]
	and r1, r1, #0xfcffffff
	orr r1, r1, #0x01000000
	str r1, [r0, #CLKCTL_CSCMR1]

	/* make sure change is effective */
1:      ldr r1, [r0, #CLKCTL_CDHIPR]
	cmp r1, #0x0
	bne 1b

        setup_pll PLL3_BASE_ADDR, 216

	setup_pll PLL4_BASE_ADDR, 455

	/* Set the platform clock dividers */
	ldr r0, =ARM_BASE_ADDR
	ldr r1, =0x00000124
	str r1, [r0, #0x14]

	ldr r0, =CCM_BASE_ADDR
	mov r1, #0
	str r1, [r0, #CLKCTL_CACRR]

	/* Switch ARM back to PLL 1. */
	mov r1, #0x0
	str r1, [r0, #CLKCTL_CCSR]

	/* make uart div=6 */
	ldr r1, [r0, #CLKCTL_CSCDR1]
	and r1, r1, #0xffffffc0
	orr r1, r1, #0x0a
	str r1, [r0, #CLKCTL_CSCDR1]

	/* Restore the default values in the Gate registers */
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #CLKCTL_CCGR0]
	str r1, [r0, #CLKCTL_CCGR1]
	str r1, [r0, #CLKCTL_CCGR2]
	str r1, [r0, #CLKCTL_CCGR3]
	str r1, [r0, #CLKCTL_CCGR4]
	str r1, [r0, #CLKCTL_CCGR5]
	str r1, [r0, #CLKCTL_CCGR6]
	str r1, [r0, #CLKCTL_CCGR7]

        mov r1, #0x00000
        str r1, [r0, #CLKCTL_CCDR]

        /* for cko - for ARM div by 8 */
        mov r1, #0x000A0000
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]

#endif	/* CONFIG_MX53 */
.endm

.macro setup_wdog
	ldr r0, =WDOG1_BASE_ADDR
	mov r1, #0x30
	strh r1, [r0]
.endm

ENTRY(lowlevel_init)
	mov r10, lr
	mov r4, #0	/* Fix R4 to 0 */

#if defined(CONFIG_MX51)
	ldr r0, =GPIO1_BASE_ADDR
	ldr r1, [r0, #0x0]
	orr r1, r1, #1 << 23
	str r1, [r0, #0x0]
	ldr r1, [r0, #0x4]
	orr r1, r1, #1 << 23
	str r1, [r0, #0x4]
#endif

	init_arm_erratum

	init_l2cc

	init_aips

	init_m4if

	init_clock

	mov pc, r10
ENDPROC(lowlevel_init)

/* Board level setting value */
#if defined(CONFIG_MX51_PLL_ERRATA)
W_DP_864:		.word DP_OP_864
			.word DP_MFD_864
			.word DP_MFN_864
W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
#else
W_DP_800:		.word DP_OP_800
			.word DP_MFD_800
			.word DP_MFN_800
#endif
#if defined(CONFIG_MX51)
W_DP_665:		.word DP_OP_665
			.word DP_MFD_665
			.word DP_MFN_665
#endif
W_DP_216:		.word DP_OP_216
			.word DP_MFD_216
			.word DP_MFN_216
W_DP_400:               .word DP_OP_400
			.word DP_MFD_400
			.word DP_MFN_400
W_DP_455:               .word DP_OP_455
			.word DP_MFD_455
			.word DP_MFN_455
Commit	Line	Data
64fdf452 SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <config.h>
	23	#include <asm/arch/imx-regs.h>
a4814a69	24	#include <generated/asm-offsets.h>
74236aca	25	#include <linux/linkage.h>
64fdf452	26
dd227b6e BT	27	.section ".text.init", "x"
dd227b6e BT	28
c4fe17f6 FE	29	.macro init_arm_erratum
	30	/* ARM erratum ID #468414 */
	31	mrc 15, 0, r1, c1, c0, 1
	32	orr r1, r1, #(1 << 5) /* enable L1NEON bit */
	33	mcr 15, 0, r1, c1, c0, 1
	34	.endm
	35
64fdf452 SB	36	/*
	37	* L2CC Cache setup/invalidation/disable
	38	*/
	39	.macro init_l2cc
	40	/* explicitly disable L2 cache */
	41	mrc 15, 0, r0, c1, c0, 1
	42	bic r0, r0, #0x2
	43	mcr 15, 0, r0, c1, c0, 1
	44
	45	/* reconfigure L2 cache aux control reg */
dd227b6e BT	46	ldr r0, =0xC0 \| /* tag RAM */ \
	47	0x4 \| /* data RAM */ \
	48	1 << 24 \| /* disable write allocate delay */ \
	49	1 << 23 \| /* disable write allocate combine */ \
	50	1 << 22 /* disable write allocate */
64fdf452	51
6e25b6ce	52	#if defined(CONFIG_MX51)
dd227b6e	53	ldr r3, [r4, #ROM_SI_REV]
6e25b6ce	54	cmp r3, #0x10
64fdf452 SB	55
64fdf452 SB	56	/* disable write combine for TO 2 and lower revs */
18c63990	57	orrls r0, r0, #1 << 25
6e25b6ce	58	#endif
64fdf452 SB	59
	60	mcr 15, 1, r0, c9, c0, 2
	61	.endm /* init_l2cc */
	62
	63	/* AIPS setup - Only setup MPROTx registers.
	64	* The PACR default values are good.*/
	65	.macro init_aips
	66	/*
	67	* Set all MPROTx to be non-bufferable, trusted for R/W,
	68	* not forced to user-mode.
	69	*/
	70	ldr r0, =AIPS1_BASE_ADDR
	71	ldr r1, =0x77777777
	72	str r1, [r0, #0x0]
	73	str r1, [r0, #0x4]
	74	ldr r0, =AIPS2_BASE_ADDR
	75	str r1, [r0, #0x0]
	76	str r1, [r0, #0x4]
	77	/*
	78	* Clear the on and off peripheral modules Supervisor Protect bit
	79	* for SDMA to access them. Did not change the AIPS control registers
	80	* (offset 0x20) access type
	81	*/
	82	.endm /* init_aips */
	83
	84	/* M4IF setup */
	85	.macro init_m4if
595f3e56	86	#ifdef CONFIG_MX51
64fdf452 SB	87	/* VPU and IPU given higher priority (0x4)
	88	* IPU accesses with ID=0x1 given highest priority (=0xA)
	89	*/
	90	ldr r0, =M4IF_BASE_ADDR
	91
	92	ldr r1, =0x00000203
	93	str r1, [r0, #0x40]
	94
dd227b6e	95	str r4, [r0, #0x44]
64fdf452 SB	96
	97	ldr r1, =0x00120125
	98	str r1, [r0, #0x9C]
	99
	100	ldr r1, =0x001901A3
	101	str r1, [r0, #0x48]
	102
595f3e56	103	#endif
64fdf452 SB	104	.endm /* init_m4if */
	105
	106	.macro setup_pll pll, freq
595f3e56	107	ldr r0, =\pll
dd227b6e BT	108	adr r2, W_DP_\freq
	109	bl setup_pll_func
	110	.endm
	111
	112	#define W_DP_OP 0
	113	#define W_DP_MFD 4
	114	#define W_DP_MFN 8
	115
	116	setup_pll_func:
64fdf452	117	ldr r1, =0x00001232
595f3e56	118	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
64fdf452	119	mov r1, #0x2
595f3e56	120	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
64fdf452	121
dd227b6e	122	ldr r1, [r2, #W_DP_OP]
595f3e56 LHR	123	str r1, [r0, #PLL_DP_OP]
595f3e56 LHR	124	str r1, [r0, #PLL_DP_HFS_OP]
64fdf452	125
dd227b6e	126	ldr r1, [r2, #W_DP_MFD]
595f3e56 LHR	127	str r1, [r0, #PLL_DP_MFD]
595f3e56 LHR	128	str r1, [r0, #PLL_DP_HFS_MFD]
64fdf452	129
dd227b6e	130	ldr r1, [r2, #W_DP_MFN]
595f3e56 LHR	131	str r1, [r0, #PLL_DP_MFN]
595f3e56 LHR	132	str r1, [r0, #PLL_DP_HFS_MFN]
64fdf452 SB	133
64fdf452 SB	134	ldr r1, =0x00001232
595f3e56 LHR	135	str r1, [r0, #PLL_DP_CTL]
595f3e56 LHR	136	1: ldr r1, [r0, #PLL_DP_CTL]
64fdf452 SB	137	ands r1, r1, #0x1
64fdf452 SB	138	beq 1b
dd227b6e BT	139
	140	/* r10 saved upper lr */
	141	mov pc, lr
64fdf452	142
9db1bfa1 DJ	143	.macro setup_pll_errata pll, freq
9db1bfa1 DJ	144	ldr r2, =\pll
dd227b6e	145	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
9db1bfa1 DJ	146	ldr r1, =0x00001236
	147	str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
	148	1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
	149	ands r1, r1, #0x1
	150	beq 1b
	151
	152	ldr r5, \freq
	153	str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
	154	str r5, [r2, #PLL_DP_HFS_MFN]
	155
	156	mov r1, #0x1
	157	str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
	158
	159	2: ldr r1, [r2, #PLL_DP_CONFIG]
	160	tst r1, #1
	161	bne 2b
	162
	163	ldr r1, =100 /* Wait at least 4 us */
	164	3: subs r1, r1, #1
	165	bge 3b
	166
	167	mov r1, #0x2
	168	str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
	169	.endm
	170
64fdf452	171	.macro init_clock
758c3449	172	#if defined (CONFIG_MX51)
64fdf452 SB	173	ldr r0, =CCM_BASE_ADDR
	174
	175	/* Gate of clocks to the peripherals first */
	176	ldr r1, =0x3FFFFFFF
	177	str r1, [r0, #CLKCTL_CCGR0]
dd227b6e BT	178	str r4, [r0, #CLKCTL_CCGR1]
	179	str r4, [r0, #CLKCTL_CCGR2]
	180	str r4, [r0, #CLKCTL_CCGR3]
64fdf452 SB	181
	182	ldr r1, =0x00030000
	183	str r1, [r0, #CLKCTL_CCGR4]
	184	ldr r1, =0x00FFF030
	185	str r1, [r0, #CLKCTL_CCGR5]
	186	ldr r1, =0x00000300
	187	str r1, [r0, #CLKCTL_CCGR6]
	188
	189	/* Disable IPU and HSC dividers */
	190	mov r1, #0x60000
	191	str r1, [r0, #CLKCTL_CCDR]
	192
	193	/* Make sure to switch the DDR away from PLL 1 */
	194	ldr r1, =0x19239145
	195	str r1, [r0, #CLKCTL_CBCDR]
	196	/* make sure divider effective */
	197	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	198	cmp r1, #0x0
	199	bne 1b
	200
	201	/* Switch ARM to step clock */
	202	mov r1, #0x4
	203	str r1, [r0, #CLKCTL_CCSR]
64fdf452	204
9db1bfa1 DJ	205	#if defined(CONFIG_MX51_PLL_ERRATA)
	206	setup_pll PLL1_BASE_ADDR, 864
	207	setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
	208	#else
595f3e56	209	setup_pll PLL1_BASE_ADDR, 800
9db1bfa1	210	#endif
595f3e56	211
595f3e56	212	setup_pll PLL3_BASE_ADDR, 665
64fdf452 SB	213
	214	/* Switch peripheral to PLL 3 */
	215	ldr r0, =CCM_BASE_ADDR
dd227b6e	216	ldr r1, =0x000010C0 \| CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	217	str r1, [r0, #CLKCTL_CBCMR]
	218	ldr r1, =0x13239145
	219	str r1, [r0, #CLKCTL_CBCDR]
595f3e56	220	setup_pll PLL2_BASE_ADDR, 665
64fdf452 SB	221
	222	/* Switch peripheral to PLL2 */
	223	ldr r0, =CCM_BASE_ADDR
	224	ldr r1, =0x19239145
	225	str r1, [r0, #CLKCTL_CBCDR]
dd227b6e	226	ldr r1, =0x000020C0 \| CONFIG_SYS_DDR_CLKSEL
64fdf452	227	str r1, [r0, #CLKCTL_CBCMR]
758c3449	228
595f3e56	229	setup_pll PLL3_BASE_ADDR, 216
64fdf452 SB	230
	231	/* Set the platform clock dividers */
	232	ldr r0, =ARM_BASE_ADDR
	233	ldr r1, =0x00000725
	234	str r1, [r0, #0x14]
	235
	236	ldr r0, =CCM_BASE_ADDR
	237
	238	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
dd227b6e	239	ldr r3, [r4, #ROM_SI_REV]
64fdf452 SB	240	cmp r3, #0x10
	241	movls r1, #0x1
	242	movhi r1, #0
758c3449	243
595f3e56	244	str r1, [r0, #CLKCTL_CACRR]
18c63990	245
64fdf452	246	/* Switch ARM back to PLL 1 */
dd227b6e	247	str r4, [r0, #CLKCTL_CCSR]
64fdf452 SB	248
	249	/* setup the rest */
	250	/* Use lp_apm (24MHz) source for perclk */
dd227b6e	251	ldr r1, =0x000020C2 \| CONFIG_SYS_DDR_CLKSEL
64fdf452 SB	252	str r1, [r0, #CLKCTL_CBCMR]
64fdf452 SB	253	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
5e1fe88f	254	ldr r1, =CONFIG_SYS_CLKTL_CBCDR
64fdf452 SB	255	str r1, [r0, #CLKCTL_CBCDR]
	256
	257	/* Restore the default values in the Gate registers */
	258	ldr r1, =0xFFFFFFFF
	259	str r1, [r0, #CLKCTL_CCGR0]
	260	str r1, [r0, #CLKCTL_CCGR1]
	261	str r1, [r0, #CLKCTL_CCGR2]
	262	str r1, [r0, #CLKCTL_CCGR3]
	263	str r1, [r0, #CLKCTL_CCGR4]
	264	str r1, [r0, #CLKCTL_CCGR5]
	265	str r1, [r0, #CLKCTL_CCGR6]
	266
	267	/* Use PLL 2 for UART's, get 66.5MHz from it */
	268	ldr r1, =0xA5A2A020
	269	str r1, [r0, #CLKCTL_CSCMR1]
	270	ldr r1, =0x00C30321
	271	str r1, [r0, #CLKCTL_CSCDR1]
758c3449 FE	272	/* make sure divider effective */
	273	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	274	cmp r1, #0x0
	275	bne 1b
	276
	277	str r4, [r0, #CLKCTL_CCDR]
	278
	279	/* for cko - for ARM div by 8 */
	280	mov r1, #0x000A0000
	281	add r1, r1, #0x00000F0
	282	str r1, [r0, #CLKCTL_CCOSR]
	283	#else /* CONFIG_MX53 */
	284	ldr r0, =CCM_BASE_ADDR
	285
	286	/* Gate of clocks to the peripherals first */
	287	ldr r1, =0x3FFFFFFF
	288	str r1, [r0, #CLKCTL_CCGR0]
	289	str r4, [r0, #CLKCTL_CCGR1]
	290	str r4, [r0, #CLKCTL_CCGR2]
	291	str r4, [r0, #CLKCTL_CCGR3]
	292	str r4, [r0, #CLKCTL_CCGR7]
	293	ldr r1, =0x00030000
	294	str r1, [r0, #CLKCTL_CCGR4]
	295	ldr r1, =0x00FFF030
	296	str r1, [r0, #CLKCTL_CCGR5]
	297	ldr r1, =0x0F00030F
	298	str r1, [r0, #CLKCTL_CCGR6]
	299
	300	/* Switch ARM to step clock */
	301	mov r1, #0x4
	302	str r1, [r0, #CLKCTL_CCSR]
	303
	304	setup_pll PLL1_BASE_ADDR, 800
	305
782b0288 FE	306	setup_pll PLL3_BASE_ADDR, 400
	307
	308	/* Switch peripheral to PLL3 */
	309	ldr r0, =CCM_BASE_ADDR
	310	ldr r1, =0x00015154
	311	str r1, [r0, #CLKCTL_CBCMR]
	312	ldr r1, =0x02888945
	313	orr r1, r1, #(1 << 16)
	314	str r1, [r0, #CLKCTL_CBCDR]
	315	/* make sure change is effective */
	316	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	317	cmp r1, #0x0
	318	bne 1b
	319
	320	setup_pll PLL2_BASE_ADDR, 400
	321
	322	/* Switch peripheral to PLL2 */
	323	ldr r0, =CCM_BASE_ADDR
	324	ldr r1, =0x00808145
	325	orr r1, r1, #(2 << 10)
	326	orr r1, r1, #(0 << 16)
	327	orr r1, r1, #(1 << 19)
	328	str r1, [r0, #CLKCTL_CBCDR]
	329
	330	ldr r1, =0x00016154
	331	str r1, [r0, #CLKCTL_CBCMR]
	332
	333	/change uart clk parent to pll2/
	334	ldr r1, [r0, #CLKCTL_CSCMR1]
	335	and r1, r1, #0xfcffffff
	336	orr r1, r1, #0x01000000
	337	str r1, [r0, #CLKCTL_CSCMR1]
	338
	339	/* make sure change is effective */
	340	1: ldr r1, [r0, #CLKCTL_CDHIPR]
	341	cmp r1, #0x0
	342	bne 1b
	343
	344	setup_pll PLL3_BASE_ADDR, 216
	345
	346	setup_pll PLL4_BASE_ADDR, 455
758c3449 FE	347
	348	/* Set the platform clock dividers */
	349	ldr r0, =ARM_BASE_ADDR
782b0288	350	ldr r1, =0x00000124
758c3449 FE	351	str r1, [r0, #0x14]
	352
	353	ldr r0, =CCM_BASE_ADDR
758c3449 FE	354	mov r1, #0
	355	str r1, [r0, #CLKCTL_CACRR]
	356
782b0288 FE	357	/* Switch ARM back to PLL 1. */
	358	mov r1, #0x0
	359	str r1, [r0, #CLKCTL_CCSR]
	360
	361	/* make uart div=6 */
	362	ldr r1, [r0, #CLKCTL_CSCDR1]
	363	and r1, r1, #0xffffffc0
	364	orr r1, r1, #0x0a
	365	str r1, [r0, #CLKCTL_CSCDR1]
758c3449 FE	366
	367	/* Restore the default values in the Gate registers */
	368	ldr r1, =0xFFFFFFFF
	369	str r1, [r0, #CLKCTL_CCGR0]
	370	str r1, [r0, #CLKCTL_CCGR1]
	371	str r1, [r0, #CLKCTL_CCGR2]
	372	str r1, [r0, #CLKCTL_CCGR3]
	373	str r1, [r0, #CLKCTL_CCGR4]
	374	str r1, [r0, #CLKCTL_CCGR5]
	375	str r1, [r0, #CLKCTL_CCGR6]
	376	str r1, [r0, #CLKCTL_CCGR7]
	377
782b0288 FE	378	mov r1, #0x00000
782b0288 FE	379	str r1, [r0, #CLKCTL_CCDR]
67ee3dd3	380
782b0288 FE	381	/* for cko - for ARM div by 8 */
	382	mov r1, #0x000A0000
	383	add r1, r1, #0x00000F0
	384	str r1, [r0, #CLKCTL_CCOSR]
64fdf452	385
758c3449	386	#endif /* CONFIG_MX53 */
64fdf452 SB	387	.endm
	388
	389	.macro setup_wdog
	390	ldr r0, =WDOG1_BASE_ADDR
	391	mov r1, #0x30
	392	strh r1, [r0]
	393	.endm
	394
74236aca	395	ENTRY(lowlevel_init)
dd227b6e BT	396	mov r10, lr
	397	mov r4, #0 /* Fix R4 to 0 */
	398
595f3e56	399	#if defined(CONFIG_MX51)
64fdf452 SB	400	ldr r0, =GPIO1_BASE_ADDR
64fdf452 SB	401	ldr r1, [r0, #0x0]
18c63990	402	orr r1, r1, #1 << 23
64fdf452 SB	403	str r1, [r0, #0x0]
64fdf452 SB	404	ldr r1, [r0, #0x4]
18c63990	405	orr r1, r1, #1 << 23
64fdf452	406	str r1, [r0, #0x4]
595f3e56	407	#endif
64fdf452	408
c4fe17f6 FE	409	init_arm_erratum
c4fe17f6 FE	410
64fdf452 SB	411	init_l2cc
	412
	413	init_aips
	414
	415	init_m4if
	416
	417	init_clock
	418
dd227b6e	419	mov pc, r10
74236aca	420	ENDPROC(lowlevel_init)
64fdf452 SB	421
64fdf452 SB	422	/* Board level setting value */
dd227b6e BT	423	#if defined(CONFIG_MX51_PLL_ERRATA)
	424	W_DP_864: .word DP_OP_864
	425	.word DP_MFD_864
	426	.word DP_MFN_864
18c63990	427	W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
dd227b6e BT	428	#else
	429	W_DP_800: .word DP_OP_800
	430	.word DP_MFD_800
	431	.word DP_MFN_800
	432	#endif
	433	#if defined(CONFIG_MX51)
	434	W_DP_665: .word DP_OP_665
	435	.word DP_MFD_665
	436	.word DP_MFN_665
	437	#endif
	438	W_DP_216: .word DP_OP_216
	439	.word DP_MFD_216
	440	.word DP_MFN_216
782b0288 FE	441	W_DP_400: .word DP_OP_400
	442	.word DP_MFD_400
	443	.word DP_MFN_400
	444	W_DP_455: .word DP_OP_455
	445	.word DP_MFD_455
	446	.word DP_MFN_455