[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <asm/imx-common/hab.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
#include <mmc.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 1,
	.fuse_word = 6,
};

U_BOOT_DEVICE(imx6_thermal) = {
	.name = "imx_thermal",
	.platdata = &imx6_thermal_plat,
};
#endif

#if defined(CONFIG_SECURE_BOOT)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	.bank = 0,
	.word = 6,
};
#endif

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);
	u32 major, cfg = 0;

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	major = ((reg >> 8) & 0xff);
	if ((major >= 1) &&
	    ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
		major--;
		type = MXC_CPU_MX6QP;
		if (cfg == 1)
			type = MXC_CPU_MX6DP;
	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + (0x10 * (major + 1)));
}

/*
 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_CFG3_SPEED_SHIFT	16
#define OCOTP_CFG3_SPEED_800MHZ	0
#define OCOTP_CFG3_SPEED_850MHZ	1
#define OCOTP_CFG3_SPEED_1GHZ	2
#define OCOTP_CFG3_SPEED_1P2GHZ	3

u32 get_cpu_speed_grade_hz(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->cfg3);
	val >>= OCOTP_CFG3_SPEED_SHIFT;
	val &= 0x3;

	switch (val) {
	/* Valid for IMX6DQ */
	case OCOTP_CFG3_SPEED_1P2GHZ:
		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
			return 1200000000;
	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	case OCOTP_CFG3_SPEED_1GHZ:
		return 996000000;
	/* Valid for IMX6DQ */
	case OCOTP_CFG3_SPEED_850MHZ:
		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
			return 852000000;
	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	case OCOTP_CFG3_SPEED_800MHZ:
		return 792000000;
	}
	return 0;
}

/*
 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
 * defines a 2-bit Temperature Grade
 *
 * return temperature grade and min/max temperature in celcius
 */
#define OCOTP_MEM0_TEMP_SHIFT          6

u32 get_cpu_temp_grade(int *minc, int *maxc)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->mem0);
	val >>= OCOTP_MEM0_TEMP_SHIFT;
	val &= 0x3;

	if (minc && maxc) {
		if (val == TEMP_AUTOMOTIVE) {
			*minc = -40;
			*maxc = 125;
		} else if (val == TEMP_INDUSTRIAL) {
			*minc = -40;
			*maxc = 105;
		} else if (val == TEMP_EXTCOMMERCIAL) {
			*minc = -20;
			*maxc = 105;
		} else {
			*minc = 0;
			*maxc = 95;
		}
	}
	return val;
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;
	reg = readl(&mxc_ccm->ccdr);

	/* Clear MMDC channel mask */
	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
	writel(reg, &mxc_ccm->ccdr);
}

static void init_bandgap(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	/*
	 * Ensure the bandgap has stabilized.
	 */
	while (!(readl(&anatop->ana_misc0) & 0x80))
		;
	/*
	 * For best noise performance of the analog blocks using the
	 * outputs of the bandgap, the reftop_selfbiasoff bit should
	 * be set.
	 */
	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
}


#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;

	reg = readl(&mxc_ccm->cscmr1);
	reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	writel(reg, &mxc_ccm->cscmr1);
}
#endif

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * Disable self-bias circuit in the analog bandap.
	 * The self-bias circuit is used by the bandgap during startup.
	 * This bit should be set after the bandgap has initialized.
	 */
	init_bandgap();

	/*
	 * When low freq boot is enabled, ROM will not set AHB
	 * freq, so we need to ensure AHB freq is 132MHz in such
	 * scenario.
	 */
	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
		set_ahb_rate(132000000);

		/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
	set_preclk_from_osc();
#endif

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	init_src();

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
	return CONFIG_SYS_MMC_ENV_DEV;
}

static int mmc_get_boot_dev(void)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
	u32 soc_sbmr = readl(&src_regs->sbmr1);
	u32 bootsel;
	int devno;

	/*
	 * Refer to
	 * "i.MX 6Dual/6Quad Applications Processor Reference Manual"
	 * Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
	 * i.MX6SL/SX/UL has same layout.
	 */
	bootsel = (soc_sbmr & 0x000000FF) >> 6;

	/* No boot from sd/mmc */
	if (bootsel != 1)
		return -1;

	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	devno = (soc_sbmr & 0x00001800) >> 11;

	return devno;
}

int mmc_get_env_dev(void)
{
	int devno = mmc_get_boot_dev();

	/* If not boot from sd/mmc, use default value */
	if (devno < 0)
		return CONFIG_SYS_MMC_ENV_DEV;

	return board_mmc_get_env_dev(devno);
}

#ifdef CONFIG_SYS_MMC_ENV_PART
__weak int board_mmc_get_env_part(int devno)
{
	return CONFIG_SYS_MMC_ENV_PART;
}

uint mmc_get_env_part(struct mmc *mmc)
{
	int devno = mmc_get_boot_dev();

	/* If not boot from sd/mmc, use default value */
	if (devno < 0)
		return CONFIG_SYS_MMC_ENV_PART;

	return board_mmc_get_env_part(devno);
}
#endif
#endif

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && 
		dev_id == 1) {
		u32 value = readl(&fuse->mac_addr2);
		mac[0] = value >> 24 ;
		mac[1] = value >> 16 ;
		mac[2] = value >> 8 ;
		mac[3] = value ;

		value = readl(&fuse->mac_addr1);
		mac[4] = value >> 24 ;
		mac[5] = value >> 16 ;
		
	} else {
		u32 value = readl(&fuse->mac_addr1);
		mac[0] = (value >> 8);
		mac[1] = value ;

		value = readl(&fuse->mac_addr0);
		mac[2] = value >> 24 ;
		mac[3] = value >> 16 ;
		mac[4] = value >> 8 ;
		mac[5] = value ;
	}

}
#endif

/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 * instead of SBMR1 to determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void reset_misc(void)
{
#ifdef CONFIG_VIDEO_MXS
	lcdif_power_down();
#endif
}

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
	11	#include <asm/errno.h>
	12	#include <asm/io.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/sys_proto.h>
124a06d7	16	#include <asm/imx-common/boot_mode.h>
ae695b18	17	#include <asm/imx-common/dma.h>
6b50bfe5	18	#include <asm/imx-common/hab.h>
76c91e66	19	#include <stdbool.h>
5ea7f0e3 PKS	20	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	21	#include <asm/arch/crm_regs.h>
7a264168 YL	22	#include <dm.h>
7a264168 YL	23	#include <imx_thermal.h>
1a43dc11	24	#include <mmc.h>
23608e23	25
3d622b78 FE	26	enum ldo_reg {
	27	LDO_ARM,
	28	LDO_SOC,
	29	LDO_PU,
	30	};
	31
20332a06 TK	32	struct scu_regs {
	33	u32 ctrl;
	34	u32 config;
	35	u32 status;
	36	u32 invalidate;
	37	u32 fpga_rev;
	38	};
	39
1368f993	40	#if defined(CONFIG_IMX_THERMAL)
7a264168 YL	41	static const struct imx_thermal_plat imx6_thermal_plat = {
	42	.regs = (void *)ANATOP_BASE_ADDR,
	43	.fuse_bank = 1,
	44	.fuse_word = 6,
	45	};
	46
	47	U_BOOT_DEVICE(imx6_thermal) = {
	48	.name = "imx_thermal",
	49	.platdata = &imx6_thermal_plat,
	50	};
	51	#endif
	52
6b50bfe5 AA	53	#if defined(CONFIG_SECURE_BOOT)
	54	struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	55	.bank = 0,
	56	.word = 6,
	57	};
	58	#endif
	59
a76df709 GH	60	u32 get_nr_cpus(void)
	61	{
	62	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	63	return readl(&scu->config) & 3;
	64	}
	65
23608e23 JL	66	u32 get_cpu_rev(void)
23608e23 JL	67	{
a7683867	68	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	69	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	70	u32 type = ((reg >> 16) & 0xff);
d0acd993	71	u32 major, cfg = 0;
a7683867	72
20332a06 TK	73	if (type != MXC_CPU_MX6SL) {
20332a06 TK	74	reg = readl(&anatop->digprog);
94db6655	75	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
d0acd993	76	cfg = readl(&scu->config) & 3;
20332a06 TK	77	type = ((reg >> 16) & 0xff);
20332a06 TK	78	if (type == MXC_CPU_MX6DL) {
20332a06 TK	79	if (!cfg)
	80	type = MXC_CPU_MX6SOLO;
	81	}
94db6655 FE	82
	83	if (type == MXC_CPU_MX6Q) {
	84	if (cfg == 1)
	85	type = MXC_CPU_MX6D;
	86	}
	87
20332a06	88	}
dfd4861c	89	major = ((reg >> 8) & 0xff);
d0acd993 PF	90	if ((major >= 1) &&
	91	((type == MXC_CPU_MX6Q) \|\| (type == MXC_CPU_MX6D))) {
	92	major--;
	93	type = MXC_CPU_MX6QP;
	94	if (cfg == 1)
	95	type = MXC_CPU_MX6DP;
	96	}
20332a06	97	reg &= 0xff; /* mx6 silicon revision */
dfd4861c	98	return (type << 12) \| (reg + (0x10 * (major + 1)));
23608e23 JL	99	}
23608e23 JL	100
9b9449c3 TH	101	/*
	102	* OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
	103	* defines a 2-bit SPEED_GRADING
	104	*/
	105	#define OCOTP_CFG3_SPEED_SHIFT 16
	106	#define OCOTP_CFG3_SPEED_800MHZ 0
	107	#define OCOTP_CFG3_SPEED_850MHZ 1
	108	#define OCOTP_CFG3_SPEED_1GHZ 2
	109	#define OCOTP_CFG3_SPEED_1P2GHZ 3
	110
	111	u32 get_cpu_speed_grade_hz(void)
	112	{
	113	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	114	struct fuse_bank *bank = &ocotp->bank[0];
	115	struct fuse_bank0_regs *fuse =
	116	(struct fuse_bank0_regs *)bank->fuse_regs;
	117	uint32_t val;
	118
	119	val = readl(&fuse->cfg3);
	120	val >>= OCOTP_CFG3_SPEED_SHIFT;
	121	val &= 0x3;
	122
	123	switch (val) {
	124	/* Valid for IMX6DQ */
	125	case OCOTP_CFG3_SPEED_1P2GHZ:
	126	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D))
	127	return 1200000000;
	128	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	129	case OCOTP_CFG3_SPEED_1GHZ:
	130	return 996000000;
	131	/* Valid for IMX6DQ */
	132	case OCOTP_CFG3_SPEED_850MHZ:
	133	if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D))
	134	return 852000000;
	135	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
	136	case OCOTP_CFG3_SPEED_800MHZ:
	137	return 792000000;
	138	}
	139	return 0;
	140	}
	141
f0e8e894 TH	142	/*
	143	* OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
	144	* defines a 2-bit Temperature Grade
	145	*
	146	* return temperature grade and min/max temperature in celcius
	147	*/
	148	#define OCOTP_MEM0_TEMP_SHIFT 6
	149
	150	u32 get_cpu_temp_grade(int minc, int maxc)
	151	{
	152	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	153	struct fuse_bank *bank = &ocotp->bank[1];
	154	struct fuse_bank1_regs *fuse =
	155	(struct fuse_bank1_regs *)bank->fuse_regs;
	156	uint32_t val;
	157
	158	val = readl(&fuse->mem0);
	159	val >>= OCOTP_MEM0_TEMP_SHIFT;
	160	val &= 0x3;
	161
	162	if (minc && maxc) {
	163	if (val == TEMP_AUTOMOTIVE) {
	164	*minc = -40;
	165	*maxc = 125;
	166	} else if (val == TEMP_INDUSTRIAL) {
	167	*minc = -40;
	168	*maxc = 105;
	169	} else if (val == TEMP_EXTCOMMERCIAL) {
	170	*minc = -20;
	171	*maxc = 105;
	172	} else {
	173	*minc = 0;
	174	*maxc = 95;
	175	}
	176	}
	177	return val;
	178	}
	179
38e70077 FE	180	#ifdef CONFIG_REVISION_TAG
	181	u32 __weak get_board_rev(void)
	182	{
	183	u32 cpurev = get_cpu_rev();
	184	u32 type = ((cpurev >> 12) & 0xff);
	185	if (type == MXC_CPU_MX6SOLO)
	186	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	187
94db6655 FE	188	if (type == MXC_CPU_MX6D)
	189	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	190
38e70077 FE	191	return cpurev;
	192	}
	193	#endif
	194
e113fd19 FE	195	static void clear_ldo_ramp(void)
	196	{
	197	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	198	int reg;
	199
	200	/* ROM may modify LDO ramp up time according to fuse setting, so in
	201	* order to be in the safe side we neeed to reset these settings to
	202	* match the reset value: 0'b00
	203	*/
	204	reg = readl(&anatop->ana_misc2);
	205	reg &= ~(0x3f << 24);
	206	writel(reg, &anatop->ana_misc2);
	207	}
	208
cac833a9	209	/*
157f45da	210	* Set the PMU_REG_CORE register
cac833a9	211	*
157f45da	212	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	213	* Possible values are from 0.725V to 1.450V in steps of
	214	* 0.025V (25mV).
	215	*/
3d622b78	216	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	217	{
cac833a9 DB	218	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	219	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	220	u8 shift;
cac833a9 DB	221
	222	if (mv < 725)
	223	val = 0x00; /* Power gated off */
	224	else if (mv > 1450)
	225	val = 0x1F; /* Power FET switched full on. No regulation */
	226	else
	227	val = (mv - 700) / 25;
	228
e113fd19 FE	229	clear_ldo_ramp();
e113fd19 FE	230
3d622b78 FE	231	switch (ldo) {
	232	case LDO_SOC:
	233	shift = 18;
	234	break;
	235	case LDO_PU:
	236	shift = 9;
	237	break;
	238	case LDO_ARM:
	239	shift = 0;
	240	break;
	241	default:
	242	return -EINVAL;
	243	}
	244
39f0ac93 FE	245	old = (reg & (0x1F << shift)) >> shift;
	246	step = abs(val - old);
	247	if (step == 0)
	248	return 0;
	249
3d622b78	250	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	251	writel(reg, &anatop->reg_core);
3d622b78	252
39f0ac93 FE	253	/*
	254	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	255	* step
	256	*/
	257	udelay(3 * step);
	258
3d622b78	259	return 0;
cac833a9 DB	260	}
cac833a9 DB	261
5c92edc2 AH	262	static void set_ahb_rate(u32 val)
	263	{
	264	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	265	u32 reg, div;
	266
	267	div = get_periph_clk() / val - 1;
	268	reg = readl(&mxc_ccm->cbcdr);
	269
	270	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	271	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	272	}
	273
16197bb8 AH	274	static void clear_mmdc_ch_mask(void)
	275	{
	276	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
e1c2d68b PF	277	u32 reg;
e1c2d68b PF	278	reg = readl(&mxc_ccm->ccdr);
16197bb8 AH	279
16197bb8 AH	280	/* Clear MMDC channel mask */
e1c2d68b PF	281	reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK \| MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
e1c2d68b PF	282	writel(reg, &mxc_ccm->ccdr);
16197bb8 AH	283	}
16197bb8 AH	284
1f516faa PF	285	static void init_bandgap(void)
	286	{
	287	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	288	/*
	289	* Ensure the bandgap has stabilized.
	290	*/
	291	while (!(readl(&anatop->ana_misc0) & 0x80))
	292	;
	293	/*
	294	* For best noise performance of the analog blocks using the
	295	* outputs of the bandgap, the reftop_selfbiasoff bit should
	296	* be set.
	297	*/
	298	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
	299	}
	300
	301
0f8ec145 YL	302	#ifdef CONFIG_MX6SL
	303	static void set_preclk_from_osc(void)
	304	{
	305	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	306	u32 reg;
	307
	308	reg = readl(&mxc_ccm->cscmr1);
	309	reg \|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	310	writel(reg, &mxc_ccm->cscmr1);
	311	}
	312	#endif
	313
23608e23 JL	314	int arch_cpu_init(void)
	315	{
	316	init_aips();
	317
16197bb8 AH	318	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	319	clear_mmdc_ch_mask();
	320
1f516faa PF	321	/*
	322	* Disable self-bias circuit in the analog bandap.
	323	* The self-bias circuit is used by the bandgap during startup.
	324	* This bit should be set after the bandgap has initialized.
	325	*/
	326	init_bandgap();
	327
5c92edc2 AH	328	/*
	329	* When low freq boot is enabled, ROM will not set AHB
	330	* freq, so we need to ensure AHB freq is 132MHz in such
	331	* scenario.
	332	*/
	333	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	334	set_ahb_rate(132000000);
	335
0f8ec145 YL	336	/* Set perclk to source from OSC 24MHz */
	337	#if defined(CONFIG_MX6SL)
	338	set_preclk_from_osc();
	339	#endif
	340
76c91e66	341	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	342
	343	#ifdef CONFIG_APBH_DMA
	344	/* Start APBH DMA */
	345	mxs_dma_init();
	346	#endif
	347
9d16c52f DB	348	init_src();
9d16c52f DB	349
23608e23 JL	350	return 0;
23608e23 JL	351	}
23608e23	352
216d286c PF	353	#ifdef CONFIG_ENV_IS_IN_MMC
	354	__weak int board_mmc_get_env_dev(int devno)
	355	{
	356	return CONFIG_SYS_MMC_ENV_DEV;
	357	}
	358
1a43dc11	359	static int mmc_get_boot_dev(void)
216d286c PF	360	{
	361	struct src src_regs = (struct src )SRC_BASE_ADDR;
	362	u32 soc_sbmr = readl(&src_regs->sbmr1);
	363	u32 bootsel;
	364	int devno;
	365
	366	/*
	367	* Refer to
	368	* "i.MX 6Dual/6Quad Applications Processor Reference Manual"
	369	* Chapter "8.5.3.1 Expansion Device eFUSE Configuration"
	370	* i.MX6SL/SX/UL has same layout.
	371	*/
	372	bootsel = (soc_sbmr & 0x000000FF) >> 6;
	373
1a43dc11	374	/* No boot from sd/mmc */
216d286c	375	if (bootsel != 1)
1a43dc11	376	return -1;
216d286c PF	377
	378	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
	379	devno = (soc_sbmr & 0x00001800) >> 11;
	380
1a43dc11 SM	381	return devno;
	382	}
	383
	384	int mmc_get_env_dev(void)
	385	{
	386	int devno = mmc_get_boot_dev();
	387
	388	/* If not boot from sd/mmc, use default value */
	389	if (devno < 0)
	390	return CONFIG_SYS_MMC_ENV_DEV;
	391
216d286c PF	392	return board_mmc_get_env_dev(devno);
216d286c PF	393	}
1a43dc11 SM	394
	395	#ifdef CONFIG_SYS_MMC_ENV_PART
	396	__weak int board_mmc_get_env_part(int devno)
	397	{
	398	return CONFIG_SYS_MMC_ENV_PART;
	399	}
	400
	401	uint mmc_get_env_part(struct mmc *mmc)
	402	{
	403	int devno = mmc_get_boot_dev();
	404
	405	/* If not boot from sd/mmc, use default value */
	406	if (devno < 0)
	407	return CONFIG_SYS_MMC_ENV_PART;
	408
	409	return board_mmc_get_env_part(devno);
	410	}
	411	#endif
216d286c PF	412	#endif
216d286c PF	413
39f0ac93 FE	414	int board_postclk_init(void)
	415	{
	416	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	417
	418	return 0;
	419	}
	420
23608e23	421	#if defined(CONFIG_FEC_MXC)
be252b65	422	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	423	{
8f3ff11c BT	424	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	425	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	426	struct fuse_bank4_regs *fuse =
	427	(struct fuse_bank4_regs *)bank->fuse_regs;
	428
d4d1dd67 YL	429	if ((is_cpu_type(MXC_CPU_MX6SX) \|\| is_cpu_type(MXC_CPU_MX6UL)) &&
	430	dev_id == 1) {
	431	u32 value = readl(&fuse->mac_addr2);
	432	mac[0] = value >> 24 ;
	433	mac[1] = value >> 16 ;
	434	mac[2] = value >> 8 ;
	435	mac[3] = value ;
	436
	437	value = readl(&fuse->mac_addr1);
	438	mac[4] = value >> 24 ;
	439	mac[5] = value >> 16 ;
	440
	441	} else {
	442	u32 value = readl(&fuse->mac_addr1);
	443	mac[0] = (value >> 8);
	444	mac[1] = value ;
	445
	446	value = readl(&fuse->mac_addr0);
	447	mac[2] = value >> 24 ;
	448	mac[3] = value >> 16 ;
	449	mac[4] = value >> 8 ;
	450	mac[5] = value ;
	451	}
23608e23 JL	452
	453	}
	454	#endif
124a06d7	455
124a06d7 TK	456	/*
	457	* cfg_val will be used for
	458	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
f2863ff3 NK	459	* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
f2863ff3 NK	460	* instead of SBMR1 to determine the boot device.
124a06d7 TK	461	*/
	462	const struct boot_mode soc_boot_modes[] = {
	463	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	464	/* reserved value should start rom usb */
	465	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	466	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	467	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	468	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	469	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	470	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	471	/* 4 bit bus width */
	472	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	473	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	474	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	475	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	476	{NULL, 0},
	477	};
8f393776	478
eb111bb3 PF	479	void reset_misc(void)
	480	{
	481	#ifdef CONFIG_VIDEO_MXS
	482	lcdif_power_down();
	483	#endif
	484	}
	485
8f393776 SW	486	void s_init(void)
8f393776 SW	487	{
8467faef	488	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	489	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	490	u32 mask480;
8467faef EN	491	u32 mask528;
9293d7fd	492	u32 reg, periph1, periph2;
a3df99b5	493
db1c217c	494	if (is_cpu_type(MXC_CPU_MX6SX) \|\| is_cpu_type(MXC_CPU_MX6UL))
a3df99b5 FE	495	return;
a3df99b5 FE	496
8467faef EN	497	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	498	* to make sure PFD is working right, otherwise, PFDs may
	499	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	500	* workaround in ROM code, as bus clock need it
	501	*/
	502
	503	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	504	ANATOP_PFD_CLKGATE_MASK(1) \|
	505	ANATOP_PFD_CLKGATE_MASK(2) \|
	506	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	507	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	508	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	509
9293d7fd YL	510	reg = readl(&ccm->cbcmr);
	511	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	512	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	513	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	514	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	515
	516	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	517	if ((periph2 != 0x2) && (periph1 != 0x2))
	518	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	519
	520	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	521	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	522	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	523
8467faef EN	524	writel(mask480, &anatop->pfd_480_set);
	525	writel(mask528, &anatop->pfd_528_set);
	526	writel(mask480, &anatop->pfd_480_clr);
	527	writel(mask528, &anatop->pfd_528_clr);
8f393776	528	}
5ea7f0e3 PKS	529
	530	#ifdef CONFIG_IMX_HDMI
	531	void imx_enable_hdmi_phy(void)
	532	{
	533	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	534	u8 reg;
	535	reg = readb(&hdmi->phy_conf0);
	536	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	537	writeb(reg, &hdmi->phy_conf0);
	538	udelay(3000);
	539	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	540	writeb(reg, &hdmi->phy_conf0);
	541	udelay(3000);
	542	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	543	writeb(reg, &hdmi->phy_conf0);
	544	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	545	}
	546
	547	void imx_setup_hdmi(void)
	548	{
	549	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	550	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	551	int reg;
	552
	553	/* Turn on HDMI PHY clock */
	554	reg = readl(&mxc_ccm->CCGR2);
	555	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	556	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	557	writel(reg, &mxc_ccm->CCGR2);
	558	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	559	reg = readl(&mxc_ccm->chsccdr);
	560	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	561	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	562	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	563	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	564	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	565	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	566	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	567	writel(reg, &mxc_ccm->chsccdr);
	568	}
	569	#endif