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23608e23 JL |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
23608e23 JL |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <asm/errno.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/arch/imx-regs.h> | |
14 | #include <asm/arch/clock.h> | |
15 | #include <asm/arch/sys_proto.h> | |
124a06d7 | 16 | #include <asm/imx-common/boot_mode.h> |
ae695b18 | 17 | #include <asm/imx-common/dma.h> |
76c91e66 | 18 | #include <stdbool.h> |
5ea7f0e3 PKS |
19 | #include <asm/arch/mxc_hdmi.h> |
20 | #include <asm/arch/crm_regs.h> | |
23608e23 | 21 | |
3d622b78 FE |
22 | enum ldo_reg { |
23 | LDO_ARM, | |
24 | LDO_SOC, | |
25 | LDO_PU, | |
26 | }; | |
27 | ||
20332a06 TK |
28 | struct scu_regs { |
29 | u32 ctrl; | |
30 | u32 config; | |
31 | u32 status; | |
32 | u32 invalidate; | |
33 | u32 fpga_rev; | |
34 | }; | |
35 | ||
23608e23 JL |
36 | u32 get_cpu_rev(void) |
37 | { | |
a7683867 | 38 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
20332a06 TK |
39 | u32 reg = readl(&anatop->digprog_sololite); |
40 | u32 type = ((reg >> 16) & 0xff); | |
a7683867 | 41 | |
20332a06 TK |
42 | if (type != MXC_CPU_MX6SL) { |
43 | reg = readl(&anatop->digprog); | |
44 | type = ((reg >> 16) & 0xff); | |
45 | if (type == MXC_CPU_MX6DL) { | |
46 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; | |
47 | u32 cfg = readl(&scu->config) & 3; | |
23608e23 | 48 | |
20332a06 TK |
49 | if (!cfg) |
50 | type = MXC_CPU_MX6SOLO; | |
51 | } | |
52 | } | |
53 | reg &= 0xff; /* mx6 silicon revision */ | |
54 | return (type << 12) | (reg + 0x10); | |
23608e23 JL |
55 | } |
56 | ||
38e70077 FE |
57 | #ifdef CONFIG_REVISION_TAG |
58 | u32 __weak get_board_rev(void) | |
59 | { | |
60 | u32 cpurev = get_cpu_rev(); | |
61 | u32 type = ((cpurev >> 12) & 0xff); | |
62 | if (type == MXC_CPU_MX6SOLO) | |
63 | cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); | |
64 | ||
65 | return cpurev; | |
66 | } | |
67 | #endif | |
68 | ||
23608e23 JL |
69 | void init_aips(void) |
70 | { | |
f2f77458 JL |
71 | struct aipstz_regs *aips1, *aips2; |
72 | ||
73 | aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; | |
74 | aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; | |
23608e23 JL |
75 | |
76 | /* | |
77 | * Set all MPROTx to be non-bufferable, trusted for R/W, | |
78 | * not forced to user-mode. | |
79 | */ | |
f2f77458 JL |
80 | writel(0x77777777, &aips1->mprot0); |
81 | writel(0x77777777, &aips1->mprot1); | |
82 | writel(0x77777777, &aips2->mprot0); | |
83 | writel(0x77777777, &aips2->mprot1); | |
23608e23 | 84 | |
f2f77458 JL |
85 | /* |
86 | * Set all OPACRx to be non-bufferable, not require | |
87 | * supervisor privilege level for access,allow for | |
88 | * write access and untrusted master access. | |
89 | */ | |
90 | writel(0x00000000, &aips1->opacr0); | |
91 | writel(0x00000000, &aips1->opacr1); | |
92 | writel(0x00000000, &aips1->opacr2); | |
93 | writel(0x00000000, &aips1->opacr3); | |
94 | writel(0x00000000, &aips1->opacr4); | |
95 | writel(0x00000000, &aips2->opacr0); | |
96 | writel(0x00000000, &aips2->opacr1); | |
97 | writel(0x00000000, &aips2->opacr2); | |
98 | writel(0x00000000, &aips2->opacr3); | |
99 | writel(0x00000000, &aips2->opacr4); | |
23608e23 JL |
100 | } |
101 | ||
e113fd19 FE |
102 | static void clear_ldo_ramp(void) |
103 | { | |
104 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
105 | int reg; | |
106 | ||
107 | /* ROM may modify LDO ramp up time according to fuse setting, so in | |
108 | * order to be in the safe side we neeed to reset these settings to | |
109 | * match the reset value: 0'b00 | |
110 | */ | |
111 | reg = readl(&anatop->ana_misc2); | |
112 | reg &= ~(0x3f << 24); | |
113 | writel(reg, &anatop->ana_misc2); | |
114 | } | |
115 | ||
cac833a9 DB |
116 | /* |
117 | * Set the VDDSOC | |
118 | * | |
119 | * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set | |
120 | * them to the specified millivolt level. | |
121 | * Possible values are from 0.725V to 1.450V in steps of | |
122 | * 0.025V (25mV). | |
123 | */ | |
3d622b78 | 124 | static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) |
cac833a9 DB |
125 | { |
126 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
39f0ac93 | 127 | u32 val, step, old, reg = readl(&anatop->reg_core); |
3d622b78 | 128 | u8 shift; |
cac833a9 DB |
129 | |
130 | if (mv < 725) | |
131 | val = 0x00; /* Power gated off */ | |
132 | else if (mv > 1450) | |
133 | val = 0x1F; /* Power FET switched full on. No regulation */ | |
134 | else | |
135 | val = (mv - 700) / 25; | |
136 | ||
e113fd19 FE |
137 | clear_ldo_ramp(); |
138 | ||
3d622b78 FE |
139 | switch (ldo) { |
140 | case LDO_SOC: | |
141 | shift = 18; | |
142 | break; | |
143 | case LDO_PU: | |
144 | shift = 9; | |
145 | break; | |
146 | case LDO_ARM: | |
147 | shift = 0; | |
148 | break; | |
149 | default: | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
39f0ac93 FE |
153 | old = (reg & (0x1F << shift)) >> shift; |
154 | step = abs(val - old); | |
155 | if (step == 0) | |
156 | return 0; | |
157 | ||
3d622b78 | 158 | reg = (reg & ~(0x1F << shift)) | (val << shift); |
cac833a9 | 159 | writel(reg, &anatop->reg_core); |
3d622b78 | 160 | |
39f0ac93 FE |
161 | /* |
162 | * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per | |
163 | * step | |
164 | */ | |
165 | udelay(3 * step); | |
166 | ||
3d622b78 | 167 | return 0; |
cac833a9 DB |
168 | } |
169 | ||
76c91e66 FE |
170 | static void imx_set_wdog_powerdown(bool enable) |
171 | { | |
172 | struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; | |
173 | struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; | |
174 | ||
175 | /* Write to the PDE (Power Down Enable) bit */ | |
176 | writew(enable, &wdog1->wmcr); | |
177 | writew(enable, &wdog2->wmcr); | |
178 | } | |
179 | ||
5c92edc2 AH |
180 | static void set_ahb_rate(u32 val) |
181 | { | |
182 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
183 | u32 reg, div; | |
184 | ||
185 | div = get_periph_clk() / val - 1; | |
186 | reg = readl(&mxc_ccm->cbcdr); | |
187 | ||
188 | writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | | |
189 | (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); | |
190 | } | |
191 | ||
23608e23 JL |
192 | int arch_cpu_init(void) |
193 | { | |
194 | init_aips(); | |
195 | ||
5c92edc2 AH |
196 | /* |
197 | * When low freq boot is enabled, ROM will not set AHB | |
198 | * freq, so we need to ensure AHB freq is 132MHz in such | |
199 | * scenario. | |
200 | */ | |
201 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) | |
202 | set_ahb_rate(132000000); | |
203 | ||
76c91e66 | 204 | imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ |
ae695b18 SR |
205 | |
206 | #ifdef CONFIG_APBH_DMA | |
207 | /* Start APBH DMA */ | |
208 | mxs_dma_init(); | |
209 | #endif | |
210 | ||
23608e23 JL |
211 | return 0; |
212 | } | |
23608e23 | 213 | |
39f0ac93 FE |
214 | int board_postclk_init(void) |
215 | { | |
216 | set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
4d422fe2 EN |
221 | #ifndef CONFIG_SYS_DCACHE_OFF |
222 | void enable_caches(void) | |
223 | { | |
ebaf6b26 FL |
224 | /* Avoid random hang when download by usb */ |
225 | invalidate_dcache_all(); | |
4d422fe2 EN |
226 | /* Enable D-cache. I-cache is already enabled in start.S */ |
227 | dcache_enable(); | |
228 | } | |
229 | #endif | |
230 | ||
23608e23 | 231 | #if defined(CONFIG_FEC_MXC) |
be252b65 | 232 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
23608e23 | 233 | { |
8f3ff11c BT |
234 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
235 | struct fuse_bank *bank = &ocotp->bank[4]; | |
23608e23 JL |
236 | struct fuse_bank4_regs *fuse = |
237 | (struct fuse_bank4_regs *)bank->fuse_regs; | |
238 | ||
bd2e27c0 JL |
239 | u32 value = readl(&fuse->mac_addr_high); |
240 | mac[0] = (value >> 8); | |
241 | mac[1] = value ; | |
23608e23 | 242 | |
bd2e27c0 JL |
243 | value = readl(&fuse->mac_addr_low); |
244 | mac[2] = value >> 24 ; | |
245 | mac[3] = value >> 16 ; | |
246 | mac[4] = value >> 8 ; | |
247 | mac[5] = value ; | |
23608e23 JL |
248 | |
249 | } | |
250 | #endif | |
124a06d7 TK |
251 | |
252 | void boot_mode_apply(unsigned cfg_val) | |
253 | { | |
254 | unsigned reg; | |
2af7e810 | 255 | struct src *psrc = (struct src *)SRC_BASE_ADDR; |
124a06d7 TK |
256 | writel(cfg_val, &psrc->gpr9); |
257 | reg = readl(&psrc->gpr10); | |
258 | if (cfg_val) | |
259 | reg |= 1 << 28; | |
260 | else | |
261 | reg &= ~(1 << 28); | |
262 | writel(reg, &psrc->gpr10); | |
263 | } | |
264 | /* | |
265 | * cfg_val will be used for | |
266 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
267 | * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] | |
268 | * to SBMR1, which will determine the boot device. | |
269 | */ | |
270 | const struct boot_mode soc_boot_modes[] = { | |
271 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, | |
272 | /* reserved value should start rom usb */ | |
273 | {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, | |
274 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, | |
275 | {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, | |
276 | {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, | |
277 | {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, | |
278 | {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, | |
279 | /* 4 bit bus width */ | |
280 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, | |
281 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
282 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
283 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, | |
284 | {NULL, 0}, | |
285 | }; | |
8f393776 SW |
286 | |
287 | void s_init(void) | |
288 | { | |
8467faef EN |
289 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
290 | int is_6q = is_cpu_type(MXC_CPU_MX6Q); | |
291 | u32 mask480; | |
292 | u32 mask528; | |
293 | ||
294 | /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs | |
295 | * to make sure PFD is working right, otherwise, PFDs may | |
296 | * not output clock after reset, MX6DL and MX6SL have added 396M pfd | |
297 | * workaround in ROM code, as bus clock need it | |
298 | */ | |
299 | ||
300 | mask480 = ANATOP_PFD_CLKGATE_MASK(0) | | |
301 | ANATOP_PFD_CLKGATE_MASK(1) | | |
302 | ANATOP_PFD_CLKGATE_MASK(2) | | |
303 | ANATOP_PFD_CLKGATE_MASK(3); | |
304 | mask528 = ANATOP_PFD_CLKGATE_MASK(0) | | |
305 | ANATOP_PFD_CLKGATE_MASK(1) | | |
306 | ANATOP_PFD_CLKGATE_MASK(3); | |
307 | ||
308 | /* | |
309 | * Don't reset PFD2 on DL/S | |
310 | */ | |
311 | if (is_6q) | |
312 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); | |
313 | writel(mask480, &anatop->pfd_480_set); | |
314 | writel(mask528, &anatop->pfd_528_set); | |
315 | writel(mask480, &anatop->pfd_480_clr); | |
316 | writel(mask528, &anatop->pfd_528_clr); | |
8f393776 | 317 | } |
5ea7f0e3 PKS |
318 | |
319 | #ifdef CONFIG_IMX_HDMI | |
320 | void imx_enable_hdmi_phy(void) | |
321 | { | |
322 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; | |
323 | u8 reg; | |
324 | reg = readb(&hdmi->phy_conf0); | |
325 | reg |= HDMI_PHY_CONF0_PDZ_MASK; | |
326 | writeb(reg, &hdmi->phy_conf0); | |
327 | udelay(3000); | |
328 | reg |= HDMI_PHY_CONF0_ENTMDS_MASK; | |
329 | writeb(reg, &hdmi->phy_conf0); | |
330 | udelay(3000); | |
331 | reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; | |
332 | writeb(reg, &hdmi->phy_conf0); | |
333 | writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); | |
334 | } | |
335 | ||
336 | void imx_setup_hdmi(void) | |
337 | { | |
338 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
339 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; | |
340 | int reg; | |
341 | ||
342 | /* Turn on HDMI PHY clock */ | |
343 | reg = readl(&mxc_ccm->CCGR2); | |
344 | reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| | |
345 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; | |
346 | writel(reg, &mxc_ccm->CCGR2); | |
347 | writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); | |
348 | reg = readl(&mxc_ccm->chsccdr); | |
349 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| | |
350 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| | |
351 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); | |
352 | reg |= (CHSCCDR_PODF_DIVIDE_BY_3 | |
353 | << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | |
354 | |(CHSCCDR_IPU_PRE_CLK_540M_PFD | |
355 | << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); | |
356 | writel(reg, &mxc_ccm->chsccdr); | |
357 | } | |
358 | #endif |