[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
			u32 cfg = readl(&scu->config) & 3;

			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}
	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + 0x10);
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

void init_aips(void)
{
	struct aipstz_regs *aips1, *aips2;

	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;

	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);
	writel(0x77777777, &aips2->mprot0);
	writel(0x77777777, &aips2->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips1->opacr0);
	writel(0x00000000, &aips1->opacr1);
	writel(0x00000000, &aips1->opacr2);
	writel(0x00000000, &aips1->opacr3);
	writel(0x00000000, &aips1->opacr4);
	writel(0x00000000, &aips2->opacr0);
	writel(0x00000000, &aips2->opacr1);
	writel(0x00000000, &aips2->opacr2);
	writel(0x00000000, &aips2->opacr3);
	writel(0x00000000, &aips2->opacr4);
}

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the VDDSOC
 *
 * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
 * them to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void imx_set_wdog_powerdown(bool enable)
{
	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

	/* Write to the PDE (Power Down Enable) bit */
	writew(enable, &wdog1->wmcr);
	writew(enable, &wdog2->wmcr);
}

int arch_cpu_init(void)
{
	init_aips();

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	return 0;
}

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Avoid random hang when download by usb */
	invalidate_dcache_all();
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	u32 value = readl(&fuse->mac_addr_high);
	mac[0] = (value >> 8);
	mac[1] = value ;

	value = readl(&fuse->mac_addr_low);
	mac[2] = value >> 24 ;
	mac[3] = value >> 16 ;
	mac[4] = value >> 8 ;
	mac[5] = value ;

}
#endif

void boot_mode_apply(unsigned cfg_val)
{
	unsigned reg;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	writel(cfg_val, &psrc->gpr9);
	reg = readl(&psrc->gpr10);
	if (cfg_val)
		reg |= 1 << 28;
	else
		reg &= ~(1 << 28);
	writel(reg, &psrc->gpr10);
}
/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 * to SBMR1, which will determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"escpi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"escpi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"escpi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"escpi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int is_6q = is_cpu_type(MXC_CPU_MX6Q);
	u32 mask480;
	u32 mask528;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	/*
	 * Don't reset PFD2 on DL/S
	 */
	if (is_6q)
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
	11	#include <asm/errno.h>
	12	#include <asm/io.h>
	13	#include <asm/arch/imx-regs.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch/sys_proto.h>
124a06d7	16	#include <asm/imx-common/boot_mode.h>
ae695b18	17	#include <asm/imx-common/dma.h>
76c91e66	18	#include <stdbool.h>
5ea7f0e3 PKS	19	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	20	#include <asm/arch/crm_regs.h>
23608e23	21
3d622b78 FE	22	enum ldo_reg {
	23	LDO_ARM,
	24	LDO_SOC,
	25	LDO_PU,
	26	};
	27
20332a06 TK	28	struct scu_regs {
	29	u32 ctrl;
	30	u32 config;
	31	u32 status;
	32	u32 invalidate;
	33	u32 fpga_rev;
	34	};
	35
23608e23 JL	36	u32 get_cpu_rev(void)
23608e23 JL	37	{
a7683867	38	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	39	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	40	u32 type = ((reg >> 16) & 0xff);
a7683867	41
20332a06 TK	42	if (type != MXC_CPU_MX6SL) {
	43	reg = readl(&anatop->digprog);
	44	type = ((reg >> 16) & 0xff);
	45	if (type == MXC_CPU_MX6DL) {
	46	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	47	u32 cfg = readl(&scu->config) & 3;
23608e23	48
20332a06 TK	49	if (!cfg)
	50	type = MXC_CPU_MX6SOLO;
	51	}
	52	}
	53	reg &= 0xff; /* mx6 silicon revision */
	54	return (type << 12) \| (reg + 0x10);
23608e23 JL	55	}
23608e23 JL	56
38e70077 FE	57	#ifdef CONFIG_REVISION_TAG
	58	u32 __weak get_board_rev(void)
	59	{
	60	u32 cpurev = get_cpu_rev();
	61	u32 type = ((cpurev >> 12) & 0xff);
	62	if (type == MXC_CPU_MX6SOLO)
	63	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	64
	65	return cpurev;
	66	}
	67	#endif
	68
23608e23 JL	69	void init_aips(void)
23608e23 JL	70	{
f2f77458 JL	71	struct aipstz_regs aips1, aips2;
	72
	73	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	74	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
23608e23 JL	75
	76	/*
	77	* Set all MPROTx to be non-bufferable, trusted for R/W,
	78	* not forced to user-mode.
	79	*/
f2f77458 JL	80	writel(0x77777777, &aips1->mprot0);
	81	writel(0x77777777, &aips1->mprot1);
	82	writel(0x77777777, &aips2->mprot0);
	83	writel(0x77777777, &aips2->mprot1);
23608e23	84
f2f77458 JL	85	/*
	86	* Set all OPACRx to be non-bufferable, not require
	87	* supervisor privilege level for access,allow for
	88	* write access and untrusted master access.
	89	*/
	90	writel(0x00000000, &aips1->opacr0);
	91	writel(0x00000000, &aips1->opacr1);
	92	writel(0x00000000, &aips1->opacr2);
	93	writel(0x00000000, &aips1->opacr3);
	94	writel(0x00000000, &aips1->opacr4);
	95	writel(0x00000000, &aips2->opacr0);
	96	writel(0x00000000, &aips2->opacr1);
	97	writel(0x00000000, &aips2->opacr2);
	98	writel(0x00000000, &aips2->opacr3);
	99	writel(0x00000000, &aips2->opacr4);
23608e23 JL	100	}
23608e23 JL	101
e113fd19 FE	102	static void clear_ldo_ramp(void)
	103	{
	104	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	105	int reg;
	106
	107	/* ROM may modify LDO ramp up time according to fuse setting, so in
	108	* order to be in the safe side we neeed to reset these settings to
	109	* match the reset value: 0'b00
	110	*/
	111	reg = readl(&anatop->ana_misc2);
	112	reg &= ~(0x3f << 24);
	113	writel(reg, &anatop->ana_misc2);
	114	}
	115
cac833a9 DB	116	/*
	117	* Set the VDDSOC
	118	*
	119	* Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
	120	* them to the specified millivolt level.
	121	* Possible values are from 0.725V to 1.450V in steps of
	122	* 0.025V (25mV).
	123	*/
3d622b78	124	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	125	{
cac833a9 DB	126	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	127	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	128	u8 shift;
cac833a9 DB	129
	130	if (mv < 725)
	131	val = 0x00; /* Power gated off */
	132	else if (mv > 1450)
	133	val = 0x1F; /* Power FET switched full on. No regulation */
	134	else
	135	val = (mv - 700) / 25;
	136
e113fd19 FE	137	clear_ldo_ramp();
e113fd19 FE	138
3d622b78 FE	139	switch (ldo) {
	140	case LDO_SOC:
	141	shift = 18;
	142	break;
	143	case LDO_PU:
	144	shift = 9;
	145	break;
	146	case LDO_ARM:
	147	shift = 0;
	148	break;
	149	default:
	150	return -EINVAL;
	151	}
	152
39f0ac93 FE	153	old = (reg & (0x1F << shift)) >> shift;
	154	step = abs(val - old);
	155	if (step == 0)
	156	return 0;
	157
3d622b78	158	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	159	writel(reg, &anatop->reg_core);
3d622b78	160
39f0ac93 FE	161	/*
	162	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	163	* step
	164	*/
	165	udelay(3 * step);
	166
3d622b78	167	return 0;
cac833a9 DB	168	}
cac833a9 DB	169
76c91e66 FE	170	static void imx_set_wdog_powerdown(bool enable)
	171	{
	172	struct wdog_regs wdog1 = (struct wdog_regs )WDOG1_BASE_ADDR;
	173	struct wdog_regs wdog2 = (struct wdog_regs )WDOG2_BASE_ADDR;
	174
	175	/* Write to the PDE (Power Down Enable) bit */
	176	writew(enable, &wdog1->wmcr);
	177	writew(enable, &wdog2->wmcr);
	178	}
	179
23608e23 JL	180	int arch_cpu_init(void)
	181	{
	182	init_aips();
	183
76c91e66	184	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	185
	186	#ifdef CONFIG_APBH_DMA
	187	/* Start APBH DMA */
	188	mxs_dma_init();
	189	#endif
	190
23608e23 JL	191	return 0;
23608e23 JL	192	}
23608e23	193
39f0ac93 FE	194	int board_postclk_init(void)
	195	{
	196	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	197
	198	return 0;
	199	}
	200
4d422fe2 EN	201	#ifndef CONFIG_SYS_DCACHE_OFF
	202	void enable_caches(void)
	203	{
ebaf6b26 FL	204	/* Avoid random hang when download by usb */
ebaf6b26 FL	205	invalidate_dcache_all();
4d422fe2 EN	206	/* Enable D-cache. I-cache is already enabled in start.S */
	207	dcache_enable();
	208	}
	209	#endif
	210
23608e23	211	#if defined(CONFIG_FEC_MXC)
be252b65	212	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	213	{
8f3ff11c BT	214	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	215	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	216	struct fuse_bank4_regs *fuse =
	217	(struct fuse_bank4_regs *)bank->fuse_regs;
	218
bd2e27c0 JL	219	u32 value = readl(&fuse->mac_addr_high);
	220	mac[0] = (value >> 8);
	221	mac[1] = value ;
23608e23	222
bd2e27c0 JL	223	value = readl(&fuse->mac_addr_low);
	224	mac[2] = value >> 24 ;
	225	mac[3] = value >> 16 ;
	226	mac[4] = value >> 8 ;
	227	mac[5] = value ;
23608e23 JL	228
	229	}
	230	#endif
124a06d7 TK	231
	232	void boot_mode_apply(unsigned cfg_val)
	233	{
	234	unsigned reg;
2af7e810	235	struct src psrc = (struct src )SRC_BASE_ADDR;
124a06d7 TK	236	writel(cfg_val, &psrc->gpr9);
	237	reg = readl(&psrc->gpr10);
	238	if (cfg_val)
	239	reg \|= 1 << 28;
	240	else
	241	reg &= ~(1 << 28);
	242	writel(reg, &psrc->gpr10);
	243	}
	244	/*
	245	* cfg_val will be used for
	246	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
	247	* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
	248	* to SBMR1, which will determine the boot device.
	249	*/
	250	const struct boot_mode soc_boot_modes[] = {
	251	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	252	/* reserved value should start rom usb */
	253	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	254	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	255	{"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	256	{"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	257	{"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	258	{"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	259	/* 4 bit bus width */
	260	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	261	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	262	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	263	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	264	{NULL, 0},
	265	};
8f393776 SW	266
	267	void s_init(void)
	268	{
8467faef EN	269	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	270	int is_6q = is_cpu_type(MXC_CPU_MX6Q);
	271	u32 mask480;
	272	u32 mask528;
	273
	274	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	275	* to make sure PFD is working right, otherwise, PFDs may
	276	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	277	* workaround in ROM code, as bus clock need it
	278	*/
	279
	280	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	281	ANATOP_PFD_CLKGATE_MASK(1) \|
	282	ANATOP_PFD_CLKGATE_MASK(2) \|
	283	ANATOP_PFD_CLKGATE_MASK(3);
	284	mask528 = ANATOP_PFD_CLKGATE_MASK(0) \|
	285	ANATOP_PFD_CLKGATE_MASK(1) \|
	286	ANATOP_PFD_CLKGATE_MASK(3);
	287
	288	/*
	289	* Don't reset PFD2 on DL/S
	290	*/
	291	if (is_6q)
	292	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
	293	writel(mask480, &anatop->pfd_480_set);
	294	writel(mask528, &anatop->pfd_528_set);
	295	writel(mask480, &anatop->pfd_480_clr);
	296	writel(mask528, &anatop->pfd_528_clr);
8f393776	297	}
5ea7f0e3 PKS	298
	299	#ifdef CONFIG_IMX_HDMI
	300	void imx_enable_hdmi_phy(void)
	301	{
	302	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	303	u8 reg;
	304	reg = readb(&hdmi->phy_conf0);
	305	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	306	writeb(reg, &hdmi->phy_conf0);
	307	udelay(3000);
	308	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	309	writeb(reg, &hdmi->phy_conf0);
	310	udelay(3000);
	311	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	312	writeb(reg, &hdmi->phy_conf0);
	313	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	314	}
	315
	316	void imx_setup_hdmi(void)
	317	{
	318	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	319	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	320	int reg;
	321
	322	/* Turn on HDMI PHY clock */
	323	reg = readl(&mxc_ccm->CCGR2);
	324	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	325	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	326	writel(reg, &mxc_ccm->CCGR2);
	327	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	328	reg = readl(&mxc_ccm->chsccdr);
	329	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	330	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	331	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	332	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	333	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	334	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	335	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	336	writel(reg, &mxc_ccm->chsccdr);
	337	}
	338	#endif