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23608e23 JL |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <asm/errno.h> | |
28 | #include <asm/io.h> | |
29 | #include <asm/arch/imx-regs.h> | |
30 | #include <asm/arch/clock.h> | |
31 | #include <asm/arch/sys_proto.h> | |
124a06d7 | 32 | #include <asm/imx-common/boot_mode.h> |
23608e23 | 33 | |
20332a06 TK |
34 | struct scu_regs { |
35 | u32 ctrl; | |
36 | u32 config; | |
37 | u32 status; | |
38 | u32 invalidate; | |
39 | u32 fpga_rev; | |
40 | }; | |
41 | ||
23608e23 JL |
42 | u32 get_cpu_rev(void) |
43 | { | |
a7683867 | 44 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
20332a06 TK |
45 | u32 reg = readl(&anatop->digprog_sololite); |
46 | u32 type = ((reg >> 16) & 0xff); | |
a7683867 | 47 | |
20332a06 TK |
48 | if (type != MXC_CPU_MX6SL) { |
49 | reg = readl(&anatop->digprog); | |
50 | type = ((reg >> 16) & 0xff); | |
51 | if (type == MXC_CPU_MX6DL) { | |
52 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; | |
53 | u32 cfg = readl(&scu->config) & 3; | |
23608e23 | 54 | |
20332a06 TK |
55 | if (!cfg) |
56 | type = MXC_CPU_MX6SOLO; | |
57 | } | |
58 | } | |
59 | reg &= 0xff; /* mx6 silicon revision */ | |
60 | return (type << 12) | (reg + 0x10); | |
23608e23 JL |
61 | } |
62 | ||
23608e23 JL |
63 | void init_aips(void) |
64 | { | |
f2f77458 JL |
65 | struct aipstz_regs *aips1, *aips2; |
66 | ||
67 | aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; | |
68 | aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; | |
23608e23 JL |
69 | |
70 | /* | |
71 | * Set all MPROTx to be non-bufferable, trusted for R/W, | |
72 | * not forced to user-mode. | |
73 | */ | |
f2f77458 JL |
74 | writel(0x77777777, &aips1->mprot0); |
75 | writel(0x77777777, &aips1->mprot1); | |
76 | writel(0x77777777, &aips2->mprot0); | |
77 | writel(0x77777777, &aips2->mprot1); | |
23608e23 | 78 | |
f2f77458 JL |
79 | /* |
80 | * Set all OPACRx to be non-bufferable, not require | |
81 | * supervisor privilege level for access,allow for | |
82 | * write access and untrusted master access. | |
83 | */ | |
84 | writel(0x00000000, &aips1->opacr0); | |
85 | writel(0x00000000, &aips1->opacr1); | |
86 | writel(0x00000000, &aips1->opacr2); | |
87 | writel(0x00000000, &aips1->opacr3); | |
88 | writel(0x00000000, &aips1->opacr4); | |
89 | writel(0x00000000, &aips2->opacr0); | |
90 | writel(0x00000000, &aips2->opacr1); | |
91 | writel(0x00000000, &aips2->opacr2); | |
92 | writel(0x00000000, &aips2->opacr3); | |
93 | writel(0x00000000, &aips2->opacr4); | |
23608e23 JL |
94 | } |
95 | ||
cac833a9 DB |
96 | /* |
97 | * Set the VDDSOC | |
98 | * | |
99 | * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set | |
100 | * them to the specified millivolt level. | |
101 | * Possible values are from 0.725V to 1.450V in steps of | |
102 | * 0.025V (25mV). | |
103 | */ | |
104 | void set_vddsoc(u32 mv) | |
105 | { | |
106 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; | |
107 | u32 val, reg = readl(&anatop->reg_core); | |
108 | ||
109 | if (mv < 725) | |
110 | val = 0x00; /* Power gated off */ | |
111 | else if (mv > 1450) | |
112 | val = 0x1F; /* Power FET switched full on. No regulation */ | |
113 | else | |
114 | val = (mv - 700) / 25; | |
115 | ||
116 | /* | |
117 | * Mask out the REG_CORE[22:18] bits (REG2_TRIG) | |
118 | * and set them to the calculated value (0.7V + val * 0.25V) | |
119 | */ | |
120 | reg = (reg & ~(0x1F << 18)) | (val << 18); | |
121 | writel(reg, &anatop->reg_core); | |
122 | } | |
123 | ||
23608e23 JL |
124 | int arch_cpu_init(void) |
125 | { | |
126 | init_aips(); | |
127 | ||
cac833a9 DB |
128 | set_vddsoc(1200); /* Set VDDSOC to 1.2V */ |
129 | ||
23608e23 JL |
130 | return 0; |
131 | } | |
23608e23 | 132 | |
4d422fe2 EN |
133 | #ifndef CONFIG_SYS_DCACHE_OFF |
134 | void enable_caches(void) | |
135 | { | |
136 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
137 | dcache_enable(); | |
138 | } | |
139 | #endif | |
140 | ||
23608e23 | 141 | #if defined(CONFIG_FEC_MXC) |
be252b65 | 142 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
23608e23 JL |
143 | { |
144 | struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; | |
145 | struct fuse_bank *bank = &iim->bank[4]; | |
146 | struct fuse_bank4_regs *fuse = | |
147 | (struct fuse_bank4_regs *)bank->fuse_regs; | |
148 | ||
bd2e27c0 JL |
149 | u32 value = readl(&fuse->mac_addr_high); |
150 | mac[0] = (value >> 8); | |
151 | mac[1] = value ; | |
23608e23 | 152 | |
bd2e27c0 JL |
153 | value = readl(&fuse->mac_addr_low); |
154 | mac[2] = value >> 24 ; | |
155 | mac[3] = value >> 16 ; | |
156 | mac[4] = value >> 8 ; | |
157 | mac[5] = value ; | |
23608e23 JL |
158 | |
159 | } | |
160 | #endif | |
124a06d7 TK |
161 | |
162 | void boot_mode_apply(unsigned cfg_val) | |
163 | { | |
164 | unsigned reg; | |
2af7e810 | 165 | struct src *psrc = (struct src *)SRC_BASE_ADDR; |
124a06d7 TK |
166 | writel(cfg_val, &psrc->gpr9); |
167 | reg = readl(&psrc->gpr10); | |
168 | if (cfg_val) | |
169 | reg |= 1 << 28; | |
170 | else | |
171 | reg &= ~(1 << 28); | |
172 | writel(reg, &psrc->gpr10); | |
173 | } | |
174 | /* | |
175 | * cfg_val will be used for | |
176 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] | |
177 | * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] | |
178 | * to SBMR1, which will determine the boot device. | |
179 | */ | |
180 | const struct boot_mode soc_boot_modes[] = { | |
181 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, | |
182 | /* reserved value should start rom usb */ | |
183 | {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, | |
184 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, | |
185 | {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, | |
186 | {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, | |
187 | {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, | |
188 | {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, | |
189 | /* 4 bit bus width */ | |
190 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, | |
191 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
192 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | |
193 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, | |
194 | {NULL, 0}, | |
195 | }; |