[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
#include <imx_thermal.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

#if defined(CONFIG_IMX6_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 1,
	.fuse_word = 6,
};

U_BOOT_DEVICE(imx6_thermal) = {
	.name = "imx_thermal",
	.platdata = &imx6_thermal_plat,
};
#endif

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		u32 cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + 0x10);
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

void init_aips(void)
{
	struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
	struct aipstz_regs *aips3;
#endif

	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
	aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif

	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);
	writel(0x77777777, &aips2->mprot0);
	writel(0x77777777, &aips2->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips1->opacr0);
	writel(0x00000000, &aips1->opacr1);
	writel(0x00000000, &aips1->opacr2);
	writel(0x00000000, &aips1->opacr3);
	writel(0x00000000, &aips1->opacr4);
	writel(0x00000000, &aips2->opacr0);
	writel(0x00000000, &aips2->opacr1);
	writel(0x00000000, &aips2->opacr2);
	writel(0x00000000, &aips2->opacr3);
	writel(0x00000000, &aips2->opacr4);

#ifdef CONFIG_MX6SX
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips3->mprot0);
	writel(0x77777777, &aips3->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips3->opacr0);
	writel(0x00000000, &aips3->opacr1);
	writel(0x00000000, &aips3->opacr2);
	writel(0x00000000, &aips3->opacr3);
	writel(0x00000000, &aips3->opacr4);
#endif
}

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void imx_set_wdog_powerdown(bool enable)
{
	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

#ifdef CONFIG_MX6SX
	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
	writew(enable, &wdog3->wmcr);
#endif

	/* Write to the PDE (Power Down Enable) bit */
	writew(enable, &wdog1->wmcr);
	writew(enable, &wdog2->wmcr);
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Clear MMDC channel mask */
	writel(0, &mxc_ccm->ccdr);
}

static void init_bandgap(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	/*
	 * Ensure the bandgap has stabilized.
	 */
	while (!(readl(&anatop->ana_misc0) & 0x80))
		;
	/*
	 * For best noise performance of the analog blocks using the
	 * outputs of the bandgap, the reftop_selfbiasoff bit should
	 * be set.
	 */
	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
}


#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;

	reg = readl(&mxc_ccm->cscmr1);
	reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	writel(reg, &mxc_ccm->cscmr1);
}
#endif

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * Disable self-bias circuit in the analog bandap.
	 * The self-bias circuit is used by the bandgap during startup.
	 * This bit should be set after the bandgap has initialized.
	 */
	init_bandgap();

	/*
	 * When low freq boot is enabled, ROM will not set AHB
	 * freq, so we need to ensure AHB freq is 132MHz in such
	 * scenario.
	 */
	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
		set_ahb_rate(132000000);

		/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
	set_preclk_from_osc();
#endif

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	return 0;
}

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	enum dcache_option option = DCACHE_WRITETHROUGH;
#else
	enum dcache_option option = DCACHE_WRITEBACK;
#endif

	/* Avoid random hang when download by usb */
	invalidate_dcache_all();

	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();

	/* Enable caching on OCRAM and ROM */
	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
					ROMCP_ARB_END_ADDR,
					option);
	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
					IRAM_SIZE,
					option);
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	u32 value = readl(&fuse->mac_addr_high);
	mac[0] = (value >> 8);
	mac[1] = value ;

	value = readl(&fuse->mac_addr_low);
	mac[2] = value >> 24 ;
	mac[3] = value >> 16 ;
	mac[4] = value >> 8 ;
	mac[5] = value ;

}
#endif

void boot_mode_apply(unsigned cfg_val)
{
	unsigned reg;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	writel(cfg_val, &psrc->gpr9);
	reg = readl(&psrc->gpr10);
	if (cfg_val)
		reg |= 1 << 28;
	else
		reg &= ~(1 << 28);
	writel(reg, &psrc->gpr10);
}
/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 * instead of SBMR1 to determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_cpu_type(MXC_CPU_MX6SX))
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif

#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
	unsigned int val;

#if defined CONFIG_MX6SL
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	val = readl(&iomux->gpr[11]);
	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
		/* L2 cache configured as OCRAM, reset it */
		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
		writel(val, &iomux->gpr[11]);
	}
#endif

	/* Must disable the L2 before changing the latency parameters */
	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	writel(0x132, &pl310->pl310_data_latency_ctrl);

	val = readl(&pl310->pl310_prefetch_ctrl);

	/* Turn on the L2 I/D prefetch */
	val |= 0x30000000;

	/*
	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	 * But according to ARM PL310 errata: 752271
	 * ID: 752271: Double linefill feature can cause data corruption
	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	 * Workaround: The only workaround to this erratum is to disable the
	 * double linefill feature. This is the default behavior.
	 */

#ifndef CONFIG_MX6Q
	val |= 0x40800000;
#endif
	writel(val, &pl310->pl310_prefetch_ctrl);

	val = readl(&pl310->pl310_power_ctrl);
	val |= L2X0_DYNAMIC_CLK_GATING_EN;
	val |= L2X0_STNDBY_MODE_EN;
	writel(val, &pl310->pl310_power_ctrl);

	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;

	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
6d73c234	11	#include <asm/armv7.h>
5624c6bd	12	#include <asm/bootm.h>
6d73c234	13	#include <asm/pl310.h>
23608e23 JL	14	#include <asm/errno.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/imx-regs.h>
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/sys_proto.h>
124a06d7	19	#include <asm/imx-common/boot_mode.h>
ae695b18	20	#include <asm/imx-common/dma.h>
76c91e66	21	#include <stdbool.h>
5ea7f0e3 PKS	22	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	23	#include <asm/arch/crm_regs.h>
f6d48b29	24	#include <asm/bootm.h>
7a264168 YL	25	#include <dm.h>
7a264168 YL	26	#include <imx_thermal.h>
23608e23	27
3d622b78 FE	28	enum ldo_reg {
	29	LDO_ARM,
	30	LDO_SOC,
	31	LDO_PU,
	32	};
	33
20332a06 TK	34	struct scu_regs {
	35	u32 ctrl;
	36	u32 config;
	37	u32 status;
	38	u32 invalidate;
	39	u32 fpga_rev;
	40	};
	41
7a264168 YL	42	#if defined(CONFIG_IMX6_THERMAL)
	43	static const struct imx_thermal_plat imx6_thermal_plat = {
	44	.regs = (void *)ANATOP_BASE_ADDR,
	45	.fuse_bank = 1,
	46	.fuse_word = 6,
	47	};
	48
	49	U_BOOT_DEVICE(imx6_thermal) = {
	50	.name = "imx_thermal",
	51	.platdata = &imx6_thermal_plat,
	52	};
	53	#endif
	54
a76df709 GH	55	u32 get_nr_cpus(void)
	56	{
	57	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	58	return readl(&scu->config) & 3;
	59	}
	60
23608e23 JL	61	u32 get_cpu_rev(void)
23608e23 JL	62	{
a7683867	63	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	64	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	65	u32 type = ((reg >> 16) & 0xff);
a7683867	66
20332a06 TK	67	if (type != MXC_CPU_MX6SL) {
20332a06 TK	68	reg = readl(&anatop->digprog);
94db6655 FE	69	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
94db6655 FE	70	u32 cfg = readl(&scu->config) & 3;
20332a06 TK	71	type = ((reg >> 16) & 0xff);
20332a06 TK	72	if (type == MXC_CPU_MX6DL) {
20332a06 TK	73	if (!cfg)
	74	type = MXC_CPU_MX6SOLO;
	75	}
94db6655 FE	76
	77	if (type == MXC_CPU_MX6Q) {
	78	if (cfg == 1)
	79	type = MXC_CPU_MX6D;
	80	}
	81
20332a06 TK	82	}
	83	reg &= 0xff; /* mx6 silicon revision */
	84	return (type << 12) \| (reg + 0x10);
23608e23 JL	85	}
23608e23 JL	86
38e70077 FE	87	#ifdef CONFIG_REVISION_TAG
	88	u32 __weak get_board_rev(void)
	89	{
	90	u32 cpurev = get_cpu_rev();
	91	u32 type = ((cpurev >> 12) & 0xff);
	92	if (type == MXC_CPU_MX6SOLO)
	93	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	94
94db6655 FE	95	if (type == MXC_CPU_MX6D)
	96	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	97
38e70077 FE	98	return cpurev;
	99	}
	100	#endif
	101
23608e23 JL	102	void init_aips(void)
23608e23 JL	103	{
f2f77458	104	struct aipstz_regs aips1, aips2;
05d54b82 FE	105	#ifdef CONFIG_MX6SX
	106	struct aipstz_regs *aips3;
	107	#endif
f2f77458 JL	108
	109	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	110	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
05d54b82	111	#ifdef CONFIG_MX6SX
e8cdeefc	112	aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
05d54b82	113	#endif
23608e23 JL	114
	115	/*
	116	* Set all MPROTx to be non-bufferable, trusted for R/W,
	117	* not forced to user-mode.
	118	*/
f2f77458 JL	119	writel(0x77777777, &aips1->mprot0);
	120	writel(0x77777777, &aips1->mprot1);
	121	writel(0x77777777, &aips2->mprot0);
	122	writel(0x77777777, &aips2->mprot1);
23608e23	123
f2f77458 JL	124	/*
	125	* Set all OPACRx to be non-bufferable, not require
	126	* supervisor privilege level for access,allow for
	127	* write access and untrusted master access.
	128	*/
	129	writel(0x00000000, &aips1->opacr0);
	130	writel(0x00000000, &aips1->opacr1);
	131	writel(0x00000000, &aips1->opacr2);
	132	writel(0x00000000, &aips1->opacr3);
	133	writel(0x00000000, &aips1->opacr4);
	134	writel(0x00000000, &aips2->opacr0);
	135	writel(0x00000000, &aips2->opacr1);
	136	writel(0x00000000, &aips2->opacr2);
	137	writel(0x00000000, &aips2->opacr3);
	138	writel(0x00000000, &aips2->opacr4);
05d54b82 FE	139
	140	#ifdef CONFIG_MX6SX
	141	/*
	142	* Set all MPROTx to be non-bufferable, trusted for R/W,
	143	* not forced to user-mode.
	144	*/
	145	writel(0x77777777, &aips3->mprot0);
	146	writel(0x77777777, &aips3->mprot1);
	147
	148	/*
	149	* Set all OPACRx to be non-bufferable, not require
	150	* supervisor privilege level for access,allow for
	151	* write access and untrusted master access.
	152	*/
	153	writel(0x00000000, &aips3->opacr0);
	154	writel(0x00000000, &aips3->opacr1);
	155	writel(0x00000000, &aips3->opacr2);
	156	writel(0x00000000, &aips3->opacr3);
	157	writel(0x00000000, &aips3->opacr4);
	158	#endif
23608e23 JL	159	}
23608e23 JL	160
e113fd19 FE	161	static void clear_ldo_ramp(void)
	162	{
	163	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	164	int reg;
	165
	166	/* ROM may modify LDO ramp up time according to fuse setting, so in
	167	* order to be in the safe side we neeed to reset these settings to
	168	* match the reset value: 0'b00
	169	*/
	170	reg = readl(&anatop->ana_misc2);
	171	reg &= ~(0x3f << 24);
	172	writel(reg, &anatop->ana_misc2);
	173	}
	174
cac833a9	175	/*
157f45da	176	* Set the PMU_REG_CORE register
cac833a9	177	*
157f45da	178	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	179	* Possible values are from 0.725V to 1.450V in steps of
	180	* 0.025V (25mV).
	181	*/
3d622b78	182	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	183	{
cac833a9 DB	184	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	185	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	186	u8 shift;
cac833a9 DB	187
	188	if (mv < 725)
	189	val = 0x00; /* Power gated off */
	190	else if (mv > 1450)
	191	val = 0x1F; /* Power FET switched full on. No regulation */
	192	else
	193	val = (mv - 700) / 25;
	194
e113fd19 FE	195	clear_ldo_ramp();
e113fd19 FE	196
3d622b78 FE	197	switch (ldo) {
	198	case LDO_SOC:
	199	shift = 18;
	200	break;
	201	case LDO_PU:
	202	shift = 9;
	203	break;
	204	case LDO_ARM:
	205	shift = 0;
	206	break;
	207	default:
	208	return -EINVAL;
	209	}
	210
39f0ac93 FE	211	old = (reg & (0x1F << shift)) >> shift;
	212	step = abs(val - old);
	213	if (step == 0)
	214	return 0;
	215
3d622b78	216	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	217	writel(reg, &anatop->reg_core);
3d622b78	218
39f0ac93 FE	219	/*
	220	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	221	* step
	222	*/
	223	udelay(3 * step);
	224
3d622b78	225	return 0;
cac833a9 DB	226	}
cac833a9 DB	227
76c91e66 FE	228	static void imx_set_wdog_powerdown(bool enable)
	229	{
	230	struct wdog_regs wdog1 = (struct wdog_regs )WDOG1_BASE_ADDR;
	231	struct wdog_regs wdog2 = (struct wdog_regs )WDOG2_BASE_ADDR;
	232
83dd1dd9 PF	233	#ifdef CONFIG_MX6SX
	234	struct wdog_regs wdog3 = (struct wdog_regs )WDOG3_BASE_ADDR;
	235	writew(enable, &wdog3->wmcr);
	236	#endif
	237
76c91e66 FE	238	/* Write to the PDE (Power Down Enable) bit */
	239	writew(enable, &wdog1->wmcr);
	240	writew(enable, &wdog2->wmcr);
	241	}
	242
5c92edc2 AH	243	static void set_ahb_rate(u32 val)
	244	{
	245	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	246	u32 reg, div;
	247
	248	div = get_periph_clk() / val - 1;
	249	reg = readl(&mxc_ccm->cbcdr);
	250
	251	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	252	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	253	}
	254
16197bb8 AH	255	static void clear_mmdc_ch_mask(void)
	256	{
	257	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	258
	259	/* Clear MMDC channel mask */
	260	writel(0, &mxc_ccm->ccdr);
	261	}
	262
1f516faa PF	263	static void init_bandgap(void)
	264	{
	265	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	266	/*
	267	* Ensure the bandgap has stabilized.
	268	*/
	269	while (!(readl(&anatop->ana_misc0) & 0x80))
	270	;
	271	/*
	272	* For best noise performance of the analog blocks using the
	273	* outputs of the bandgap, the reftop_selfbiasoff bit should
	274	* be set.
	275	*/
	276	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
	277	}
	278
	279
0f8ec145 YL	280	#ifdef CONFIG_MX6SL
	281	static void set_preclk_from_osc(void)
	282	{
	283	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	284	u32 reg;
	285
	286	reg = readl(&mxc_ccm->cscmr1);
	287	reg \|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	288	writel(reg, &mxc_ccm->cscmr1);
	289	}
	290	#endif
	291
23608e23 JL	292	int arch_cpu_init(void)
	293	{
	294	init_aips();
	295
16197bb8 AH	296	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	297	clear_mmdc_ch_mask();
	298
1f516faa PF	299	/*
	300	* Disable self-bias circuit in the analog bandap.
	301	* The self-bias circuit is used by the bandgap during startup.
	302	* This bit should be set after the bandgap has initialized.
	303	*/
	304	init_bandgap();
	305
5c92edc2 AH	306	/*
	307	* When low freq boot is enabled, ROM will not set AHB
	308	* freq, so we need to ensure AHB freq is 132MHz in such
	309	* scenario.
	310	*/
	311	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	312	set_ahb_rate(132000000);
	313
0f8ec145 YL	314	/* Set perclk to source from OSC 24MHz */
	315	#if defined(CONFIG_MX6SL)
	316	set_preclk_from_osc();
	317	#endif
	318
76c91e66	319	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	320
	321	#ifdef CONFIG_APBH_DMA
	322	/* Start APBH DMA */
	323	mxs_dma_init();
	324	#endif
	325
23608e23 JL	326	return 0;
23608e23 JL	327	}
23608e23	328
39f0ac93 FE	329	int board_postclk_init(void)
	330	{
	331	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	332
	333	return 0;
	334	}
	335
4d422fe2 EN	336	#ifndef CONFIG_SYS_DCACHE_OFF
	337	void enable_caches(void)
	338	{
36c1ca4d NG	339	#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	340	enum dcache_option option = DCACHE_WRITETHROUGH;
	341	#else
	342	enum dcache_option option = DCACHE_WRITEBACK;
	343	#endif
	344
ebaf6b26 FL	345	/* Avoid random hang when download by usb */
ebaf6b26 FL	346	invalidate_dcache_all();
36c1ca4d	347
4d422fe2 EN	348	/* Enable D-cache. I-cache is already enabled in start.S */
4d422fe2 EN	349	dcache_enable();
36c1ca4d NG	350
	351	/* Enable caching on OCRAM and ROM */
	352	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
	353	ROMCP_ARB_END_ADDR,
	354	option);
	355	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
	356	IRAM_SIZE,
	357	option);
4d422fe2 EN	358	}
	359	#endif
	360
23608e23	361	#if defined(CONFIG_FEC_MXC)
be252b65	362	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	363	{
8f3ff11c BT	364	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	365	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	366	struct fuse_bank4_regs *fuse =
	367	(struct fuse_bank4_regs *)bank->fuse_regs;
	368
bd2e27c0 JL	369	u32 value = readl(&fuse->mac_addr_high);
	370	mac[0] = (value >> 8);
	371	mac[1] = value ;
23608e23	372
bd2e27c0 JL	373	value = readl(&fuse->mac_addr_low);
	374	mac[2] = value >> 24 ;
	375	mac[3] = value >> 16 ;
	376	mac[4] = value >> 8 ;
	377	mac[5] = value ;
23608e23 JL	378
	379	}
	380	#endif
124a06d7 TK	381
	382	void boot_mode_apply(unsigned cfg_val)
	383	{
	384	unsigned reg;
2af7e810	385	struct src psrc = (struct src )SRC_BASE_ADDR;
124a06d7 TK	386	writel(cfg_val, &psrc->gpr9);
	387	reg = readl(&psrc->gpr10);
	388	if (cfg_val)
	389	reg \|= 1 << 28;
	390	else
	391	reg &= ~(1 << 28);
	392	writel(reg, &psrc->gpr10);
	393	}
	394	/*
	395	* cfg_val will be used for
	396	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
f2863ff3 NK	397	* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
f2863ff3 NK	398	* instead of SBMR1 to determine the boot device.
124a06d7 TK	399	*/
	400	const struct boot_mode soc_boot_modes[] = {
	401	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	402	/* reserved value should start rom usb */
	403	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	404	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	405	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	406	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	407	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	408	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	409	/* 4 bit bus width */
	410	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	411	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	412	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	413	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	414	{NULL, 0},
	415	};
8f393776 SW	416
	417	void s_init(void)
	418	{
8467faef	419	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	420	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	421	u32 mask480;
8467faef EN	422	u32 mask528;
9293d7fd	423	u32 reg, periph1, periph2;
a3df99b5 FE	424
	425	if (is_cpu_type(MXC_CPU_MX6SX))
	426	return;
	427
8467faef EN	428	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	429	* to make sure PFD is working right, otherwise, PFDs may
	430	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	431	* workaround in ROM code, as bus clock need it
	432	*/
	433
	434	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	435	ANATOP_PFD_CLKGATE_MASK(1) \|
	436	ANATOP_PFD_CLKGATE_MASK(2) \|
	437	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	438	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	439	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	440
9293d7fd YL	441	reg = readl(&ccm->cbcmr);
	442	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	443	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	444	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	445	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	446
	447	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	448	if ((periph2 != 0x2) && (periph1 != 0x2))
	449	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	450
	451	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	452	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	453	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	454
8467faef EN	455	writel(mask480, &anatop->pfd_480_set);
	456	writel(mask528, &anatop->pfd_528_set);
	457	writel(mask480, &anatop->pfd_480_clr);
	458	writel(mask528, &anatop->pfd_528_clr);
8f393776	459	}
5ea7f0e3 PKS	460
	461	#ifdef CONFIG_IMX_HDMI
	462	void imx_enable_hdmi_phy(void)
	463	{
	464	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	465	u8 reg;
	466	reg = readb(&hdmi->phy_conf0);
	467	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	468	writeb(reg, &hdmi->phy_conf0);
	469	udelay(3000);
	470	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	471	writeb(reg, &hdmi->phy_conf0);
	472	udelay(3000);
	473	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	474	writeb(reg, &hdmi->phy_conf0);
	475	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	476	}
	477
	478	void imx_setup_hdmi(void)
	479	{
	480	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	481	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	482	int reg;
	483
	484	/* Turn on HDMI PHY clock */
	485	reg = readl(&mxc_ccm->CCGR2);
	486	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	487	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	488	writel(reg, &mxc_ccm->CCGR2);
	489	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	490	reg = readl(&mxc_ccm->chsccdr);
	491	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	492	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	493	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	494	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	495	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	496	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	497	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	498	writel(reg, &mxc_ccm->chsccdr);
	499	}
	500	#endif
6d73c234 FE	501
	502	#ifndef CONFIG_SYS_L2CACHE_OFF
	503	#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
	504	void v7_outer_cache_enable(void)
	505	{
	506	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	507	unsigned int val;
	508
	509	#if defined CONFIG_MX6SL
	510	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	511	val = readl(&iomux->gpr[11]);
	512	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
	513	/* L2 cache configured as OCRAM, reset it */
	514	val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
	515	writel(val, &iomux->gpr[11]);
	516	}
	517	#endif
	518
4aa7ac30 YL	519	/* Must disable the L2 before changing the latency parameters */
	520	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	521
6d73c234 FE	522	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	523	writel(0x132, &pl310->pl310_data_latency_ctrl);
	524
	525	val = readl(&pl310->pl310_prefetch_ctrl);
	526
	527	/* Turn on the L2 I/D prefetch */
	528	val \|= 0x30000000;
	529
	530	/*
	531	* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	532	* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	533	* But according to ARM PL310 errata: 752271
	534	* ID: 752271: Double linefill feature can cause data corruption
	535	* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	536	* Workaround: The only workaround to this erratum is to disable the
	537	* double linefill feature. This is the default behavior.
	538	*/
	539
	540	#ifndef CONFIG_MX6Q
	541	val \|= 0x40800000;
	542	#endif
	543	writel(val, &pl310->pl310_prefetch_ctrl);
	544
	545	val = readl(&pl310->pl310_power_ctrl);
	546	val \|= L2X0_DYNAMIC_CLK_GATING_EN;
	547	val \|= L2X0_STNDBY_MODE_EN;
	548	writel(val, &pl310->pl310_power_ctrl);
	549
	550	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	551	}
	552
	553	void v7_outer_cache_disable(void)
	554	{
	555	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	556
	557	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	558	}
	559	#endif /* !CONFIG_SYS_L2CACHE_OFF */