[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/armv7.h>
#include <asm/bootm.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

#if defined(CONFIG_IMX6_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 1,
	.fuse_word = 6,
};

U_BOOT_DEVICE(imx6_thermal) = {
	.name = "imx_thermal",
	.platdata = &imx6_thermal_plat,
};
#endif

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		u32 cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + 0x10);
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

void init_aips(void)
{
	struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
	struct aipstz_regs *aips3;
#endif

	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
	aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
#endif

	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);
	writel(0x77777777, &aips2->mprot0);
	writel(0x77777777, &aips2->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips1->opacr0);
	writel(0x00000000, &aips1->opacr1);
	writel(0x00000000, &aips1->opacr2);
	writel(0x00000000, &aips1->opacr3);
	writel(0x00000000, &aips1->opacr4);
	writel(0x00000000, &aips2->opacr0);
	writel(0x00000000, &aips2->opacr1);
	writel(0x00000000, &aips2->opacr2);
	writel(0x00000000, &aips2->opacr3);
	writel(0x00000000, &aips2->opacr4);

#ifdef CONFIG_MX6SX
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips3->mprot0);
	writel(0x77777777, &aips3->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips3->opacr0);
	writel(0x00000000, &aips3->opacr1);
	writel(0x00000000, &aips3->opacr2);
	writel(0x00000000, &aips3->opacr3);
	writel(0x00000000, &aips3->opacr4);
#endif
}

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void imx_set_wdog_powerdown(bool enable)
{
	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

#ifdef CONFIG_MX6SX
	struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
	writew(enable, &wdog3->wmcr);
#endif

	/* Write to the PDE (Power Down Enable) bit */
	writew(enable, &wdog1->wmcr);
	writew(enable, &wdog2->wmcr);
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Clear MMDC channel mask */
	writel(0, &mxc_ccm->ccdr);
}

static void init_bandgap(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	/*
	 * Ensure the bandgap has stabilized.
	 */
	while (!(readl(&anatop->ana_misc0) & 0x80))
		;
	/*
	 * For best noise performance of the analog blocks using the
	 * outputs of the bandgap, the reftop_selfbiasoff bit should
	 * be set.
	 */
	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
}


#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg;

	reg = readl(&mxc_ccm->cscmr1);
	reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	writel(reg, &mxc_ccm->cscmr1);
}
#endif

#define SRC_SCR_WARM_RESET_ENABLE	0

static void init_src(void)
{
	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
	u32 val;

	/*
	 * force warm reset sources to generate cold reset
	 * for a more reliable restart
	 */
	val = readl(&src_regs->scr);
	val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
	writel(val, &src_regs->scr);
}

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * Disable self-bias circuit in the analog bandap.
	 * The self-bias circuit is used by the bandgap during startup.
	 * This bit should be set after the bandgap has initialized.
	 */
	init_bandgap();

	/*
	 * When low freq boot is enabled, ROM will not set AHB
	 * freq, so we need to ensure AHB freq is 132MHz in such
	 * scenario.
	 */
	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
		set_ahb_rate(132000000);

		/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
	set_preclk_from_osc();
#endif

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	init_src();

	return 0;
}

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	enum dcache_option option = DCACHE_WRITETHROUGH;
#else
	enum dcache_option option = DCACHE_WRITEBACK;
#endif

	/* Avoid random hang when download by usb */
	invalidate_dcache_all();

	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();

	/* Enable caching on OCRAM and ROM */
	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
					ROMCP_ARB_END_ADDR,
					option);
	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
					IRAM_SIZE,
					option);
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	u32 value = readl(&fuse->mac_addr_high);
	mac[0] = (value >> 8);
	mac[1] = value ;

	value = readl(&fuse->mac_addr_low);
	mac[2] = value >> 24 ;
	mac[3] = value >> 16 ;
	mac[4] = value >> 8 ;
	mac[5] = value ;

}
#endif

void boot_mode_apply(unsigned cfg_val)
{
	unsigned reg;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	writel(cfg_val, &psrc->gpr9);
	reg = readl(&psrc->gpr10);
	if (cfg_val)
		reg |= 1 << 28;
	else
		reg &= ~(1 << 28);
	writel(reg, &psrc->gpr10);
}
/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
 * instead of SBMR1 to determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_cpu_type(MXC_CPU_MX6SX))
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif

#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
	unsigned int val;


	/*
	 * Set bit 22 in the auxiliary control register. If this bit
	 * is cleared, PL310 treats Normal Shared Non-cacheable
	 * accesses as Cacheable no-allocate.
	 */
	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);

#if defined CONFIG_MX6SL
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	val = readl(&iomux->gpr[11]);
	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
		/* L2 cache configured as OCRAM, reset it */
		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
		writel(val, &iomux->gpr[11]);
	}
#endif

	/* Must disable the L2 before changing the latency parameters */
	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	writel(0x132, &pl310->pl310_data_latency_ctrl);

	val = readl(&pl310->pl310_prefetch_ctrl);

	/* Turn on the L2 I/D prefetch */
	val |= 0x30000000;

	/*
	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	 * But according to ARM PL310 errata: 752271
	 * ID: 752271: Double linefill feature can cause data corruption
	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	 * Workaround: The only workaround to this erratum is to disable the
	 * double linefill feature. This is the default behavior.
	 */

#ifndef CONFIG_MX6Q
	val |= 0x40800000;
#endif
	writel(val, &pl310->pl310_prefetch_ctrl);

	val = readl(&pl310->pl310_power_ctrl);
	val |= L2X0_DYNAMIC_CLK_GATING_EN;
	val |= L2X0_STNDBY_MODE_EN;
	writel(val, &pl310->pl310_power_ctrl);

	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;

	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
6d73c234	11	#include <asm/armv7.h>
5624c6bd	12	#include <asm/bootm.h>
6d73c234	13	#include <asm/pl310.h>
23608e23 JL	14	#include <asm/errno.h>
	15	#include <asm/io.h>
	16	#include <asm/arch/imx-regs.h>
	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/sys_proto.h>
124a06d7	19	#include <asm/imx-common/boot_mode.h>
ae695b18	20	#include <asm/imx-common/dma.h>
76c91e66	21	#include <stdbool.h>
5ea7f0e3 PKS	22	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	23	#include <asm/arch/crm_regs.h>
7a264168 YL	24	#include <dm.h>
7a264168 YL	25	#include <imx_thermal.h>
23608e23	26
3d622b78 FE	27	enum ldo_reg {
	28	LDO_ARM,
	29	LDO_SOC,
	30	LDO_PU,
	31	};
	32
20332a06 TK	33	struct scu_regs {
	34	u32 ctrl;
	35	u32 config;
	36	u32 status;
	37	u32 invalidate;
	38	u32 fpga_rev;
	39	};
	40
7a264168 YL	41	#if defined(CONFIG_IMX6_THERMAL)
	42	static const struct imx_thermal_plat imx6_thermal_plat = {
	43	.regs = (void *)ANATOP_BASE_ADDR,
	44	.fuse_bank = 1,
	45	.fuse_word = 6,
	46	};
	47
	48	U_BOOT_DEVICE(imx6_thermal) = {
	49	.name = "imx_thermal",
	50	.platdata = &imx6_thermal_plat,
	51	};
	52	#endif
	53
a76df709 GH	54	u32 get_nr_cpus(void)
	55	{
	56	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	57	return readl(&scu->config) & 3;
	58	}
	59
23608e23 JL	60	u32 get_cpu_rev(void)
23608e23 JL	61	{
a7683867	62	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	63	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	64	u32 type = ((reg >> 16) & 0xff);
a7683867	65
20332a06 TK	66	if (type != MXC_CPU_MX6SL) {
20332a06 TK	67	reg = readl(&anatop->digprog);
94db6655 FE	68	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
94db6655 FE	69	u32 cfg = readl(&scu->config) & 3;
20332a06 TK	70	type = ((reg >> 16) & 0xff);
20332a06 TK	71	if (type == MXC_CPU_MX6DL) {
20332a06 TK	72	if (!cfg)
	73	type = MXC_CPU_MX6SOLO;
	74	}
94db6655 FE	75
	76	if (type == MXC_CPU_MX6Q) {
	77	if (cfg == 1)
	78	type = MXC_CPU_MX6D;
	79	}
	80
20332a06 TK	81	}
	82	reg &= 0xff; /* mx6 silicon revision */
	83	return (type << 12) \| (reg + 0x10);
23608e23 JL	84	}
23608e23 JL	85
38e70077 FE	86	#ifdef CONFIG_REVISION_TAG
	87	u32 __weak get_board_rev(void)
	88	{
	89	u32 cpurev = get_cpu_rev();
	90	u32 type = ((cpurev >> 12) & 0xff);
	91	if (type == MXC_CPU_MX6SOLO)
	92	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	93
94db6655 FE	94	if (type == MXC_CPU_MX6D)
	95	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	96
38e70077 FE	97	return cpurev;
	98	}
	99	#endif
	100
23608e23 JL	101	void init_aips(void)
23608e23 JL	102	{
f2f77458	103	struct aipstz_regs aips1, aips2;
05d54b82 FE	104	#ifdef CONFIG_MX6SX
	105	struct aipstz_regs *aips3;
	106	#endif
f2f77458 JL	107
	108	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	109	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
05d54b82	110	#ifdef CONFIG_MX6SX
e8cdeefc	111	aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
05d54b82	112	#endif
23608e23 JL	113
	114	/*
	115	* Set all MPROTx to be non-bufferable, trusted for R/W,
	116	* not forced to user-mode.
	117	*/
f2f77458 JL	118	writel(0x77777777, &aips1->mprot0);
	119	writel(0x77777777, &aips1->mprot1);
	120	writel(0x77777777, &aips2->mprot0);
	121	writel(0x77777777, &aips2->mprot1);
23608e23	122
f2f77458 JL	123	/*
	124	* Set all OPACRx to be non-bufferable, not require
	125	* supervisor privilege level for access,allow for
	126	* write access and untrusted master access.
	127	*/
	128	writel(0x00000000, &aips1->opacr0);
	129	writel(0x00000000, &aips1->opacr1);
	130	writel(0x00000000, &aips1->opacr2);
	131	writel(0x00000000, &aips1->opacr3);
	132	writel(0x00000000, &aips1->opacr4);
	133	writel(0x00000000, &aips2->opacr0);
	134	writel(0x00000000, &aips2->opacr1);
	135	writel(0x00000000, &aips2->opacr2);
	136	writel(0x00000000, &aips2->opacr3);
	137	writel(0x00000000, &aips2->opacr4);
05d54b82 FE	138
	139	#ifdef CONFIG_MX6SX
	140	/*
	141	* Set all MPROTx to be non-bufferable, trusted for R/W,
	142	* not forced to user-mode.
	143	*/
	144	writel(0x77777777, &aips3->mprot0);
	145	writel(0x77777777, &aips3->mprot1);
	146
	147	/*
	148	* Set all OPACRx to be non-bufferable, not require
	149	* supervisor privilege level for access,allow for
	150	* write access and untrusted master access.
	151	*/
	152	writel(0x00000000, &aips3->opacr0);
	153	writel(0x00000000, &aips3->opacr1);
	154	writel(0x00000000, &aips3->opacr2);
	155	writel(0x00000000, &aips3->opacr3);
	156	writel(0x00000000, &aips3->opacr4);
	157	#endif
23608e23 JL	158	}
23608e23 JL	159
e113fd19 FE	160	static void clear_ldo_ramp(void)
	161	{
	162	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	163	int reg;
	164
	165	/* ROM may modify LDO ramp up time according to fuse setting, so in
	166	* order to be in the safe side we neeed to reset these settings to
	167	* match the reset value: 0'b00
	168	*/
	169	reg = readl(&anatop->ana_misc2);
	170	reg &= ~(0x3f << 24);
	171	writel(reg, &anatop->ana_misc2);
	172	}
	173
cac833a9	174	/*
157f45da	175	* Set the PMU_REG_CORE register
cac833a9	176	*
157f45da	177	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	178	* Possible values are from 0.725V to 1.450V in steps of
	179	* 0.025V (25mV).
	180	*/
3d622b78	181	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	182	{
cac833a9 DB	183	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	184	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	185	u8 shift;
cac833a9 DB	186
	187	if (mv < 725)
	188	val = 0x00; /* Power gated off */
	189	else if (mv > 1450)
	190	val = 0x1F; /* Power FET switched full on. No regulation */
	191	else
	192	val = (mv - 700) / 25;
	193
e113fd19 FE	194	clear_ldo_ramp();
e113fd19 FE	195
3d622b78 FE	196	switch (ldo) {
	197	case LDO_SOC:
	198	shift = 18;
	199	break;
	200	case LDO_PU:
	201	shift = 9;
	202	break;
	203	case LDO_ARM:
	204	shift = 0;
	205	break;
	206	default:
	207	return -EINVAL;
	208	}
	209
39f0ac93 FE	210	old = (reg & (0x1F << shift)) >> shift;
	211	step = abs(val - old);
	212	if (step == 0)
	213	return 0;
	214
3d622b78	215	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	216	writel(reg, &anatop->reg_core);
3d622b78	217
39f0ac93 FE	218	/*
	219	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	220	* step
	221	*/
	222	udelay(3 * step);
	223
3d622b78	224	return 0;
cac833a9 DB	225	}
cac833a9 DB	226
76c91e66 FE	227	static void imx_set_wdog_powerdown(bool enable)
	228	{
	229	struct wdog_regs wdog1 = (struct wdog_regs )WDOG1_BASE_ADDR;
	230	struct wdog_regs wdog2 = (struct wdog_regs )WDOG2_BASE_ADDR;
	231
83dd1dd9 PF	232	#ifdef CONFIG_MX6SX
	233	struct wdog_regs wdog3 = (struct wdog_regs )WDOG3_BASE_ADDR;
	234	writew(enable, &wdog3->wmcr);
	235	#endif
	236
76c91e66 FE	237	/* Write to the PDE (Power Down Enable) bit */
	238	writew(enable, &wdog1->wmcr);
	239	writew(enable, &wdog2->wmcr);
	240	}
	241
5c92edc2 AH	242	static void set_ahb_rate(u32 val)
	243	{
	244	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	245	u32 reg, div;
	246
	247	div = get_periph_clk() / val - 1;
	248	reg = readl(&mxc_ccm->cbcdr);
	249
	250	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	251	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	252	}
	253
16197bb8 AH	254	static void clear_mmdc_ch_mask(void)
	255	{
	256	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	257
	258	/* Clear MMDC channel mask */
	259	writel(0, &mxc_ccm->ccdr);
	260	}
	261
1f516faa PF	262	static void init_bandgap(void)
	263	{
	264	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	265	/*
	266	* Ensure the bandgap has stabilized.
	267	*/
	268	while (!(readl(&anatop->ana_misc0) & 0x80))
	269	;
	270	/*
	271	* For best noise performance of the analog blocks using the
	272	* outputs of the bandgap, the reftop_selfbiasoff bit should
	273	* be set.
	274	*/
	275	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
	276	}
	277
	278
0f8ec145 YL	279	#ifdef CONFIG_MX6SL
	280	static void set_preclk_from_osc(void)
	281	{
	282	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	283	u32 reg;
	284
	285	reg = readl(&mxc_ccm->cscmr1);
	286	reg \|= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
	287	writel(reg, &mxc_ccm->cscmr1);
	288	}
	289	#endif
	290
9d16c52f DB	291	#define SRC_SCR_WARM_RESET_ENABLE 0
	292
	293	static void init_src(void)
	294	{
	295	struct src src_regs = (struct src )SRC_BASE_ADDR;
	296	u32 val;
	297
	298	/*
	299	* force warm reset sources to generate cold reset
	300	* for a more reliable restart
	301	*/
	302	val = readl(&src_regs->scr);
	303	val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
	304	writel(val, &src_regs->scr);
	305	}
	306
23608e23 JL	307	int arch_cpu_init(void)
	308	{
	309	init_aips();
	310
16197bb8 AH	311	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	312	clear_mmdc_ch_mask();
	313
1f516faa PF	314	/*
	315	* Disable self-bias circuit in the analog bandap.
	316	* The self-bias circuit is used by the bandgap during startup.
	317	* This bit should be set after the bandgap has initialized.
	318	*/
	319	init_bandgap();
	320
5c92edc2 AH	321	/*
	322	* When low freq boot is enabled, ROM will not set AHB
	323	* freq, so we need to ensure AHB freq is 132MHz in such
	324	* scenario.
	325	*/
	326	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	327	set_ahb_rate(132000000);
	328
0f8ec145 YL	329	/* Set perclk to source from OSC 24MHz */
	330	#if defined(CONFIG_MX6SL)
	331	set_preclk_from_osc();
	332	#endif
	333
76c91e66	334	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	335
	336	#ifdef CONFIG_APBH_DMA
	337	/* Start APBH DMA */
	338	mxs_dma_init();
	339	#endif
	340
9d16c52f DB	341	init_src();
9d16c52f DB	342
23608e23 JL	343	return 0;
23608e23 JL	344	}
23608e23	345
39f0ac93 FE	346	int board_postclk_init(void)
	347	{
	348	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	349
	350	return 0;
	351	}
	352
4d422fe2 EN	353	#ifndef CONFIG_SYS_DCACHE_OFF
	354	void enable_caches(void)
	355	{
36c1ca4d NG	356	#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	357	enum dcache_option option = DCACHE_WRITETHROUGH;
	358	#else
	359	enum dcache_option option = DCACHE_WRITEBACK;
	360	#endif
	361
ebaf6b26 FL	362	/* Avoid random hang when download by usb */
ebaf6b26 FL	363	invalidate_dcache_all();
36c1ca4d	364
4d422fe2 EN	365	/* Enable D-cache. I-cache is already enabled in start.S */
4d422fe2 EN	366	dcache_enable();
36c1ca4d NG	367
	368	/* Enable caching on OCRAM and ROM */
	369	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
	370	ROMCP_ARB_END_ADDR,
	371	option);
	372	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
	373	IRAM_SIZE,
	374	option);
4d422fe2 EN	375	}
	376	#endif
	377
23608e23	378	#if defined(CONFIG_FEC_MXC)
be252b65	379	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	380	{
8f3ff11c BT	381	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	382	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	383	struct fuse_bank4_regs *fuse =
	384	(struct fuse_bank4_regs *)bank->fuse_regs;
	385
bd2e27c0 JL	386	u32 value = readl(&fuse->mac_addr_high);
	387	mac[0] = (value >> 8);
	388	mac[1] = value ;
23608e23	389
bd2e27c0 JL	390	value = readl(&fuse->mac_addr_low);
	391	mac[2] = value >> 24 ;
	392	mac[3] = value >> 16 ;
	393	mac[4] = value >> 8 ;
	394	mac[5] = value ;
23608e23 JL	395
	396	}
	397	#endif
124a06d7 TK	398
	399	void boot_mode_apply(unsigned cfg_val)
	400	{
	401	unsigned reg;
2af7e810	402	struct src psrc = (struct src )SRC_BASE_ADDR;
124a06d7 TK	403	writel(cfg_val, &psrc->gpr9);
	404	reg = readl(&psrc->gpr10);
	405	if (cfg_val)
	406	reg \|= 1 << 28;
	407	else
	408	reg &= ~(1 << 28);
	409	writel(reg, &psrc->gpr10);
	410	}
	411	/*
	412	* cfg_val will be used for
	413	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
f2863ff3 NK	414	* After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
f2863ff3 NK	415	* instead of SBMR1 to determine the boot device.
124a06d7 TK	416	*/
	417	const struct boot_mode soc_boot_modes[] = {
	418	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	419	/* reserved value should start rom usb */
	420	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	421	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	422	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	423	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	424	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	425	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	426	/* 4 bit bus width */
	427	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	428	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	429	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	430	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	431	{NULL, 0},
	432	};
8f393776 SW	433
	434	void s_init(void)
	435	{
8467faef	436	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	437	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	438	u32 mask480;
8467faef EN	439	u32 mask528;
9293d7fd	440	u32 reg, periph1, periph2;
a3df99b5 FE	441
	442	if (is_cpu_type(MXC_CPU_MX6SX))
	443	return;
	444
8467faef EN	445	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	446	* to make sure PFD is working right, otherwise, PFDs may
	447	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	448	* workaround in ROM code, as bus clock need it
	449	*/
	450
	451	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	452	ANATOP_PFD_CLKGATE_MASK(1) \|
	453	ANATOP_PFD_CLKGATE_MASK(2) \|
	454	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	455	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	456	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	457
9293d7fd YL	458	reg = readl(&ccm->cbcmr);
	459	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	460	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	461	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	462	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	463
	464	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	465	if ((periph2 != 0x2) && (periph1 != 0x2))
	466	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	467
	468	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	469	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	470	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	471
8467faef EN	472	writel(mask480, &anatop->pfd_480_set);
	473	writel(mask528, &anatop->pfd_528_set);
	474	writel(mask480, &anatop->pfd_480_clr);
	475	writel(mask528, &anatop->pfd_528_clr);
8f393776	476	}
5ea7f0e3 PKS	477
	478	#ifdef CONFIG_IMX_HDMI
	479	void imx_enable_hdmi_phy(void)
	480	{
	481	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	482	u8 reg;
	483	reg = readb(&hdmi->phy_conf0);
	484	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	485	writeb(reg, &hdmi->phy_conf0);
	486	udelay(3000);
	487	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	488	writeb(reg, &hdmi->phy_conf0);
	489	udelay(3000);
	490	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	491	writeb(reg, &hdmi->phy_conf0);
	492	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	493	}
	494
	495	void imx_setup_hdmi(void)
	496	{
	497	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	498	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	499	int reg;
	500
	501	/* Turn on HDMI PHY clock */
	502	reg = readl(&mxc_ccm->CCGR2);
	503	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	504	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	505	writel(reg, &mxc_ccm->CCGR2);
	506	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	507	reg = readl(&mxc_ccm->chsccdr);
	508	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	509	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	510	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	511	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	512	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	513	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	514	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	515	writel(reg, &mxc_ccm->chsccdr);
	516	}
	517	#endif
6d73c234 FE	518
	519	#ifndef CONFIG_SYS_L2CACHE_OFF
	520	#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
	521	void v7_outer_cache_enable(void)
	522	{
	523	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	524	unsigned int val;
	525
b4ed9f86 FE	526
	527	/*
	528	* Set bit 22 in the auxiliary control register. If this bit
	529	* is cleared, PL310 treats Normal Shared Non-cacheable
	530	* accesses as Cacheable no-allocate.
	531	*/
	532	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
	533
6d73c234 FE	534	#if defined CONFIG_MX6SL
	535	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	536	val = readl(&iomux->gpr[11]);
	537	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
	538	/* L2 cache configured as OCRAM, reset it */
	539	val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
	540	writel(val, &iomux->gpr[11]);
	541	}
	542	#endif
	543
4aa7ac30 YL	544	/* Must disable the L2 before changing the latency parameters */
	545	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	546
6d73c234 FE	547	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	548	writel(0x132, &pl310->pl310_data_latency_ctrl);
	549
	550	val = readl(&pl310->pl310_prefetch_ctrl);
	551
	552	/* Turn on the L2 I/D prefetch */
	553	val \|= 0x30000000;
	554
	555	/*
	556	* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	557	* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	558	* But according to ARM PL310 errata: 752271
	559	* ID: 752271: Double linefill feature can cause data corruption
	560	* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	561	* Workaround: The only workaround to this erratum is to disable the
	562	* double linefill feature. This is the default behavior.
	563	*/
	564
	565	#ifndef CONFIG_MX6Q
	566	val \|= 0x40800000;
	567	#endif
	568	writel(val, &pl310->pl310_prefetch_ctrl);
	569
	570	val = readl(&pl310->pl310_power_ctrl);
	571	val \|= L2X0_DYNAMIC_CLK_GATING_EN;
	572	val \|= L2X0_STNDBY_MODE_EN;
	573	writel(val, &pl310->pl310_power_ctrl);
	574
	575	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	576	}
	577
	578	void v7_outer_cache_disable(void)
	579	{
	580	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	581
	582	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	583	}
	584	#endif /* !CONFIG_SYS_L2CACHE_OFF */