[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / soc.c

/*
 * (C) Copyright 2007
 * Sascha Hauer, Pengutronix
 *
 * (C) Copyright 2009 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>

enum ldo_reg {
	LDO_ARM,
	LDO_SOC,
	LDO_PU,
};

struct scu_regs {
	u32	ctrl;
	u32	config;
	u32	status;
	u32	invalidate;
	u32	fpga_rev;
};

u32 get_nr_cpus(void)
{
	struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
	return readl(&scu->config) & 3;
}

u32 get_cpu_rev(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 reg = readl(&anatop->digprog_sololite);
	u32 type = ((reg >> 16) & 0xff);

	if (type != MXC_CPU_MX6SL) {
		reg = readl(&anatop->digprog);
		struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
		u32 cfg = readl(&scu->config) & 3;
		type = ((reg >> 16) & 0xff);
		if (type == MXC_CPU_MX6DL) {
			if (!cfg)
				type = MXC_CPU_MX6SOLO;
		}

		if (type == MXC_CPU_MX6Q) {
			if (cfg == 1)
				type = MXC_CPU_MX6D;
		}

	}
	reg &= 0xff;		/* mx6 silicon revision */
	return (type << 12) | (reg + 0x10);
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	u32 cpurev = get_cpu_rev();
	u32 type = ((cpurev >> 12) & 0xff);
	if (type == MXC_CPU_MX6SOLO)
		cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);

	if (type == MXC_CPU_MX6D)
		cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);

	return cpurev;
}
#endif

void init_aips(void)
{
	struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
	struct aipstz_regs *aips3;
#endif

	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif

	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips1->mprot0);
	writel(0x77777777, &aips1->mprot1);
	writel(0x77777777, &aips2->mprot0);
	writel(0x77777777, &aips2->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips1->opacr0);
	writel(0x00000000, &aips1->opacr1);
	writel(0x00000000, &aips1->opacr2);
	writel(0x00000000, &aips1->opacr3);
	writel(0x00000000, &aips1->opacr4);
	writel(0x00000000, &aips2->opacr0);
	writel(0x00000000, &aips2->opacr1);
	writel(0x00000000, &aips2->opacr2);
	writel(0x00000000, &aips2->opacr3);
	writel(0x00000000, &aips2->opacr4);

#ifdef CONFIG_MX6SX
	/*
	 * Set all MPROTx to be non-bufferable, trusted for R/W,
	 * not forced to user-mode.
	 */
	writel(0x77777777, &aips3->mprot0);
	writel(0x77777777, &aips3->mprot1);

	/*
	 * Set all OPACRx to be non-bufferable, not require
	 * supervisor privilege level for access,allow for
	 * write access and untrusted master access.
	 */
	writel(0x00000000, &aips3->opacr0);
	writel(0x00000000, &aips3->opacr1);
	writel(0x00000000, &aips3->opacr2);
	writel(0x00000000, &aips3->opacr3);
	writel(0x00000000, &aips3->opacr4);
#endif
}

static void clear_ldo_ramp(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	int reg;

	/* ROM may modify LDO ramp up time according to fuse setting, so in
	 * order to be in the safe side we neeed to reset these settings to
	 * match the reset value: 0'b00
	 */
	reg = readl(&anatop->ana_misc2);
	reg &= ~(0x3f << 24);
	writel(reg, &anatop->ana_misc2);
}

/*
 * Set the PMU_REG_CORE register
 *
 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
 * Possible values are from 0.725V to 1.450V in steps of
 * 0.025V (25mV).
 */
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	u32 val, step, old, reg = readl(&anatop->reg_core);
	u8 shift;

	if (mv < 725)
		val = 0x00;	/* Power gated off */
	else if (mv > 1450)
		val = 0x1F;	/* Power FET switched full on. No regulation */
	else
		val = (mv - 700) / 25;

	clear_ldo_ramp();

	switch (ldo) {
	case LDO_SOC:
		shift = 18;
		break;
	case LDO_PU:
		shift = 9;
		break;
	case LDO_ARM:
		shift = 0;
		break;
	default:
		return -EINVAL;
	}

	old = (reg & (0x1F << shift)) >> shift;
	step = abs(val - old);
	if (step == 0)
		return 0;

	reg = (reg & ~(0x1F << shift)) | (val << shift);
	writel(reg, &anatop->reg_core);

	/*
	 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	 * step
	 */
	udelay(3 * step);

	return 0;
}

static void imx_set_wdog_powerdown(bool enable)
{
	struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
	struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;

	/* Write to the PDE (Power Down Enable) bit */
	writew(enable, &wdog1->wmcr);
	writew(enable, &wdog2->wmcr);
}

static void set_ahb_rate(u32 val)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 reg, div;

	div = get_periph_clk() / val - 1;
	reg = readl(&mxc_ccm->cbcdr);

	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
		(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}

static void clear_mmdc_ch_mask(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Clear MMDC channel mask */
	writel(0, &mxc_ccm->ccdr);
}

int arch_cpu_init(void)
{
	init_aips();

	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	clear_mmdc_ch_mask();

	/*
	 * When low freq boot is enabled, ROM will not set AHB
	 * freq, so we need to ensure AHB freq is 132MHz in such
	 * scenario.
	 */
	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
		set_ahb_rate(132000000);

	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

	return 0;
}

int board_postclk_init(void)
{
	set_ldo_voltage(LDO_SOC, 1175);	/* Set VDDSOC to 1.175V */

	return 0;
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	enum dcache_option option = DCACHE_WRITETHROUGH;
#else
	enum dcache_option option = DCACHE_WRITEBACK;
#endif

	/* Avoid random hang when download by usb */
	invalidate_dcache_all();

	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();

	/* Enable caching on OCRAM and ROM */
	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
					ROMCP_ARB_END_ADDR,
					option);
	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
					IRAM_SIZE,
					option);
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[4];
	struct fuse_bank4_regs *fuse =
			(struct fuse_bank4_regs *)bank->fuse_regs;

	u32 value = readl(&fuse->mac_addr_high);
	mac[0] = (value >> 8);
	mac[1] = value ;

	value = readl(&fuse->mac_addr_low);
	mac[2] = value >> 24 ;
	mac[3] = value >> 16 ;
	mac[4] = value >> 8 ;
	mac[5] = value ;

}
#endif

void boot_mode_apply(unsigned cfg_val)
{
	unsigned reg;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	writel(cfg_val, &psrc->gpr9);
	reg = readl(&psrc->gpr10);
	if (cfg_val)
		reg |= 1 << 28;
	else
		reg &= ~(1 << 28);
	writel(reg, &psrc->gpr10);
}
/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 * to SBMR1, which will determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	/* reserved value should start rom usb */
	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	{"ecspi1:1",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	{"ecspi1:2",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	{"ecspi1:3",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
	/* 4 bit bus width */
	{"esdhc1",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	{"esdhc2",	MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"esdhc3",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{"esdhc4",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	{NULL,		0},
};

void s_init(void)
{
	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	u32 mask480;
	u32 mask528;
	u32 reg, periph1, periph2;

	if (is_cpu_type(MXC_CPU_MX6SX))
		return;

	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	 * to make sure PFD is working right, otherwise, PFDs may
	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
	 * workaround in ROM code, as bus clock need it
	 */

	mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
		ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(2) |
		ANATOP_PFD_CLKGATE_MASK(3);
	mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
		ANATOP_PFD_CLKGATE_MASK(3);

	reg = readl(&ccm->cbcmr);
	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
		>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);

	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	if ((periph2 != 0x2) && (periph1 != 0x2))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(0);

	if ((periph2 != 0x1) && (periph1 != 0x1) &&
		(periph2 != 0x3) && (periph1 != 0x3))
		mask528 |= ANATOP_PFD_CLKGATE_MASK(2);

	writel(mask480, &anatop->pfd_480_set);
	writel(mask528, &anatop->pfd_528_set);
	writel(mask480, &anatop->pfd_480_clr);
	writel(mask528, &anatop->pfd_528_clr);
}

#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	u8 reg;
	reg = readb(&hdmi->phy_conf0);
	reg |= HDMI_PHY_CONF0_PDZ_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
	writeb(reg, &hdmi->phy_conf0);
	udelay(3000);
	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	writeb(reg, &hdmi->phy_conf0);
	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}

void imx_setup_hdmi(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
	int reg;

	/* Turn on HDMI PHY clock */
	reg = readl(&mxc_ccm->CCGR2);
	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	writel(reg, &mxc_ccm->CCGR2);
	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	reg = readl(&mxc_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);
}
#endif

#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
void v7_outer_cache_enable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
	unsigned int val;

#if defined CONFIG_MX6SL
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	val = readl(&iomux->gpr[11]);
	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
		/* L2 cache configured as OCRAM, reset it */
		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
		writel(val, &iomux->gpr[11]);
	}
#endif

	/* Must disable the L2 before changing the latency parameters */
	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);

	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	writel(0x132, &pl310->pl310_data_latency_ctrl);

	val = readl(&pl310->pl310_prefetch_ctrl);

	/* Turn on the L2 I/D prefetch */
	val |= 0x30000000;

	/*
	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	 * But according to ARM PL310 errata: 752271
	 * ID: 752271: Double linefill feature can cause data corruption
	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	 * Workaround: The only workaround to this erratum is to disable the
	 * double linefill feature. This is the default behavior.
	 */

#ifndef CONFIG_MX6Q
	val |= 0x40800000;
#endif
	writel(val, &pl310->pl310_prefetch_ctrl);

	val = readl(&pl310->pl310_power_ctrl);
	val |= L2X0_DYNAMIC_CLK_GATING_EN;
	val |= L2X0_STNDBY_MODE_EN;
	writel(val, &pl310->pl310_power_ctrl);

	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}

void v7_outer_cache_disable(void)
{
	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;

	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
23608e23 JL	1	/*
	2	* (C) Copyright 2007
	3	* Sascha Hauer, Pengutronix
	4	*
	5	* (C) Copyright 2009 Freescale Semiconductor, Inc.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	8	*/
	9
	10	#include <common.h>
6d73c234 FE	11	#include <asm/armv7.h>
6d73c234 FE	12	#include <asm/pl310.h>
23608e23 JL	13	#include <asm/errno.h>
	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/sys_proto.h>
124a06d7	18	#include <asm/imx-common/boot_mode.h>
ae695b18	19	#include <asm/imx-common/dma.h>
76c91e66	20	#include <stdbool.h>
5ea7f0e3 PKS	21	#include <asm/arch/mxc_hdmi.h>
5ea7f0e3 PKS	22	#include <asm/arch/crm_regs.h>
f6d48b29	23	#include <asm/bootm.h>
23608e23	24
3d622b78 FE	25	enum ldo_reg {
	26	LDO_ARM,
	27	LDO_SOC,
	28	LDO_PU,
	29	};
	30
20332a06 TK	31	struct scu_regs {
	32	u32 ctrl;
	33	u32 config;
	34	u32 status;
	35	u32 invalidate;
	36	u32 fpga_rev;
	37	};
	38
a76df709 GH	39	u32 get_nr_cpus(void)
	40	{
	41	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
	42	return readl(&scu->config) & 3;
	43	}
	44
23608e23 JL	45	u32 get_cpu_rev(void)
23608e23 JL	46	{
a7683867	47	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
20332a06 TK	48	u32 reg = readl(&anatop->digprog_sololite);
20332a06 TK	49	u32 type = ((reg >> 16) & 0xff);
a7683867	50
20332a06 TK	51	if (type != MXC_CPU_MX6SL) {
20332a06 TK	52	reg = readl(&anatop->digprog);
94db6655 FE	53	struct scu_regs scu = (struct scu_regs )SCU_BASE_ADDR;
94db6655 FE	54	u32 cfg = readl(&scu->config) & 3;
20332a06 TK	55	type = ((reg >> 16) & 0xff);
20332a06 TK	56	if (type == MXC_CPU_MX6DL) {
20332a06 TK	57	if (!cfg)
	58	type = MXC_CPU_MX6SOLO;
	59	}
94db6655 FE	60
	61	if (type == MXC_CPU_MX6Q) {
	62	if (cfg == 1)
	63	type = MXC_CPU_MX6D;
	64	}
	65
20332a06 TK	66	}
	67	reg &= 0xff; /* mx6 silicon revision */
	68	return (type << 12) \| (reg + 0x10);
23608e23 JL	69	}
23608e23 JL	70
38e70077 FE	71	#ifdef CONFIG_REVISION_TAG
	72	u32 __weak get_board_rev(void)
	73	{
	74	u32 cpurev = get_cpu_rev();
	75	u32 type = ((cpurev >> 12) & 0xff);
	76	if (type == MXC_CPU_MX6SOLO)
	77	cpurev = (MXC_CPU_MX6DL) << 12 \| (cpurev & 0xFFF);
	78
94db6655 FE	79	if (type == MXC_CPU_MX6D)
	80	cpurev = (MXC_CPU_MX6Q) << 12 \| (cpurev & 0xFFF);
	81
38e70077 FE	82	return cpurev;
	83	}
	84	#endif
	85
23608e23 JL	86	void init_aips(void)
23608e23 JL	87	{
f2f77458	88	struct aipstz_regs aips1, aips2;
05d54b82 FE	89	#ifdef CONFIG_MX6SX
	90	struct aipstz_regs *aips3;
	91	#endif
f2f77458 JL	92
	93	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
	94	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
05d54b82 FE	95	#ifdef CONFIG_MX6SX
	96	aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
	97	#endif
23608e23 JL	98
	99	/*
	100	* Set all MPROTx to be non-bufferable, trusted for R/W,
	101	* not forced to user-mode.
	102	*/
f2f77458 JL	103	writel(0x77777777, &aips1->mprot0);
	104	writel(0x77777777, &aips1->mprot1);
	105	writel(0x77777777, &aips2->mprot0);
	106	writel(0x77777777, &aips2->mprot1);
23608e23	107
f2f77458 JL	108	/*
	109	* Set all OPACRx to be non-bufferable, not require
	110	* supervisor privilege level for access,allow for
	111	* write access and untrusted master access.
	112	*/
	113	writel(0x00000000, &aips1->opacr0);
	114	writel(0x00000000, &aips1->opacr1);
	115	writel(0x00000000, &aips1->opacr2);
	116	writel(0x00000000, &aips1->opacr3);
	117	writel(0x00000000, &aips1->opacr4);
	118	writel(0x00000000, &aips2->opacr0);
	119	writel(0x00000000, &aips2->opacr1);
	120	writel(0x00000000, &aips2->opacr2);
	121	writel(0x00000000, &aips2->opacr3);
	122	writel(0x00000000, &aips2->opacr4);
05d54b82 FE	123
	124	#ifdef CONFIG_MX6SX
	125	/*
	126	* Set all MPROTx to be non-bufferable, trusted for R/W,
	127	* not forced to user-mode.
	128	*/
	129	writel(0x77777777, &aips3->mprot0);
	130	writel(0x77777777, &aips3->mprot1);
	131
	132	/*
	133	* Set all OPACRx to be non-bufferable, not require
	134	* supervisor privilege level for access,allow for
	135	* write access and untrusted master access.
	136	*/
	137	writel(0x00000000, &aips3->opacr0);
	138	writel(0x00000000, &aips3->opacr1);
	139	writel(0x00000000, &aips3->opacr2);
	140	writel(0x00000000, &aips3->opacr3);
	141	writel(0x00000000, &aips3->opacr4);
	142	#endif
23608e23 JL	143	}
23608e23 JL	144
e113fd19 FE	145	static void clear_ldo_ramp(void)
	146	{
	147	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
	148	int reg;
	149
	150	/* ROM may modify LDO ramp up time according to fuse setting, so in
	151	* order to be in the safe side we neeed to reset these settings to
	152	* match the reset value: 0'b00
	153	*/
	154	reg = readl(&anatop->ana_misc2);
	155	reg &= ~(0x3f << 24);
	156	writel(reg, &anatop->ana_misc2);
	157	}
	158
cac833a9	159	/*
157f45da	160	* Set the PMU_REG_CORE register
cac833a9	161	*
157f45da	162	* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
cac833a9 DB	163	* Possible values are from 0.725V to 1.450V in steps of
	164	* 0.025V (25mV).
	165	*/
3d622b78	166	static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
cac833a9 DB	167	{
cac833a9 DB	168	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
39f0ac93	169	u32 val, step, old, reg = readl(&anatop->reg_core);
3d622b78	170	u8 shift;
cac833a9 DB	171
	172	if (mv < 725)
	173	val = 0x00; /* Power gated off */
	174	else if (mv > 1450)
	175	val = 0x1F; /* Power FET switched full on. No regulation */
	176	else
	177	val = (mv - 700) / 25;
	178
e113fd19 FE	179	clear_ldo_ramp();
e113fd19 FE	180
3d622b78 FE	181	switch (ldo) {
	182	case LDO_SOC:
	183	shift = 18;
	184	break;
	185	case LDO_PU:
	186	shift = 9;
	187	break;
	188	case LDO_ARM:
	189	shift = 0;
	190	break;
	191	default:
	192	return -EINVAL;
	193	}
	194
39f0ac93 FE	195	old = (reg & (0x1F << shift)) >> shift;
	196	step = abs(val - old);
	197	if (step == 0)
	198	return 0;
	199
3d622b78	200	reg = (reg & ~(0x1F << shift)) \| (val << shift);
cac833a9	201	writel(reg, &anatop->reg_core);
3d622b78	202
39f0ac93 FE	203	/*
	204	* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
	205	* step
	206	*/
	207	udelay(3 * step);
	208
3d622b78	209	return 0;
cac833a9 DB	210	}
cac833a9 DB	211
76c91e66 FE	212	static void imx_set_wdog_powerdown(bool enable)
	213	{
	214	struct wdog_regs wdog1 = (struct wdog_regs )WDOG1_BASE_ADDR;
	215	struct wdog_regs wdog2 = (struct wdog_regs )WDOG2_BASE_ADDR;
	216
	217	/* Write to the PDE (Power Down Enable) bit */
	218	writew(enable, &wdog1->wmcr);
	219	writew(enable, &wdog2->wmcr);
	220	}
	221
5c92edc2 AH	222	static void set_ahb_rate(u32 val)
	223	{
	224	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	225	u32 reg, div;
	226
	227	div = get_periph_clk() / val - 1;
	228	reg = readl(&mxc_ccm->cbcdr);
	229
	230	writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) \|
	231	(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
	232	}
	233
16197bb8 AH	234	static void clear_mmdc_ch_mask(void)
	235	{
	236	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	237
	238	/* Clear MMDC channel mask */
	239	writel(0, &mxc_ccm->ccdr);
	240	}
	241
23608e23 JL	242	int arch_cpu_init(void)
	243	{
	244	init_aips();
	245
16197bb8 AH	246	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
	247	clear_mmdc_ch_mask();
	248
5c92edc2 AH	249	/*
	250	* When low freq boot is enabled, ROM will not set AHB
	251	* freq, so we need to ensure AHB freq is 132MHz in such
	252	* scenario.
	253	*/
	254	if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
	255	set_ahb_rate(132000000);
	256
76c91e66	257	imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
ae695b18 SR	258
	259	#ifdef CONFIG_APBH_DMA
	260	/* Start APBH DMA */
	261	mxs_dma_init();
	262	#endif
	263
23608e23 JL	264	return 0;
23608e23 JL	265	}
23608e23	266
39f0ac93 FE	267	int board_postclk_init(void)
	268	{
	269	set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
	270
	271	return 0;
	272	}
	273
4d422fe2 EN	274	#ifndef CONFIG_SYS_DCACHE_OFF
	275	void enable_caches(void)
	276	{
36c1ca4d NG	277	#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
	278	enum dcache_option option = DCACHE_WRITETHROUGH;
	279	#else
	280	enum dcache_option option = DCACHE_WRITEBACK;
	281	#endif
	282
ebaf6b26 FL	283	/* Avoid random hang when download by usb */
ebaf6b26 FL	284	invalidate_dcache_all();
36c1ca4d	285
4d422fe2 EN	286	/* Enable D-cache. I-cache is already enabled in start.S */
4d422fe2 EN	287	dcache_enable();
36c1ca4d NG	288
	289	/* Enable caching on OCRAM and ROM */
	290	mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
	291	ROMCP_ARB_END_ADDR,
	292	option);
	293	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
	294	IRAM_SIZE,
	295	option);
4d422fe2 EN	296	}
	297	#endif
	298
23608e23	299	#if defined(CONFIG_FEC_MXC)
be252b65	300	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
23608e23	301	{
8f3ff11c BT	302	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
8f3ff11c BT	303	struct fuse_bank *bank = &ocotp->bank[4];
23608e23 JL	304	struct fuse_bank4_regs *fuse =
	305	(struct fuse_bank4_regs *)bank->fuse_regs;
	306
bd2e27c0 JL	307	u32 value = readl(&fuse->mac_addr_high);
	308	mac[0] = (value >> 8);
	309	mac[1] = value ;
23608e23	310
bd2e27c0 JL	311	value = readl(&fuse->mac_addr_low);
	312	mac[2] = value >> 24 ;
	313	mac[3] = value >> 16 ;
	314	mac[4] = value >> 8 ;
	315	mac[5] = value ;
23608e23 JL	316
	317	}
	318	#endif
124a06d7 TK	319
	320	void boot_mode_apply(unsigned cfg_val)
	321	{
	322	unsigned reg;
2af7e810	323	struct src psrc = (struct src )SRC_BASE_ADDR;
124a06d7 TK	324	writel(cfg_val, &psrc->gpr9);
	325	reg = readl(&psrc->gpr10);
	326	if (cfg_val)
	327	reg \|= 1 << 28;
	328	else
	329	reg &= ~(1 << 28);
	330	writel(reg, &psrc->gpr10);
	331	}
	332	/*
	333	* cfg_val will be used for
	334	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
	335	* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
	336	* to SBMR1, which will determine the boot device.
	337	*/
	338	const struct boot_mode soc_boot_modes[] = {
	339	{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
	340	/* reserved value should start rom usb */
	341	{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
	342	{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
2d59e3ec ND	343	{"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
	344	{"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
	345	{"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
	346	{"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
124a06d7 TK	347	/* 4 bit bus width */
	348	{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	349	{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	350	{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	351	{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	352	{NULL, 0},
	353	};
8f393776 SW	354
	355	void s_init(void)
	356	{
8467faef	357	struct anatop_regs anatop = (struct anatop_regs )ANATOP_BASE_ADDR;
9293d7fd	358	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
8467faef EN	359	u32 mask480;
8467faef EN	360	u32 mask528;
9293d7fd	361	u32 reg, periph1, periph2;
a3df99b5 FE	362
	363	if (is_cpu_type(MXC_CPU_MX6SX))
	364	return;
	365
8467faef EN	366	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
	367	* to make sure PFD is working right, otherwise, PFDs may
	368	* not output clock after reset, MX6DL and MX6SL have added 396M pfd
	369	* workaround in ROM code, as bus clock need it
	370	*/
	371
	372	mask480 = ANATOP_PFD_CLKGATE_MASK(0) \|
	373	ANATOP_PFD_CLKGATE_MASK(1) \|
	374	ANATOP_PFD_CLKGATE_MASK(2) \|
	375	ANATOP_PFD_CLKGATE_MASK(3);
9293d7fd	376	mask528 = ANATOP_PFD_CLKGATE_MASK(1) \|
8467faef EN	377	ANATOP_PFD_CLKGATE_MASK(3);
8467faef EN	378
9293d7fd YL	379	reg = readl(&ccm->cbcmr);
	380	periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
	381	>> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
	382	periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
	383	>> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
	384
	385	/* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
	386	if ((periph2 != 0x2) && (periph1 != 0x2))
	387	mask528 \|= ANATOP_PFD_CLKGATE_MASK(0);
	388
	389	if ((periph2 != 0x1) && (periph1 != 0x1) &&
	390	(periph2 != 0x3) && (periph1 != 0x3))
8467faef	391	mask528 \|= ANATOP_PFD_CLKGATE_MASK(2);
9293d7fd	392
8467faef EN	393	writel(mask480, &anatop->pfd_480_set);
	394	writel(mask528, &anatop->pfd_528_set);
	395	writel(mask480, &anatop->pfd_480_clr);
	396	writel(mask528, &anatop->pfd_528_clr);
8f393776	397	}
5ea7f0e3 PKS	398
	399	#ifdef CONFIG_IMX_HDMI
	400	void imx_enable_hdmi_phy(void)
	401	{
	402	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	403	u8 reg;
	404	reg = readb(&hdmi->phy_conf0);
	405	reg \|= HDMI_PHY_CONF0_PDZ_MASK;
	406	writeb(reg, &hdmi->phy_conf0);
	407	udelay(3000);
	408	reg \|= HDMI_PHY_CONF0_ENTMDS_MASK;
	409	writeb(reg, &hdmi->phy_conf0);
	410	udelay(3000);
	411	reg \|= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
	412	writeb(reg, &hdmi->phy_conf0);
	413	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
	414	}
	415
	416	void imx_setup_hdmi(void)
	417	{
	418	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	419	struct hdmi_regs hdmi = (struct hdmi_regs )HDMI_ARB_BASE_ADDR;
	420	int reg;
	421
	422	/* Turn on HDMI PHY clock */
	423	reg = readl(&mxc_ccm->CCGR2);
	424	reg \|= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK\|
	425	MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
	426	writel(reg, &mxc_ccm->CCGR2);
	427	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
	428	reg = readl(&mxc_ccm->chsccdr);
	429	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK\|
	430	MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK\|
	431	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
	432	reg \|= (CHSCCDR_PODF_DIVIDE_BY_3
	433	<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
	434	\|(CHSCCDR_IPU_PRE_CLK_540M_PFD
	435	<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
	436	writel(reg, &mxc_ccm->chsccdr);
	437	}
	438	#endif
6d73c234 FE	439
	440	#ifndef CONFIG_SYS_L2CACHE_OFF
	441	#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
	442	void v7_outer_cache_enable(void)
	443	{
	444	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	445	unsigned int val;
	446
	447	#if defined CONFIG_MX6SL
	448	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	449	val = readl(&iomux->gpr[11]);
	450	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
	451	/* L2 cache configured as OCRAM, reset it */
	452	val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
	453	writel(val, &iomux->gpr[11]);
	454	}
	455	#endif
	456
4aa7ac30 YL	457	/* Must disable the L2 before changing the latency parameters */
	458	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	459
6d73c234 FE	460	writel(0x132, &pl310->pl310_tag_latency_ctrl);
	461	writel(0x132, &pl310->pl310_data_latency_ctrl);
	462
	463	val = readl(&pl310->pl310_prefetch_ctrl);
	464
	465	/* Turn on the L2 I/D prefetch */
	466	val \|= 0x30000000;
	467
	468	/*
	469	* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
	470	* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
	471	* But according to ARM PL310 errata: 752271
	472	* ID: 752271: Double linefill feature can cause data corruption
	473	* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
	474	* Workaround: The only workaround to this erratum is to disable the
	475	* double linefill feature. This is the default behavior.
	476	*/
	477
	478	#ifndef CONFIG_MX6Q
	479	val \|= 0x40800000;
	480	#endif
	481	writel(val, &pl310->pl310_prefetch_ctrl);
	482
	483	val = readl(&pl310->pl310_power_ctrl);
	484	val \|= L2X0_DYNAMIC_CLK_GATING_EN;
	485	val \|= L2X0_STNDBY_MODE_EN;
	486	writel(val, &pl310->pl310_power_ctrl);
	487
	488	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	489	}
	490
	491	void v7_outer_cache_disable(void)
	492	{
	493	struct pl310_regs const pl310 = (struct pl310_regs )L2_PL310_BASE;
	494
	495	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
	496	}
	497	#endif /* !CONFIG_SYS_L2CACHE_OFF */