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Commit | Line | Data |
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8a8f084e CN |
1 | /* |
2 | * boot-common.c | |
3 | * | |
4 | * Common bootmode functions for omap based boards | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
8a8f084e CN |
9 | */ |
10 | ||
11 | #include <common.h> | |
47f7bcae | 12 | #include <spl.h> |
8a8f084e CN |
13 | #include <asm/omap_common.h> |
14 | #include <asm/arch/omap.h> | |
f0881250 | 15 | #include <asm/arch/mmc_host_def.h> |
1befaffb | 16 | #include <asm/arch/sys_proto.h> |
8a8f084e | 17 | |
4a0eb757 | 18 | DECLARE_GLOBAL_DATA_PTR; |
8a8f084e | 19 | |
4596dcc1 TR |
20 | void save_omap_boot_params(void) |
21 | { | |
22 | u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); | |
23 | u8 boot_device; | |
24 | u32 dev_desc, dev_data; | |
25 | ||
26 | if ((rom_params < NON_SECURE_SRAM_START) || | |
27 | (rom_params > NON_SECURE_SRAM_END)) | |
28 | return; | |
29 | ||
30 | /* | |
31 | * rom_params can be type casted to omap_boot_parameters and | |
32 | * used. But it not correct to assume that romcode structure | |
33 | * encoding would be same as u-boot. So use the defined offsets. | |
34 | */ | |
35 | gd->arch.omap_boot_params.omap_bootdevice = boot_device = | |
36 | *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); | |
37 | ||
38 | gd->arch.omap_boot_params.ch_flags = | |
39 | *((u8 *)(rom_params + CH_FLAGS_OFFSET)); | |
40 | ||
41 | if ((boot_device >= MMC_BOOT_DEVICES_START) && | |
42 | (boot_device <= MMC_BOOT_DEVICES_END)) { | |
43 | #if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) | |
44 | if ((omap_hw_init_context() == | |
45 | OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { | |
46 | gd->arch.omap_boot_params.omap_bootmode = | |
47 | *((u8 *)(rom_params + BOOT_MODE_OFFSET)); | |
48 | } else | |
49 | #endif | |
50 | { | |
51 | dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); | |
52 | dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); | |
53 | gd->arch.omap_boot_params.omap_bootmode = | |
54 | *((u32 *)(dev_data + BOOT_MODE_OFFSET)); | |
55 | } | |
56 | } | |
57 | } | |
58 | ||
8a8f084e | 59 | #ifdef CONFIG_SPL_BUILD |
8e1b836e | 60 | u32 spl_boot_device(void) |
8a8f084e | 61 | { |
4a0eb757 | 62 | return (u32) (gd->arch.omap_boot_params.omap_bootdevice); |
8a8f084e CN |
63 | } |
64 | ||
37189a19 | 65 | u32 spl_boot_mode(void) |
8a8f084e | 66 | { |
4a0eb757 | 67 | return gd->arch.omap_boot_params.omap_bootmode; |
8a8f084e | 68 | } |
f0881250 | 69 | |
d7cb93b2 TR |
70 | void spl_board_init(void) |
71 | { | |
72 | #ifdef CONFIG_SPL_NAND_SUPPORT | |
73 | gpmc_init(); | |
74 | #endif | |
da07c21b IY |
75 | #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) |
76 | arch_misc_init(); | |
77 | #endif | |
d7cb93b2 TR |
78 | } |
79 | ||
f0881250 TR |
80 | int board_mmc_init(bd_t *bis) |
81 | { | |
82 | switch (spl_boot_device()) { | |
83 | case BOOT_DEVICE_MMC1: | |
e3913f56 | 84 | omap_mmc_init(0, 0, 0, -1, -1); |
f0881250 TR |
85 | break; |
86 | case BOOT_DEVICE_MMC2: | |
87 | case BOOT_DEVICE_MMC2_2: | |
e3913f56 | 88 | omap_mmc_init(1, 0, 0, -1, -1); |
f0881250 TR |
89 | break; |
90 | } | |
91 | return 0; | |
92 | } | |
4a0eb757 S |
93 | |
94 | void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) | |
95 | { | |
96 | typedef void __noreturn (*image_entry_noargs_t)(u32 *); | |
97 | image_entry_noargs_t image_entry = | |
98 | (image_entry_noargs_t) spl_image->entry_point; | |
99 | ||
100 | debug("image entry point: 0x%X\n", spl_image->entry_point); | |
101 | /* Pass the saved boot_params from rom code */ | |
102 | image_entry((u32 *)&gd->arch.omap_boot_params); | |
103 | } | |
8a8f084e | 104 | #endif |