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Commit | Line | Data |
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d34efc76 SS |
1 | /* |
2 | * | |
508a58fa | 3 | * Common functions for OMAP4/5 based boards |
d34efc76 SS |
4 | * |
5 | * (C) Copyright 2010 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Author : | |
9 | * Aneesh V <aneesh@ti.com> | |
10 | * Steve Sakoman <steve@sakoman.com> | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | #include <common.h> | |
47f7bcae | 31 | #include <spl.h> |
d34efc76 | 32 | #include <asm/arch/sys_proto.h> |
7ca3f9c5 | 33 | #include <asm/sizes.h> |
bb772a59 | 34 | #include <asm/emif.h> |
01b753ff | 35 | #include <asm/omap_common.h> |
d4d986ee | 36 | #include <linux/compiler.h> |
de63ac27 S |
37 | #include <asm/cache.h> |
38 | #include <asm/system.h> | |
39 | ||
40 | #define ARMV7_DCACHE_WRITEBACK 0xe | |
41 | #define ARMV7_DOMAIN_CLIENT 1 | |
42 | #define ARMV7_DOMAIN_MASK (0x3 << 0) | |
d34efc76 | 43 | |
93e3568b NM |
44 | DECLARE_GLOBAL_DATA_PTR; |
45 | ||
469ec1e3 A |
46 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
47 | { | |
48 | int i; | |
49 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; | |
50 | ||
51 | for (i = 0; i < size; i++, pad++) | |
52 | writew(pad->val, base + pad->offset); | |
53 | } | |
54 | ||
469ec1e3 A |
55 | static void set_mux_conf_regs(void) |
56 | { | |
508a58fa | 57 | switch (omap_hw_init_context()) { |
469ec1e3 A |
58 | case OMAP_INIT_CONTEXT_SPL: |
59 | set_muxconf_regs_essential(); | |
60 | break; | |
61 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: | |
78f455c0 | 62 | #ifdef CONFIG_SYS_ENABLE_PADS_ALL |
469ec1e3 | 63 | set_muxconf_regs_non_essential(); |
78f455c0 | 64 | #endif |
469ec1e3 A |
65 | break; |
66 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: | |
67 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: | |
68 | set_muxconf_regs_essential(); | |
78f455c0 | 69 | #ifdef CONFIG_SYS_ENABLE_PADS_ALL |
469ec1e3 | 70 | set_muxconf_regs_non_essential(); |
78f455c0 | 71 | #endif |
469ec1e3 A |
72 | break; |
73 | } | |
74 | } | |
75 | ||
508a58fa | 76 | u32 cortex_rev(void) |
ad577c8a A |
77 | { |
78 | ||
79 | unsigned int rev; | |
80 | ||
81 | /* Read Main ID Register (MIDR) */ | |
82 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); | |
83 | ||
84 | return rev; | |
85 | } | |
86 | ||
761ca31e | 87 | void omap_rev_string(void) |
ad577c8a | 88 | { |
508a58fa | 89 | u32 omap_rev = omap_revision(); |
de62688b | 90 | u32 soc_variant = (omap_rev & 0xF0000000) >> 28; |
508a58fa S |
91 | u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; |
92 | u32 major_rev = (omap_rev & 0x00000F00) >> 8; | |
93 | u32 minor_rev = (omap_rev & 0x000000F0) >> 4; | |
ad577c8a | 94 | |
de62688b LV |
95 | if (soc_variant) |
96 | printf("OMAP"); | |
97 | else | |
98 | printf("DRA"); | |
99 | printf("%x ES%x.%x\n", omap_variant, major_rev, | |
100 | minor_rev); | |
ad577c8a A |
101 | } |
102 | ||
78f455c0 | 103 | #ifdef CONFIG_SPL_BUILD |
861a86f4 TR |
104 | void spl_display_print(void) |
105 | { | |
106 | omap_rev_string(); | |
107 | } | |
78f455c0 S |
108 | #endif |
109 | ||
d4d986ee LV |
110 | void __weak srcomp_enable(void) |
111 | { | |
112 | } | |
113 | ||
fda06812 S |
114 | static void save_omap_boot_params(void) |
115 | { | |
116 | u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); | |
117 | u8 boot_device; | |
118 | u32 dev_desc, dev_data; | |
119 | ||
120 | if ((rom_params < NON_SECURE_SRAM_START) || | |
121 | (rom_params > NON_SECURE_SRAM_END)) | |
122 | return; | |
123 | ||
124 | /* | |
125 | * rom_params can be type casted to omap_boot_parameters and | |
126 | * used. But it not correct to assume that romcode structure | |
127 | * encoding would be same as u-boot. So use the defined offsets. | |
128 | */ | |
129 | gd->arch.omap_boot_params.omap_bootdevice = boot_device = | |
130 | *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); | |
131 | ||
132 | gd->arch.omap_boot_params.ch_flags = | |
133 | *((u8 *)(rom_params + CH_FLAGS_OFFSET)); | |
134 | ||
135 | if ((boot_device >= MMC_BOOT_DEVICES_START) && | |
136 | (boot_device <= MMC_BOOT_DEVICES_END)) { | |
137 | if ((omap_hw_init_context() == | |
138 | OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { | |
139 | gd->arch.omap_boot_params.omap_bootmode = | |
140 | *((u8 *)(rom_params + BOOT_MODE_OFFSET)); | |
141 | } else { | |
142 | dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); | |
143 | dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); | |
144 | gd->arch.omap_boot_params.omap_bootmode = | |
145 | *((u32 *)(dev_data + BOOT_MODE_OFFSET)); | |
146 | } | |
147 | } | |
148 | } | |
149 | ||
47c6ea07 S |
150 | #ifdef CONFIG_ARCH_CPU_INIT |
151 | /* | |
152 | * SOC specific cpu init | |
153 | */ | |
154 | int arch_cpu_init(void) | |
155 | { | |
156 | save_omap_boot_params(); | |
157 | return 0; | |
158 | } | |
159 | #endif /* CONFIG_ARCH_CPU_INIT */ | |
160 | ||
d34efc76 SS |
161 | /* |
162 | * Routine: s_init | |
469ec1e3 A |
163 | * Description: Does early system init of watchdog, muxing, andclocks |
164 | * Watchdog disable is done always. For the rest what gets done | |
165 | * depends on the boot mode in which this function is executed | |
166 | * 1. s_init of SPL running from SRAM | |
167 | * 2. s_init of U-Boot running from FLASH | |
168 | * 3. s_init of U-Boot loaded to SDRAM by SPL | |
169 | * 4. s_init of U-Boot loaded to SDRAM by ROM code using the | |
170 | * Configuration Header feature | |
171 | * Please have a look at the respective functions to see what gets | |
172 | * done in each of these cases | |
173 | * This function is called with SRAM stack. | |
d34efc76 SS |
174 | */ |
175 | void s_init(void) | |
176 | { | |
fda06812 S |
177 | /* |
178 | * Save the boot parameters passed from romcode. | |
179 | * We cannot delay the saving further than this, | |
180 | * to prevent overwrites. | |
181 | */ | |
182 | #ifdef CONFIG_SPL_BUILD | |
183 | save_omap_boot_params(); | |
184 | #endif | |
508a58fa | 185 | init_omap_revision(); |
01b753ff S |
186 | hw_data_init(); |
187 | ||
38f25b12 LV |
188 | #ifdef CONFIG_SPL_BUILD |
189 | if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) | |
190 | force_emif_self_refresh(); | |
191 | #endif | |
d34efc76 | 192 | watchdog_init(); |
469ec1e3 | 193 | set_mux_conf_regs(); |
bcae7211 | 194 | #ifdef CONFIG_SPL_BUILD |
d4d986ee | 195 | srcomp_enable(); |
63ffcfcb | 196 | setup_clocks_for_console(); |
6507f133 TR |
197 | |
198 | gd = &gdata; | |
199 | ||
bcae7211 | 200 | preloader_console_init(); |
4ecfcfaa | 201 | do_io_settings(); |
bcae7211 | 202 | #endif |
3776801d | 203 | prcm_init(); |
bcae7211 | 204 | #ifdef CONFIG_SPL_BUILD |
f5902179 DN |
205 | timer_init(); |
206 | ||
bcae7211 A |
207 | /* For regular u-boot sdram_init() is called from dram_init() */ |
208 | sdram_init(); | |
209 | #endif | |
d34efc76 SS |
210 | } |
211 | ||
212 | /* | |
213 | * Routine: wait_for_command_complete | |
214 | * Description: Wait for posting to finish on watchdog | |
215 | */ | |
216 | void wait_for_command_complete(struct watchdog *wd_base) | |
217 | { | |
218 | int pending = 1; | |
219 | do { | |
220 | pending = readl(&wd_base->wwps); | |
221 | } while (pending); | |
222 | } | |
223 | ||
224 | /* | |
225 | * Routine: watchdog_init | |
226 | * Description: Shut down watch dogs | |
227 | */ | |
228 | void watchdog_init(void) | |
229 | { | |
230 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; | |
231 | ||
232 | writel(WD_UNLOCK1, &wd2_base->wspr); | |
233 | wait_for_command_complete(wd2_base); | |
234 | writel(WD_UNLOCK2, &wd2_base->wspr); | |
235 | } | |
236 | ||
7ca3f9c5 A |
237 | |
238 | /* | |
239 | * This function finds the SDRAM size available in the system | |
240 | * based on DMM section configurations | |
241 | * This is needed because the size of memory installed may be | |
242 | * different on different versions of the board | |
243 | */ | |
508a58fa | 244 | u32 omap_sdram_size(void) |
7ca3f9c5 | 245 | { |
e06e914d S |
246 | u32 section, i, valid; |
247 | u64 sdram_start = 0, sdram_end = 0, addr, | |
248 | size, total_size = 0, trap_size = 0; | |
bb772a59 | 249 | |
7ca3f9c5 | 250 | for (i = 0; i < 4; i++) { |
bb772a59 | 251 | section = __raw_readl(DMM_BASE + i*4); |
e06e914d S |
252 | valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> |
253 | (EMIF_SDRC_ADDRSPC_SHIFT); | |
bb772a59 | 254 | addr = section & EMIF_SYS_ADDR_MASK; |
e06e914d | 255 | |
7ca3f9c5 | 256 | /* See if the address is valid */ |
bb772a59 S |
257 | if ((addr >= DRAM_ADDR_SPACE_START) && |
258 | (addr < DRAM_ADDR_SPACE_END)) { | |
259 | size = ((section & EMIF_SYS_SIZE_MASK) >> | |
260 | EMIF_SYS_SIZE_SHIFT); | |
261 | size = 1 << size; | |
262 | size *= SZ_16M; | |
e06e914d S |
263 | |
264 | if (valid != DMM_SDRC_ADDR_SPC_INVALID) { | |
265 | if (!sdram_start || (addr < sdram_start)) | |
266 | sdram_start = addr; | |
267 | if (!sdram_end || ((addr + size) > sdram_end)) | |
268 | sdram_end = addr + size; | |
269 | } else { | |
270 | trap_size = size; | |
271 | } | |
272 | ||
7ca3f9c5 | 273 | } |
e06e914d | 274 | |
7ca3f9c5 | 275 | } |
e06e914d | 276 | total_size = (sdram_end - sdram_start) - (trap_size); |
bb772a59 | 277 | |
7ca3f9c5 A |
278 | return total_size; |
279 | } | |
280 | ||
281 | ||
d34efc76 SS |
282 | /* |
283 | * Routine: dram_init | |
284 | * Description: sets uboots idea of sdram size | |
285 | */ | |
286 | int dram_init(void) | |
287 | { | |
2ae610f0 | 288 | sdram_init(); |
508a58fa | 289 | gd->ram_size = omap_sdram_size(); |
d34efc76 SS |
290 | return 0; |
291 | } | |
292 | ||
293 | /* | |
294 | * Print board information | |
295 | */ | |
296 | int checkboard(void) | |
297 | { | |
298 | puts(sysinfo.board_string); | |
299 | return 0; | |
300 | } | |
301 | ||
508a58fa S |
302 | /* |
303 | * get_device_type(): tell if GP/HS/EMU/TST | |
304 | */ | |
305 | u32 get_device_type(void) | |
8b457fa8 | 306 | { |
c43c8339 | 307 | return (readl((*ctrl)->control_status) & |
c1fa3c37 | 308 | (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; |
8b457fa8 A |
309 | } |
310 | ||
508a58fa S |
311 | /* |
312 | * Print CPU information | |
313 | */ | |
314 | int print_cpuinfo(void) | |
8b457fa8 | 315 | { |
761ca31e AM |
316 | puts("CPU : "); |
317 | omap_rev_string(); | |
13d4f9bd | 318 | |
508a58fa S |
319 | return 0; |
320 | } | |
13d4f9bd A |
321 | #ifndef CONFIG_SYS_DCACHE_OFF |
322 | void enable_caches(void) | |
323 | { | |
324 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
325 | dcache_enable(); | |
326 | } | |
de63ac27 S |
327 | |
328 | void dram_bank_mmu_setup(int bank) | |
329 | { | |
330 | bd_t *bd = gd->bd; | |
331 | int i; | |
332 | ||
333 | u32 start = bd->bi_dram[bank].start >> 20; | |
334 | u32 size = bd->bi_dram[bank].size >> 20; | |
335 | u32 end = start + size; | |
336 | ||
337 | debug("%s: bank: %d\n", __func__, bank); | |
338 | for (i = start; i < end; i++) | |
339 | set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); | |
340 | ||
341 | } | |
342 | ||
343 | void arm_init_domains(void) | |
344 | { | |
345 | u32 reg; | |
346 | ||
347 | reg = get_dacr(); | |
348 | /* | |
349 | * Set DOMAIN to client access so that all permissions | |
350 | * set in pagetables are validated by the mmu. | |
351 | */ | |
352 | reg &= ~ARMV7_DOMAIN_MASK; | |
353 | reg |= ARMV7_DOMAIN_CLIENT; | |
354 | set_dacr(reg); | |
355 | } | |
13d4f9bd | 356 | #endif |