[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap3_boot_device = BOOT_DEVICE_NAND;

/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 spl_boot_mode(void)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC2:
		return MMCSD_MODE_RAW;
	case BOOT_DEVICE_MMC1:
		return MMCSD_MODE_FAT;
		break;
	default:
		puts("spl: ERROR:  unknown device - can't select boot mode\n");
		hang();
	}
}

u32 spl_boot_device(void)
{
	return omap3_boot_device;
}

int board_mmc_init(bd_t *bis)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC1:
		omap_mmc_init(0, 0, 0, -1, -1);
		break;
	case BOOT_DEVICE_MMC2:
	case BOOT_DEVICE_MMC2_2:
		omap_mmc_init(1, 0, 0, -1, -1);
		break;
	}
	return 0;
}

void spl_board_init(void)
{
#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
	gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
#endif /* CONFIG_SPL_BUILD */


/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/* Errata workarounds */
	omap3_setup_aux_cr();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif

#ifdef CONFIG_SPL_BUILD
	gd = &gdata;

	preloader_console_init();

	timer_init();
#endif

	if (!in_sdram)
		mem_init();
}

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	dieid_num_r();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	if (argc < 2 || argc > 3)
		goto usage;

	if (strncmp(argv[1], "hw", 2) == 0) {
		if (argc == 2) {
			omap_nand_switch_ecc(1, 1);
		} else {
			if (strncmp(argv[2], "hamming", 7) == 0)
				omap_nand_switch_ecc(1, 1);
			else if (strncmp(argv[2], "bch8", 4) == 0)
				omap_nand_switch_ecc(1, 8);
			else
				goto usage;
		}
	} else if (strncmp(argv[1], "sw", 2) == 0) {
		omap_nand_switch_ecc(0, 0);
	} else {
		goto usage;
	}

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 3, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
	" 8-bit BCH\n"
	"                           ecc calculation (second parameter may"
	" be omitted).\n"
	"nandecc sw               - Switch to NAND software ecc algorithm."
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
				       acr);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = acr;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
				       (u32 *)&emu_romcode_params);
	}
}

static void omap3_setup_aux_cr(void)
{
	/* Workaround for Cortex-A8 errata: #454179 #430973
	 *	Set "IBE" bit
	 *	Set "Disable Branch Size Mispredicts" bit
	 * Workaround for erratum #621766
	 *	Enable L1NEON bit
	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
	 */
	omap3_update_aux_cr_secure(0xE0, 0);
}

#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	/* Write ACR - affects non-secure banked bits */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
				      0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{
	/* Set L2EN */
	omap3_update_aux_cr_secure(0x2, 0);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/* Clear L2EN */
	omap3_update_aux_cr_secure(0, 0x2);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif /* !CONFIG_SYS_DCACHE_OFF */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
1a459660	17	* SPDX-License-Identifier: GPL-2.0+
91eee546 DB	18	*/
91eee546 DB	19	#include <common.h>
47f7bcae	20	#include <spl.h>
91eee546 DB	21	#include <asm/io.h>
	22	#include <asm/arch/sys_proto.h>
	23	#include <asm/arch/mem.h>
06e758e7	24	#include <asm/cache.h>
45bf0585	25	#include <asm/armv7.h>
080a46ea	26	#include <asm/arch/gpio.h>
bb085b87	27	#include <asm/omap_common.h>
f0881250	28	#include <asm/arch/mmc_host_def.h>
ee08a826	29	#include <i2c.h>
8a87a3d7	30	#include <linux/compiler.h>
91eee546	31
6507f133 TR	32	DECLARE_GLOBAL_DATA_PTR;
6507f133 TR	33
45bf0585	34	/* Declarations */
91eee546	35	extern omap3_sysinfo sysinfo;
45bf0585	36	static void omap3_setup_aux_cr(void);
57f588be	37	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	38	static void omap3_invalidate_l2_cache_secure(void);
57f588be	39	#endif
91eee546	40
25223a68 A	41	static const struct gpio_bank gpio_bank_34xx[6] = {
	42	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	43	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	44	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	45	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	46	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	47	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
	48	};
	49
	50	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	51
bb085b87 SS	52	#ifdef CONFIG_SPL_BUILD
	53	/*
	54	* We use static variables because global data is not ready yet.
	55	* Initialized data is available in SPL right from the beginning.
	56	* We would not typically need to save these parameters in regular
	57	* U-Boot. This is needed only in SPL at the moment.
	58	*/
	59	u32 omap3_boot_device = BOOT_DEVICE_NAND;
	60
	61	/* auto boot mode detection is not possible for OMAP3 - hard code */
37189a19	62	u32 spl_boot_mode(void)
bb085b87	63	{
8e1b836e	64	switch (spl_boot_device()) {
bb085b87 SS	65	case BOOT_DEVICE_MMC2:
	66	return MMCSD_MODE_RAW;
	67	case BOOT_DEVICE_MMC1:
	68	return MMCSD_MODE_FAT;
	69	break;
bb085b87 SS	70	default:
	71	puts("spl: ERROR: unknown device - can't select boot mode\n");
	72	hang();
	73	}
	74	}
	75
8e1b836e	76	u32 spl_boot_device(void)
bb085b87 SS	77	{
	78	return omap3_boot_device;
	79	}
	80
f0881250 TR	81	int board_mmc_init(bd_t *bis)
	82	{
	83	switch (spl_boot_device()) {
	84	case BOOT_DEVICE_MMC1:
e3913f56	85	omap_mmc_init(0, 0, 0, -1, -1);
f0881250 TR	86	break;
	87	case BOOT_DEVICE_MMC2:
	88	case BOOT_DEVICE_MMC2_2:
e3913f56	89	omap_mmc_init(1, 0, 0, -1, -1);
f0881250 TR	90	break;
	91	}
	92	return 0;
	93	}
	94
ee08a826 TR	95	void spl_board_init(void)
ee08a826 TR	96	{
b51a5e3a	97	#if defined(CONFIG_SPL_NAND_SUPPORT) \|\| defined(CONFIG_SPL_ONENAND_SUPPORT)
d7cb93b2 TR	98	gpmc_init();
d7cb93b2 TR	99	#endif
da521387	100	#ifdef CONFIG_SPL_I2C_SUPPORT
ee08a826	101	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
da521387	102	#endif
ee08a826	103	}
bb085b87 SS	104	#endif /* CONFIG_SPL_BUILD */
	105
	106
91eee546 DB	107	/******************************************************************************
	108	* Routine: secure_unlock
	109	* Description: Setup security registers for access
	110	* (GP Device only)
	111	*****************************************************************************/
	112	void secure_unlock_mem(void)
	113	{
97a099ea DB	114	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	115	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	116	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	117	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	118	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	119
	120	/* Protection Module Register Target APE (PM_RT) */
	121	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	122	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	123	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	124	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	125
	126	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	127	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	128	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	129
	130	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	131	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	132	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	133	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	134
	135	/* IVA Changes */
	136	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	137	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	138	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	139
	140	/* SDRC region 0 public */
	141	writel(UNLOCK_1, &sms_base->rg_att0);
	142	}
	143
	144	/******************************************************************************
	145	* Routine: secureworld_exit()
	146	* Description: If chip is EMU and boot type is external
	147	* configure secure registers and exit secure world
	148	* general use.
	149	*****************************************************************************/
	150	void secureworld_exit()
	151	{
	152	unsigned long i;
	153
a4958313	154	/* configure non-secure access control register */
91eee546 DB	155	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	156	/* enabling co-processor CP10 and CP11 accesses in NS world */
	157	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	158	/*
	159	* allow allocation of locked TLBs and L2 lines in NS world
	160	* allow use of PLE registers in NS world also
	161	*/
	162	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	163	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	164
	165	/* Enable ASA in ACR register */
	166	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	167	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	168	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	169
	170	/* Exiting secure world */
	171	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	172	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	173	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	174	}
	175
91eee546 DB	176	/******************************************************************************
	177	* Routine: try_unlock_sram()
	178	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	179	* general use.
	180	*****************************************************************************/
	181	void try_unlock_memory()
	182	{
	183	int mode;
	184	int in_sdram = is_running_in_sdram();
	185
	186	/*
	187	* if GP device unlock device SRAM for general use
	188	* secure code breaks for Secure/Emulation device - HS/E/T
	189	*/
	190	mode = get_device_type();
	191	if (mode == GP_DEVICE)
	192	secure_unlock_mem();
	193
	194	/*
	195	* If device is EMU and boot is XIP external booting
	196	* Unlock firewalls and disable L2 and put chip
	197	* out of secure world
	198	*
	199	* Assuming memories are unlocked by the demon who put us in SDRAM
	200	*/
	201	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	202	&& (!in_sdram)) {
	203	secure_unlock_mem();
	204	secureworld_exit();
	205	}
	206
	207	return;
	208	}
	209
	210	/******************************************************************************
	211	* Routine: s_init
	212	* Description: Does early system init of muxing and clocks.
	213	* - Called path is with SRAM stack.
	214	*****************************************************************************/
	215	void s_init(void)
	216	{
	217	int in_sdram = is_running_in_sdram();
	218
	219	watchdog_init();
	220
	221	try_unlock_memory();
	222
45bf0585 A	223	/* Errata workarounds */
45bf0585 A	224	omap3_setup_aux_cr();
91eee546	225
45bf0585 A	226	#ifndef CONFIG_SYS_L2CACHE_OFF
	227	/* Invalidate L2-cache from secure mode */
	228	omap3_invalidate_l2_cache_secure();
91eee546	229	#endif
91eee546 DB	230
91eee546 DB	231	set_muxconf_regs();
86623add	232	sdelay(100);
91eee546 DB	233
	234	prcm_init();
	235
	236	per_clocks_enable();
	237
95f87910 G	238	#ifdef CONFIG_USB_EHCI_OMAP
	239	ehci_clocks_enable();
	240	#endif
	241
bb085b87	242	#ifdef CONFIG_SPL_BUILD
6507f133 TR	243	gd = &gdata;
6507f133 TR	244
bb085b87	245	preloader_console_init();
8775471b AM	246
8775471b AM	247	timer_init();
bb085b87 SS	248	#endif
bb085b87 SS	249
91eee546	250	if (!in_sdram)
cae377b5	251	mem_init();
91eee546 DB	252	}
91eee546 DB	253
8a87a3d7 TR	254	/*
	255	* Routine: misc_init_r
	256	* Description: A basic misc_init_r that just displays the die ID
	257	*/
	258	int __weak misc_init_r(void)
	259	{
	260	dieid_num_r();
	261
	262	return 0;
	263	}
	264
91eee546 DB	265	/******************************************************************************
	266	* Routine: wait_for_command_complete
	267	* Description: Wait for posting to finish on watchdog
	268	*****************************************************************************/
97a099ea	269	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	270	{
	271	int pending = 1;
	272	do {
	273	pending = readl(&wd_base->wwps);
	274	} while (pending);
	275	}
	276
	277	/******************************************************************************
	278	* Routine: watchdog_init
	279	* Description: Shut down watch dogs
	280	*****************************************************************************/
	281	void watchdog_init(void)
	282	{
97a099ea DB	283	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	284	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	285
	286	/*
	287	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	288	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	289	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	290	* should not be running and does not generate a PRCM reset.
	291	*/
	292
	293	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	294	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	295	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	296
	297	writel(WD_UNLOCK1, &wd2_base->wspr);
	298	wait_for_command_complete(wd2_base);
	299	writel(WD_UNLOCK2, &wd2_base->wspr);
	300	}
	301
91eee546 DB	302	/******************************************************************************
	303	* Dummy function to handle errors for EABI incompatibility
	304	*****************************************************************************/
	305	void abort(void)
	306	{
	307	}
	308
bb085b87	309	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	310	/******************************************************************************
	311	* OMAP3 specific command to switch between NAND HW and SW ecc
	312	*****************************************************************************/
54841ab5	313	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546	314	{
da634ae3	315	if (argc < 2 \|\| argc > 3)
91eee546	316	goto usage;
da634ae3 AB	317
	318	if (strncmp(argv[1], "hw", 2) == 0) {
	319	if (argc == 2) {
	320	omap_nand_switch_ecc(1, 1);
	321	} else {
	322	if (strncmp(argv[2], "hamming", 7) == 0)
	323	omap_nand_switch_ecc(1, 1);
	324	else if (strncmp(argv[2], "bch8", 4) == 0)
	325	omap_nand_switch_ecc(1, 8);
	326	else
	327	goto usage;
	328	}
	329	} else if (strncmp(argv[1], "sw", 2) == 0) {
	330	omap_nand_switch_ecc(0, 0);
	331	} else {
91eee546	332	goto usage;
da634ae3	333	}
91eee546 DB	334
	335	return 0;
	336
	337	usage:
36003268	338	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	339	return 1;
	340	}
	341
	342	U_BOOT_CMD(
da634ae3	343	nandecc, 3, 1, do_switch_ecc,
a93c92cd	344	"switch OMAP3 NAND ECC calculation algorithm",
da634ae3 AB	345	"hw [hamming\|bch8] - Switch between NAND hardware 1-bit hamming and"
	346	" 8-bit BCH\n"
	347	" ecc calculation (second parameter may"
	348	" be omitted).\n"
	349	"nandecc sw - Switch to NAND software ecc algorithm."
a89c33db	350	);
91eee546	351
bb085b87	352	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	353
	354	#ifdef CONFIG_DISPLAY_BOARDINFO
	355	/**
	356	* Print board information
	357	*/
	358	int checkboard (void)
	359	{
	360	char *mem_s ;
	361
	362	if (is_mem_sdr())
	363	mem_s = "mSDR";
	364	else
	365	mem_s = "LPDDR";
	366
	367	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	368	sysinfo.nand_string);
	369
	370	return 0;
	371	}
	372	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	373
	374	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	375	{
	376	u32 i, num_params = *parameters;
	377	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	378
	379	/*
	380	* copy the parameters to an un-cached area to avoid coherency
	381	* issues
	382	*/
	383	for (i = 0; i < num_params; i++) {
	384	__raw_writel(*parameters, sram_scratch_space);
	385	parameters++;
	386	sram_scratch_space++;
	387	}
	388
	389	/* Now make the PPA call */
	390	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	391	}
	392
	393	static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
	394	{
	395	u32 acr;
	396
	397	/* Read ACR */
	398	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	399	acr &= ~clear_bits;
	400	acr \|= set_bits;
	401
	402	if (get_device_type() == GP_DEVICE) {
	403	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
	404	acr);
	405	} else {
	406	struct emu_hal_params emu_romcode_params;
	407	emu_romcode_params.num_params = 1;
	408	emu_romcode_params.param1 = acr;
	409	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	410	(u32 *)&emu_romcode_params);
	411	}
	412	}
	413
45bf0585 A	414	static void omap3_setup_aux_cr(void)
	415	{
	416	/* Workaround for Cortex-A8 errata: #454179 #430973
	417	* Set "IBE" bit
a4958313	418	* Set "Disable Branch Size Mispredicts" bit
45bf0585 A	419	* Workaround for erratum #621766
	420	* Enable L1NEON bit
	421	* ACR \|= (IBE \| DBSM \| L1NEON) => ACR \|= 0xE0
	422	*/
	423	omap3_update_aux_cr_secure(0xE0, 0);
	424	}
	425
	426	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	427	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	428	{
	429	u32 acr;
	430
	431	/* Read ACR */
	432	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	433	acr &= ~clear_bits;
	434	acr \|= set_bits;
	435
	436	/* Write ACR - affects non-secure banked bits */
	437	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
	438	}
	439
45bf0585 A	440	/* Invalidate the entire L2 cache from secure mode */
	441	static void omap3_invalidate_l2_cache_secure(void)
	442	{
	443	if (get_device_type() == GP_DEVICE) {
	444	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
	445	0);
	446	} else {
	447	struct emu_hal_params emu_romcode_params;
	448	emu_romcode_params.num_params = 1;
	449	emu_romcode_params.param1 = 0;
	450	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	451	(u32 *)&emu_romcode_params);
	452	}
	453	}
	454
	455	void v7_outer_cache_enable(void)
	456	{
	457	/* Set L2EN */
	458	omap3_update_aux_cr_secure(0x2, 0);
	459
	460	/*
	461	* On some revisions L2EN bit is banked on some revisions it's not
	462	* No harm in setting both banked bits(in fact this is required
	463	* by an erratum)
	464	*/
	465	omap3_update_aux_cr(0x2, 0);
	466	}
	467
f1f2c3ca	468	void omap3_outer_cache_disable(void)
45bf0585 A	469	{
	470	/* Clear L2EN */
	471	omap3_update_aux_cr_secure(0, 0x2);
	472
	473	/*
	474	* On some revisions L2EN bit is banked on some revisions it's not
	475	* No harm in clearing both banked bits(in fact this is required
	476	* by an erratum)
	477	*/
	478	omap3_update_aux_cr(0, 0x2);
	479	}
e3fe6257	480	#endif /* !CONFIG_SYS_L2CACHE_OFF */
13d4f9bd A	481
	482	#ifndef CONFIG_SYS_DCACHE_OFF
	483	void enable_caches(void)
	484	{
	485	/* Enable D-cache. I-cache is already enabled in start.S */
	486	dcache_enable();
	487	}
e3fe6257	488	#endif /* !CONFIG_SYS_DCACHE_OFF */