[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/spl.h>
#include <asm/omap_common.h>
#include <i2c.h>
#include <linux/compiler.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
static void omap3_invalidate_l2_cache_secure(void);

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap3_boot_device = BOOT_DEVICE_NAND;

/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 spl_boot_mode(void)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC2:
		return MMCSD_MODE_RAW;
	case BOOT_DEVICE_MMC1:
		return MMCSD_MODE_FAT;
		break;
	default:
		puts("spl: ERROR:  unknown device - can't select boot mode\n");
		hang();
	}
}

u32 spl_boot_device(void)
{
	return omap3_boot_device;
}

void spl_board_init(void)
{
#ifdef CONFIG_SPL_I2C_SUPPORT
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
#endif /* CONFIG_SPL_BUILD */


/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/* Errata workarounds */
	omap3_setup_aux_cr();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif

#ifdef CONFIG_SPL_BUILD
	preloader_console_init();

	timer_init();
#endif

	if (!in_sdram)
		mem_init();
}

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	dieid_num_r();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
				       acr);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = acr;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
				       (u32 *)&emu_romcode_params);
	}
}

static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	/* Write ACR - affects non-secure banked bits */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}

static void omap3_setup_aux_cr(void)
{
	/* Workaround for Cortex-A8 errata: #454179 #430973
	 *	Set "IBE" bit
	 *	Set "Disable Branch Size Mispredicts" bit
	 * Workaround for erratum #621766
	 *	Enable L1NEON bit
	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
	 */
	omap3_update_aux_cr_secure(0xE0, 0);
}

#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
				      0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{
	/* Set L2EN */
	omap3_update_aux_cr_secure(0x2, 0);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/* Clear L2EN */
	omap3_update_aux_cr_secure(0, 0x2);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
06e758e7	39	#include <asm/cache.h>
45bf0585	40	#include <asm/armv7.h>
080a46ea	41	#include <asm/arch/gpio.h>
55cdbb8d	42	#include <asm/spl.h>
bb085b87	43	#include <asm/omap_common.h>
ee08a826	44	#include <i2c.h>
8a87a3d7	45	#include <linux/compiler.h>
91eee546	46
45bf0585	47	/* Declarations */
91eee546	48	extern omap3_sysinfo sysinfo;
45bf0585 A	49	static void omap3_setup_aux_cr(void);
45bf0585 A	50	static void omap3_invalidate_l2_cache_secure(void);
91eee546	51
25223a68 A	52	static const struct gpio_bank gpio_bank_34xx[6] = {
	53	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	54	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	55	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	56	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	57	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	58	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
	59	};
	60
	61	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	62
bb085b87 SS	63	#ifdef CONFIG_SPL_BUILD
	64	/*
	65	* We use static variables because global data is not ready yet.
	66	* Initialized data is available in SPL right from the beginning.
	67	* We would not typically need to save these parameters in regular
	68	* U-Boot. This is needed only in SPL at the moment.
	69	*/
	70	u32 omap3_boot_device = BOOT_DEVICE_NAND;
	71
	72	/* auto boot mode detection is not possible for OMAP3 - hard code */
37189a19	73	u32 spl_boot_mode(void)
bb085b87	74	{
8e1b836e	75	switch (spl_boot_device()) {
bb085b87 SS	76	case BOOT_DEVICE_MMC2:
	77	return MMCSD_MODE_RAW;
	78	case BOOT_DEVICE_MMC1:
	79	return MMCSD_MODE_FAT;
	80	break;
bb085b87 SS	81	default:
	82	puts("spl: ERROR: unknown device - can't select boot mode\n");
	83	hang();
	84	}
	85	}
	86
8e1b836e	87	u32 spl_boot_device(void)
bb085b87 SS	88	{
	89	return omap3_boot_device;
	90	}
	91
ee08a826 TR	92	void spl_board_init(void)
ee08a826 TR	93	{
da521387	94	#ifdef CONFIG_SPL_I2C_SUPPORT
ee08a826	95	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
da521387	96	#endif
ee08a826	97	}
bb085b87 SS	98	#endif /* CONFIG_SPL_BUILD */
	99
	100
91eee546 DB	101	/******************************************************************************
	102	* Routine: secure_unlock
	103	* Description: Setup security registers for access
	104	* (GP Device only)
	105	*****************************************************************************/
	106	void secure_unlock_mem(void)
	107	{
97a099ea DB	108	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	109	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	110	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	111	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	112	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	113
	114	/* Protection Module Register Target APE (PM_RT) */
	115	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	116	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	117	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	118	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	119
	120	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	121	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	122	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	123
	124	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	125	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	126	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	127	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	128
	129	/* IVA Changes */
	130	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	131	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	132	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	133
	134	/* SDRC region 0 public */
	135	writel(UNLOCK_1, &sms_base->rg_att0);
	136	}
	137
	138	/******************************************************************************
	139	* Routine: secureworld_exit()
	140	* Description: If chip is EMU and boot type is external
	141	* configure secure registers and exit secure world
	142	* general use.
	143	*****************************************************************************/
	144	void secureworld_exit()
	145	{
	146	unsigned long i;
	147
a4958313	148	/* configure non-secure access control register */
91eee546 DB	149	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	150	/* enabling co-processor CP10 and CP11 accesses in NS world */
	151	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	152	/*
	153	* allow allocation of locked TLBs and L2 lines in NS world
	154	* allow use of PLE registers in NS world also
	155	*/
	156	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	157	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	158
	159	/* Enable ASA in ACR register */
	160	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	161	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	162	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	163
	164	/* Exiting secure world */
	165	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	166	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	167	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	168	}
	169
91eee546 DB	170	/******************************************************************************
	171	* Routine: try_unlock_sram()
	172	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	173	* general use.
	174	*****************************************************************************/
	175	void try_unlock_memory()
	176	{
	177	int mode;
	178	int in_sdram = is_running_in_sdram();
	179
	180	/*
	181	* if GP device unlock device SRAM for general use
	182	* secure code breaks for Secure/Emulation device - HS/E/T
	183	*/
	184	mode = get_device_type();
	185	if (mode == GP_DEVICE)
	186	secure_unlock_mem();
	187
	188	/*
	189	* If device is EMU and boot is XIP external booting
	190	* Unlock firewalls and disable L2 and put chip
	191	* out of secure world
	192	*
	193	* Assuming memories are unlocked by the demon who put us in SDRAM
	194	*/
	195	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	196	&& (!in_sdram)) {
	197	secure_unlock_mem();
	198	secureworld_exit();
	199	}
	200
	201	return;
	202	}
	203
	204	/******************************************************************************
	205	* Routine: s_init
	206	* Description: Does early system init of muxing and clocks.
	207	* - Called path is with SRAM stack.
	208	*****************************************************************************/
	209	void s_init(void)
	210	{
	211	int in_sdram = is_running_in_sdram();
	212
	213	watchdog_init();
	214
	215	try_unlock_memory();
	216
45bf0585 A	217	/* Errata workarounds */
45bf0585 A	218	omap3_setup_aux_cr();
91eee546	219
45bf0585 A	220	#ifndef CONFIG_SYS_L2CACHE_OFF
	221	/* Invalidate L2-cache from secure mode */
	222	omap3_invalidate_l2_cache_secure();
91eee546	223	#endif
91eee546 DB	224
91eee546 DB	225	set_muxconf_regs();
86623add	226	sdelay(100);
91eee546 DB	227
	228	prcm_init();
	229
	230	per_clocks_enable();
	231
95f87910 G	232	#ifdef CONFIG_USB_EHCI_OMAP
	233	ehci_clocks_enable();
	234	#endif
	235
bb085b87 SS	236	#ifdef CONFIG_SPL_BUILD
bb085b87 SS	237	preloader_console_init();
8775471b AM	238
8775471b AM	239	timer_init();
bb085b87 SS	240	#endif
bb085b87 SS	241
91eee546	242	if (!in_sdram)
cae377b5	243	mem_init();
91eee546 DB	244	}
91eee546 DB	245
8a87a3d7 TR	246	/*
	247	* Routine: misc_init_r
	248	* Description: A basic misc_init_r that just displays the die ID
	249	*/
	250	int __weak misc_init_r(void)
	251	{
	252	dieid_num_r();
	253
	254	return 0;
	255	}
	256
91eee546 DB	257	/******************************************************************************
	258	* Routine: wait_for_command_complete
	259	* Description: Wait for posting to finish on watchdog
	260	*****************************************************************************/
97a099ea	261	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	262	{
	263	int pending = 1;
	264	do {
	265	pending = readl(&wd_base->wwps);
	266	} while (pending);
	267	}
	268
	269	/******************************************************************************
	270	* Routine: watchdog_init
	271	* Description: Shut down watch dogs
	272	*****************************************************************************/
	273	void watchdog_init(void)
	274	{
97a099ea DB	275	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	276	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	277
	278	/*
	279	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	280	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	281	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	282	* should not be running and does not generate a PRCM reset.
	283	*/
	284
	285	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	286	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	287	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	288
	289	writel(WD_UNLOCK1, &wd2_base->wspr);
	290	wait_for_command_complete(wd2_base);
	291	writel(WD_UNLOCK2, &wd2_base->wspr);
	292	}
	293
91eee546 DB	294	/******************************************************************************
	295	* Dummy function to handle errors for EABI incompatibility
	296	*****************************************************************************/
	297	void abort(void)
	298	{
	299	}
	300
bb085b87	301	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	302	/******************************************************************************
	303	* OMAP3 specific command to switch between NAND HW and SW ecc
	304	*****************************************************************************/
54841ab5	305	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546 DB	306	{
	307	if (argc != 2)
	308	goto usage;
	309	if (strncmp(argv[1], "hw", 2) == 0)
	310	omap_nand_switch_ecc(1);
	311	else if (strncmp(argv[1], "sw", 2) == 0)
	312	omap_nand_switch_ecc(0);
	313	else
	314	goto usage;
	315
	316	return 0;
	317
	318	usage:
36003268	319	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	320	return 1;
	321	}
	322
	323	U_BOOT_CMD(
	324	nandecc, 2, 1, do_switch_ecc,
a93c92cd	325	"switch OMAP3 NAND ECC calculation algorithm",
a89c33db WD	326	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	327	);
91eee546	328
bb085b87	329	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	330
	331	#ifdef CONFIG_DISPLAY_BOARDINFO
	332	/**
	333	* Print board information
	334	*/
	335	int checkboard (void)
	336	{
	337	char *mem_s ;
	338
	339	if (is_mem_sdr())
	340	mem_s = "mSDR";
	341	else
	342	mem_s = "LPDDR";
	343
	344	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	345	sysinfo.nand_string);
	346
	347	return 0;
	348	}
	349	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	350
	351	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	352	{
	353	u32 i, num_params = *parameters;
	354	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	355
	356	/*
	357	* copy the parameters to an un-cached area to avoid coherency
	358	* issues
	359	*/
	360	for (i = 0; i < num_params; i++) {
	361	__raw_writel(*parameters, sram_scratch_space);
	362	parameters++;
	363	sram_scratch_space++;
	364	}
	365
	366	/* Now make the PPA call */
	367	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	368	}
	369
	370	static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
	371	{
	372	u32 acr;
	373
	374	/* Read ACR */
	375	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	376	acr &= ~clear_bits;
	377	acr \|= set_bits;
	378
	379	if (get_device_type() == GP_DEVICE) {
	380	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
	381	acr);
	382	} else {
	383	struct emu_hal_params emu_romcode_params;
	384	emu_romcode_params.num_params = 1;
	385	emu_romcode_params.param1 = acr;
	386	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	387	(u32 *)&emu_romcode_params);
	388	}
	389	}
	390
	391	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	392	{
	393	u32 acr;
	394
	395	/* Read ACR */
	396	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	397	acr &= ~clear_bits;
	398	acr \|= set_bits;
	399
	400	/* Write ACR - affects non-secure banked bits */
	401	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
	402	}
	403
	404	static void omap3_setup_aux_cr(void)
	405	{
	406	/* Workaround for Cortex-A8 errata: #454179 #430973
	407	* Set "IBE" bit
a4958313	408	* Set "Disable Branch Size Mispredicts" bit
45bf0585 A	409	* Workaround for erratum #621766
	410	* Enable L1NEON bit
	411	* ACR \|= (IBE \| DBSM \| L1NEON) => ACR \|= 0xE0
	412	*/
	413	omap3_update_aux_cr_secure(0xE0, 0);
	414	}
	415
	416	#ifndef CONFIG_SYS_L2CACHE_OFF
	417	/* Invalidate the entire L2 cache from secure mode */
	418	static void omap3_invalidate_l2_cache_secure(void)
	419	{
	420	if (get_device_type() == GP_DEVICE) {
	421	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
	422	0);
	423	} else {
	424	struct emu_hal_params emu_romcode_params;
	425	emu_romcode_params.num_params = 1;
	426	emu_romcode_params.param1 = 0;
	427	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	428	(u32 *)&emu_romcode_params);
	429	}
	430	}
	431
	432	void v7_outer_cache_enable(void)
	433	{
	434	/* Set L2EN */
	435	omap3_update_aux_cr_secure(0x2, 0);
	436
	437	/*
	438	* On some revisions L2EN bit is banked on some revisions it's not
	439	* No harm in setting both banked bits(in fact this is required
	440	* by an erratum)
	441	*/
	442	omap3_update_aux_cr(0x2, 0);
	443	}
	444
f1f2c3ca	445	void omap3_outer_cache_disable(void)
45bf0585 A	446	{
	447	/* Clear L2EN */
	448	omap3_update_aux_cr_secure(0, 0x2);
	449
	450	/*
	451	* On some revisions L2EN bit is banked on some revisions it's not
	452	* No harm in clearing both banked bits(in fact this is required
	453	* by an erratum)
	454	*/
	455	omap3_update_aux_cr(0, 0x2);
	456	}
	457	#endif
13d4f9bd A	458
	459	#ifndef CONFIG_SYS_DCACHE_OFF
	460	void enable_caches(void)
	461	{
	462	/* Enable D-cache. I-cache is already enabled in start.S */
	463	dcache_enable();
	464	}
	465	#endif