[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap3_boot_device = BOOT_DEVICE_NAND;

/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 spl_boot_mode(void)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC2:
		return MMCSD_MODE_RAW;
	case BOOT_DEVICE_MMC1:
		return MMCSD_MODE_FAT;
		break;
	default:
		puts("spl: ERROR:  unknown device - can't select boot mode\n");
		hang();
	}
}

u32 spl_boot_device(void)
{
	return omap3_boot_device;
}

int board_mmc_init(bd_t *bis)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC1:
		omap_mmc_init(0, 0, 0, -1, -1);
		break;
	case BOOT_DEVICE_MMC2:
	case BOOT_DEVICE_MMC2_2:
		omap_mmc_init(1, 0, 0, -1, -1);
		break;
	}
	return 0;
}

void spl_board_init(void)
{
#ifdef CONFIG_SPL_NAND_SUPPORT
	gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
#endif /* CONFIG_SPL_BUILD */


/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/* Errata workarounds */
	omap3_setup_aux_cr();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif

#ifdef CONFIG_SPL_BUILD
	gd = &gdata;

	preloader_console_init();

	timer_init();
#endif

	if (!in_sdram)
		mem_init();
}

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	dieid_num_r();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
				       acr);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = acr;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
				       (u32 *)&emu_romcode_params);
	}
}

static void omap3_setup_aux_cr(void)
{
	/* Workaround for Cortex-A8 errata: #454179 #430973
	 *	Set "IBE" bit
	 *	Set "Disable Branch Size Mispredicts" bit
	 * Workaround for erratum #621766
	 *	Enable L1NEON bit
	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
	 */
	omap3_update_aux_cr_secure(0xE0, 0);
}

#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	/* Write ACR - affects non-secure banked bits */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
				      0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{
	/* Set L2EN */
	omap3_update_aux_cr_secure(0x2, 0);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/* Clear L2EN */
	omap3_update_aux_cr_secure(0, 0x2);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif /* !CONFIG_SYS_DCACHE_OFF */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
47f7bcae	36	#include <spl.h>
91eee546 DB	37	#include <asm/io.h>
	38	#include <asm/arch/sys_proto.h>
	39	#include <asm/arch/mem.h>
06e758e7	40	#include <asm/cache.h>
45bf0585	41	#include <asm/armv7.h>
080a46ea	42	#include <asm/arch/gpio.h>
bb085b87	43	#include <asm/omap_common.h>
f0881250	44	#include <asm/arch/mmc_host_def.h>
ee08a826	45	#include <i2c.h>
8a87a3d7	46	#include <linux/compiler.h>
91eee546	47
6507f133 TR	48	DECLARE_GLOBAL_DATA_PTR;
6507f133 TR	49
45bf0585	50	/* Declarations */
91eee546	51	extern omap3_sysinfo sysinfo;
45bf0585	52	static void omap3_setup_aux_cr(void);
57f588be	53	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	54	static void omap3_invalidate_l2_cache_secure(void);
57f588be	55	#endif
91eee546	56
25223a68 A	57	static const struct gpio_bank gpio_bank_34xx[6] = {
	58	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	59	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	60	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	61	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	62	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	63	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
	64	};
	65
	66	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	67
bb085b87 SS	68	#ifdef CONFIG_SPL_BUILD
	69	/*
	70	* We use static variables because global data is not ready yet.
	71	* Initialized data is available in SPL right from the beginning.
	72	* We would not typically need to save these parameters in regular
	73	* U-Boot. This is needed only in SPL at the moment.
	74	*/
	75	u32 omap3_boot_device = BOOT_DEVICE_NAND;
	76
	77	/* auto boot mode detection is not possible for OMAP3 - hard code */
37189a19	78	u32 spl_boot_mode(void)
bb085b87	79	{
8e1b836e	80	switch (spl_boot_device()) {
bb085b87 SS	81	case BOOT_DEVICE_MMC2:
	82	return MMCSD_MODE_RAW;
	83	case BOOT_DEVICE_MMC1:
	84	return MMCSD_MODE_FAT;
	85	break;
bb085b87 SS	86	default:
	87	puts("spl: ERROR: unknown device - can't select boot mode\n");
	88	hang();
	89	}
	90	}
	91
8e1b836e	92	u32 spl_boot_device(void)
bb085b87 SS	93	{
	94	return omap3_boot_device;
	95	}
	96
f0881250 TR	97	int board_mmc_init(bd_t *bis)
	98	{
	99	switch (spl_boot_device()) {
	100	case BOOT_DEVICE_MMC1:
e3913f56	101	omap_mmc_init(0, 0, 0, -1, -1);
f0881250 TR	102	break;
	103	case BOOT_DEVICE_MMC2:
	104	case BOOT_DEVICE_MMC2_2:
e3913f56	105	omap_mmc_init(1, 0, 0, -1, -1);
f0881250 TR	106	break;
	107	}
	108	return 0;
	109	}
	110
ee08a826 TR	111	void spl_board_init(void)
ee08a826 TR	112	{
d7cb93b2 TR	113	#ifdef CONFIG_SPL_NAND_SUPPORT
	114	gpmc_init();
	115	#endif
da521387	116	#ifdef CONFIG_SPL_I2C_SUPPORT
ee08a826	117	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
da521387	118	#endif
ee08a826	119	}
bb085b87 SS	120	#endif /* CONFIG_SPL_BUILD */
	121
	122
91eee546 DB	123	/******************************************************************************
	124	* Routine: secure_unlock
	125	* Description: Setup security registers for access
	126	* (GP Device only)
	127	*****************************************************************************/
	128	void secure_unlock_mem(void)
	129	{
97a099ea DB	130	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	131	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	132	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	133	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	134	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	135
	136	/* Protection Module Register Target APE (PM_RT) */
	137	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	138	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	139	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	140	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	141
	142	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	143	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	144	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	145
	146	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	147	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	148	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	149	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	150
	151	/* IVA Changes */
	152	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	153	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	154	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	155
	156	/* SDRC region 0 public */
	157	writel(UNLOCK_1, &sms_base->rg_att0);
	158	}
	159
	160	/******************************************************************************
	161	* Routine: secureworld_exit()
	162	* Description: If chip is EMU and boot type is external
	163	* configure secure registers and exit secure world
	164	* general use.
	165	*****************************************************************************/
	166	void secureworld_exit()
	167	{
	168	unsigned long i;
	169
a4958313	170	/* configure non-secure access control register */
91eee546 DB	171	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	172	/* enabling co-processor CP10 and CP11 accesses in NS world */
	173	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	174	/*
	175	* allow allocation of locked TLBs and L2 lines in NS world
	176	* allow use of PLE registers in NS world also
	177	*/
	178	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	179	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	180
	181	/* Enable ASA in ACR register */
	182	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	183	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	184	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	185
	186	/* Exiting secure world */
	187	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	188	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	189	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	190	}
	191
91eee546 DB	192	/******************************************************************************
	193	* Routine: try_unlock_sram()
	194	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	195	* general use.
	196	*****************************************************************************/
	197	void try_unlock_memory()
	198	{
	199	int mode;
	200	int in_sdram = is_running_in_sdram();
	201
	202	/*
	203	* if GP device unlock device SRAM for general use
	204	* secure code breaks for Secure/Emulation device - HS/E/T
	205	*/
	206	mode = get_device_type();
	207	if (mode == GP_DEVICE)
	208	secure_unlock_mem();
	209
	210	/*
	211	* If device is EMU and boot is XIP external booting
	212	* Unlock firewalls and disable L2 and put chip
	213	* out of secure world
	214	*
	215	* Assuming memories are unlocked by the demon who put us in SDRAM
	216	*/
	217	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	218	&& (!in_sdram)) {
	219	secure_unlock_mem();
	220	secureworld_exit();
	221	}
	222
	223	return;
	224	}
	225
	226	/******************************************************************************
	227	* Routine: s_init
	228	* Description: Does early system init of muxing and clocks.
	229	* - Called path is with SRAM stack.
	230	*****************************************************************************/
	231	void s_init(void)
	232	{
	233	int in_sdram = is_running_in_sdram();
	234
	235	watchdog_init();
	236
	237	try_unlock_memory();
	238
45bf0585 A	239	/* Errata workarounds */
45bf0585 A	240	omap3_setup_aux_cr();
91eee546	241
45bf0585 A	242	#ifndef CONFIG_SYS_L2CACHE_OFF
	243	/* Invalidate L2-cache from secure mode */
	244	omap3_invalidate_l2_cache_secure();
91eee546	245	#endif
91eee546 DB	246
91eee546 DB	247	set_muxconf_regs();
86623add	248	sdelay(100);
91eee546 DB	249
	250	prcm_init();
	251
	252	per_clocks_enable();
	253
95f87910 G	254	#ifdef CONFIG_USB_EHCI_OMAP
	255	ehci_clocks_enable();
	256	#endif
	257
bb085b87	258	#ifdef CONFIG_SPL_BUILD
6507f133 TR	259	gd = &gdata;
6507f133 TR	260
bb085b87	261	preloader_console_init();
8775471b AM	262
8775471b AM	263	timer_init();
bb085b87 SS	264	#endif
bb085b87 SS	265
91eee546	266	if (!in_sdram)
cae377b5	267	mem_init();
91eee546 DB	268	}
91eee546 DB	269
8a87a3d7 TR	270	/*
	271	* Routine: misc_init_r
	272	* Description: A basic misc_init_r that just displays the die ID
	273	*/
	274	int __weak misc_init_r(void)
	275	{
	276	dieid_num_r();
	277
	278	return 0;
	279	}
	280
91eee546 DB	281	/******************************************************************************
	282	* Routine: wait_for_command_complete
	283	* Description: Wait for posting to finish on watchdog
	284	*****************************************************************************/
97a099ea	285	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	286	{
	287	int pending = 1;
	288	do {
	289	pending = readl(&wd_base->wwps);
	290	} while (pending);
	291	}
	292
	293	/******************************************************************************
	294	* Routine: watchdog_init
	295	* Description: Shut down watch dogs
	296	*****************************************************************************/
	297	void watchdog_init(void)
	298	{
97a099ea DB	299	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	300	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	301
	302	/*
	303	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	304	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	305	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	306	* should not be running and does not generate a PRCM reset.
	307	*/
	308
	309	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	310	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	311	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	312
	313	writel(WD_UNLOCK1, &wd2_base->wspr);
	314	wait_for_command_complete(wd2_base);
	315	writel(WD_UNLOCK2, &wd2_base->wspr);
	316	}
	317
91eee546 DB	318	/******************************************************************************
	319	* Dummy function to handle errors for EABI incompatibility
	320	*****************************************************************************/
	321	void abort(void)
	322	{
	323	}
	324
bb085b87	325	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	326	/******************************************************************************
	327	* OMAP3 specific command to switch between NAND HW and SW ecc
	328	*****************************************************************************/
54841ab5	329	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546 DB	330	{
	331	if (argc != 2)
	332	goto usage;
	333	if (strncmp(argv[1], "hw", 2) == 0)
	334	omap_nand_switch_ecc(1);
	335	else if (strncmp(argv[1], "sw", 2) == 0)
	336	omap_nand_switch_ecc(0);
	337	else
	338	goto usage;
	339
	340	return 0;
	341
	342	usage:
36003268	343	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	344	return 1;
	345	}
	346
	347	U_BOOT_CMD(
	348	nandecc, 2, 1, do_switch_ecc,
a93c92cd	349	"switch OMAP3 NAND ECC calculation algorithm",
a89c33db WD	350	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	351	);
91eee546	352
bb085b87	353	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	354
	355	#ifdef CONFIG_DISPLAY_BOARDINFO
	356	/**
	357	* Print board information
	358	*/
	359	int checkboard (void)
	360	{
	361	char *mem_s ;
	362
	363	if (is_mem_sdr())
	364	mem_s = "mSDR";
	365	else
	366	mem_s = "LPDDR";
	367
	368	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	369	sysinfo.nand_string);
	370
	371	return 0;
	372	}
	373	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	374
	375	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	376	{
	377	u32 i, num_params = *parameters;
	378	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	379
	380	/*
	381	* copy the parameters to an un-cached area to avoid coherency
	382	* issues
	383	*/
	384	for (i = 0; i < num_params; i++) {
	385	__raw_writel(*parameters, sram_scratch_space);
	386	parameters++;
	387	sram_scratch_space++;
	388	}
	389
	390	/* Now make the PPA call */
	391	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	392	}
	393
	394	static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
	395	{
	396	u32 acr;
	397
	398	/* Read ACR */
	399	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	400	acr &= ~clear_bits;
	401	acr \|= set_bits;
	402
	403	if (get_device_type() == GP_DEVICE) {
	404	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
	405	acr);
	406	} else {
	407	struct emu_hal_params emu_romcode_params;
	408	emu_romcode_params.num_params = 1;
	409	emu_romcode_params.param1 = acr;
	410	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	411	(u32 *)&emu_romcode_params);
	412	}
	413	}
	414
45bf0585 A	415	static void omap3_setup_aux_cr(void)
	416	{
	417	/* Workaround for Cortex-A8 errata: #454179 #430973
	418	* Set "IBE" bit
a4958313	419	* Set "Disable Branch Size Mispredicts" bit
45bf0585 A	420	* Workaround for erratum #621766
	421	* Enable L1NEON bit
	422	* ACR \|= (IBE \| DBSM \| L1NEON) => ACR \|= 0xE0
	423	*/
	424	omap3_update_aux_cr_secure(0xE0, 0);
	425	}
	426
	427	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	428	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	429	{
	430	u32 acr;
	431
	432	/* Read ACR */
	433	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	434	acr &= ~clear_bits;
	435	acr \|= set_bits;
	436
	437	/* Write ACR - affects non-secure banked bits */
	438	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
	439	}
	440
45bf0585 A	441	/* Invalidate the entire L2 cache from secure mode */
	442	static void omap3_invalidate_l2_cache_secure(void)
	443	{
	444	if (get_device_type() == GP_DEVICE) {
	445	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
	446	0);
	447	} else {
	448	struct emu_hal_params emu_romcode_params;
	449	emu_romcode_params.num_params = 1;
	450	emu_romcode_params.param1 = 0;
	451	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	452	(u32 *)&emu_romcode_params);
	453	}
	454	}
	455
	456	void v7_outer_cache_enable(void)
	457	{
	458	/* Set L2EN */
	459	omap3_update_aux_cr_secure(0x2, 0);
	460
	461	/*
	462	* On some revisions L2EN bit is banked on some revisions it's not
	463	* No harm in setting both banked bits(in fact this is required
	464	* by an erratum)
	465	*/
	466	omap3_update_aux_cr(0x2, 0);
	467	}
	468
f1f2c3ca	469	void omap3_outer_cache_disable(void)
45bf0585 A	470	{
	471	/* Clear L2EN */
	472	omap3_update_aux_cr_secure(0, 0x2);
	473
	474	/*
	475	* On some revisions L2EN bit is banked on some revisions it's not
	476	* No harm in clearing both banked bits(in fact this is required
	477	* by an erratum)
	478	*/
	479	omap3_update_aux_cr(0, 0x2);
	480	}
e3fe6257	481	#endif /* !CONFIG_SYS_L2CACHE_OFF */
13d4f9bd A	482
	483	#ifndef CONFIG_SYS_DCACHE_OFF
	484	void enable_caches(void)
	485	{
	486	/* Enable D-cache. I-cache is already enabled in start.S */
	487	dcache_enable();
	488	}
e3fe6257	489	#endif /* !CONFIG_SYS_DCACHE_OFF */