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91eee546 DB |
1 | /* |
2 | * | |
3 | * Common board functions for OMAP3 based boards. | |
4 | * | |
5 | * (C) Copyright 2004-2008 | |
6 | * Texas Instruments, <www.ti.com> | |
7 | * | |
8 | * Author : | |
9 | * Sunil Kumar <sunilsaini05@gmail.com> | |
10 | * Shashi Ranjan <shashiranjanmca05@gmail.com> | |
11 | * | |
12 | * Derived from Beagle Board and 3430 SDP code by | |
13 | * Richard Woodruff <r-woodruff2@ti.com> | |
14 | * Syed Mohammed Khasim <khasim@ti.com> | |
15 | * | |
16 | * | |
17 | * See file CREDITS for list of people who contributed to this | |
18 | * project. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License as | |
22 | * published by the Free Software Foundation; either version 2 of | |
23 | * the License, or (at your option) any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; if not, write to the Free Software | |
32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
33 | * MA 02111-1307 USA | |
34 | */ | |
35 | #include <common.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/arch/sys_proto.h> | |
38 | #include <asm/arch/mem.h> | |
06e758e7 | 39 | #include <asm/cache.h> |
45bf0585 | 40 | #include <asm/armv7.h> |
080a46ea | 41 | #include <asm/arch/gpio.h> |
bb085b87 | 42 | #include <asm/omap_common.h> |
ee08a826 | 43 | #include <i2c.h> |
91eee546 | 44 | |
45bf0585 | 45 | /* Declarations */ |
91eee546 | 46 | extern omap3_sysinfo sysinfo; |
45bf0585 A |
47 | static void omap3_setup_aux_cr(void); |
48 | static void omap3_invalidate_l2_cache_secure(void); | |
91eee546 | 49 | |
25223a68 A |
50 | static const struct gpio_bank gpio_bank_34xx[6] = { |
51 | { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, | |
52 | { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX }, | |
53 | { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX }, | |
54 | { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX }, | |
55 | { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX }, | |
56 | { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX }, | |
57 | }; | |
58 | ||
59 | const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; | |
60 | ||
bb085b87 SS |
61 | #ifdef CONFIG_SPL_BUILD |
62 | /* | |
63 | * We use static variables because global data is not ready yet. | |
64 | * Initialized data is available in SPL right from the beginning. | |
65 | * We would not typically need to save these parameters in regular | |
66 | * U-Boot. This is needed only in SPL at the moment. | |
67 | */ | |
68 | u32 omap3_boot_device = BOOT_DEVICE_NAND; | |
69 | ||
70 | /* auto boot mode detection is not possible for OMAP3 - hard code */ | |
71 | u32 omap_boot_mode(void) | |
72 | { | |
73 | switch (omap_boot_device()) { | |
74 | case BOOT_DEVICE_MMC2: | |
75 | return MMCSD_MODE_RAW; | |
76 | case BOOT_DEVICE_MMC1: | |
77 | return MMCSD_MODE_FAT; | |
78 | break; | |
79 | case BOOT_DEVICE_NAND: | |
80 | return NAND_MODE_HW_ECC; | |
81 | break; | |
82 | default: | |
83 | puts("spl: ERROR: unknown device - can't select boot mode\n"); | |
84 | hang(); | |
85 | } | |
86 | } | |
87 | ||
88 | u32 omap_boot_device(void) | |
89 | { | |
90 | return omap3_boot_device; | |
91 | } | |
92 | ||
ee08a826 TR |
93 | void spl_board_init(void) |
94 | { | |
95 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
96 | } | |
bb085b87 SS |
97 | #endif /* CONFIG_SPL_BUILD */ |
98 | ||
99 | ||
91eee546 DB |
100 | /****************************************************************************** |
101 | * Routine: secure_unlock | |
102 | * Description: Setup security registers for access | |
103 | * (GP Device only) | |
104 | *****************************************************************************/ | |
105 | void secure_unlock_mem(void) | |
106 | { | |
97a099ea DB |
107 | struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM; |
108 | struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM; | |
109 | struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM; | |
110 | struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM; | |
111 | struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE; | |
91eee546 DB |
112 | |
113 | /* Protection Module Register Target APE (PM_RT) */ | |
114 | writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1); | |
115 | writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0); | |
116 | writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0); | |
117 | writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1); | |
118 | ||
119 | writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0); | |
120 | writel(UNLOCK_3, &pm_gpmc_base->read_permission_0); | |
121 | writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0); | |
122 | ||
123 | writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0); | |
124 | writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0); | |
125 | writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0); | |
126 | writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2); | |
127 | ||
128 | /* IVA Changes */ | |
129 | writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0); | |
130 | writel(UNLOCK_3, &pm_iva2_base->read_permission_0); | |
131 | writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0); | |
132 | ||
133 | /* SDRC region 0 public */ | |
134 | writel(UNLOCK_1, &sms_base->rg_att0); | |
135 | } | |
136 | ||
137 | /****************************************************************************** | |
138 | * Routine: secureworld_exit() | |
139 | * Description: If chip is EMU and boot type is external | |
140 | * configure secure registers and exit secure world | |
141 | * general use. | |
142 | *****************************************************************************/ | |
143 | void secureworld_exit() | |
144 | { | |
145 | unsigned long i; | |
146 | ||
147 | /* configrue non-secure access control register */ | |
148 | __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i)); | |
149 | /* enabling co-processor CP10 and CP11 accesses in NS world */ | |
150 | __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i)); | |
151 | /* | |
152 | * allow allocation of locked TLBs and L2 lines in NS world | |
153 | * allow use of PLE registers in NS world also | |
154 | */ | |
155 | __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i)); | |
156 | __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i)); | |
157 | ||
158 | /* Enable ASA in ACR register */ | |
159 | __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); | |
160 | __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i)); | |
161 | __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); | |
162 | ||
163 | /* Exiting secure world */ | |
164 | __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i)); | |
165 | __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i)); | |
166 | __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i)); | |
167 | } | |
168 | ||
91eee546 DB |
169 | /****************************************************************************** |
170 | * Routine: try_unlock_sram() | |
171 | * Description: If chip is GP/EMU(special) type, unlock the SRAM for | |
172 | * general use. | |
173 | *****************************************************************************/ | |
174 | void try_unlock_memory() | |
175 | { | |
176 | int mode; | |
177 | int in_sdram = is_running_in_sdram(); | |
178 | ||
179 | /* | |
180 | * if GP device unlock device SRAM for general use | |
181 | * secure code breaks for Secure/Emulation device - HS/E/T | |
182 | */ | |
183 | mode = get_device_type(); | |
184 | if (mode == GP_DEVICE) | |
185 | secure_unlock_mem(); | |
186 | ||
187 | /* | |
188 | * If device is EMU and boot is XIP external booting | |
189 | * Unlock firewalls and disable L2 and put chip | |
190 | * out of secure world | |
191 | * | |
192 | * Assuming memories are unlocked by the demon who put us in SDRAM | |
193 | */ | |
194 | if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F) | |
195 | && (!in_sdram)) { | |
196 | secure_unlock_mem(); | |
197 | secureworld_exit(); | |
198 | } | |
199 | ||
200 | return; | |
201 | } | |
202 | ||
203 | /****************************************************************************** | |
204 | * Routine: s_init | |
205 | * Description: Does early system init of muxing and clocks. | |
206 | * - Called path is with SRAM stack. | |
207 | *****************************************************************************/ | |
208 | void s_init(void) | |
209 | { | |
210 | int in_sdram = is_running_in_sdram(); | |
211 | ||
212 | watchdog_init(); | |
213 | ||
214 | try_unlock_memory(); | |
215 | ||
45bf0585 A |
216 | /* Errata workarounds */ |
217 | omap3_setup_aux_cr(); | |
91eee546 | 218 | |
45bf0585 A |
219 | #ifndef CONFIG_SYS_L2CACHE_OFF |
220 | /* Invalidate L2-cache from secure mode */ | |
221 | omap3_invalidate_l2_cache_secure(); | |
91eee546 | 222 | #endif |
91eee546 DB |
223 | |
224 | set_muxconf_regs(); | |
86623add | 225 | sdelay(100); |
91eee546 DB |
226 | |
227 | prcm_init(); | |
228 | ||
229 | per_clocks_enable(); | |
230 | ||
95f87910 G |
231 | #ifdef CONFIG_USB_EHCI_OMAP |
232 | ehci_clocks_enable(); | |
233 | #endif | |
234 | ||
bb085b87 SS |
235 | #ifdef CONFIG_SPL_BUILD |
236 | preloader_console_init(); | |
8775471b AM |
237 | |
238 | timer_init(); | |
bb085b87 SS |
239 | #endif |
240 | ||
91eee546 | 241 | if (!in_sdram) |
cae377b5 | 242 | mem_init(); |
91eee546 DB |
243 | } |
244 | ||
245 | /****************************************************************************** | |
246 | * Routine: wait_for_command_complete | |
247 | * Description: Wait for posting to finish on watchdog | |
248 | *****************************************************************************/ | |
97a099ea | 249 | void wait_for_command_complete(struct watchdog *wd_base) |
91eee546 DB |
250 | { |
251 | int pending = 1; | |
252 | do { | |
253 | pending = readl(&wd_base->wwps); | |
254 | } while (pending); | |
255 | } | |
256 | ||
257 | /****************************************************************************** | |
258 | * Routine: watchdog_init | |
259 | * Description: Shut down watch dogs | |
260 | *****************************************************************************/ | |
261 | void watchdog_init(void) | |
262 | { | |
97a099ea DB |
263 | struct watchdog *wd2_base = (struct watchdog *)WD2_BASE; |
264 | struct prcm *prcm_base = (struct prcm *)PRCM_BASE; | |
91eee546 DB |
265 | |
266 | /* | |
267 | * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is | |
268 | * either taken care of by ROM (HS/EMU) or not accessible (GP). | |
269 | * We need to take care of WD2-MPU or take a PRCM reset. WD3 | |
270 | * should not be running and does not generate a PRCM reset. | |
271 | */ | |
272 | ||
273 | sr32(&prcm_base->fclken_wkup, 5, 1, 1); | |
274 | sr32(&prcm_base->iclken_wkup, 5, 1, 1); | |
275 | wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5); | |
276 | ||
277 | writel(WD_UNLOCK1, &wd2_base->wspr); | |
278 | wait_for_command_complete(wd2_base); | |
279 | writel(WD_UNLOCK2, &wd2_base->wspr); | |
280 | } | |
281 | ||
91eee546 DB |
282 | /****************************************************************************** |
283 | * Dummy function to handle errors for EABI incompatibility | |
284 | *****************************************************************************/ | |
285 | void abort(void) | |
286 | { | |
287 | } | |
288 | ||
bb085b87 | 289 | #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD) |
91eee546 DB |
290 | /****************************************************************************** |
291 | * OMAP3 specific command to switch between NAND HW and SW ecc | |
292 | *****************************************************************************/ | |
54841ab5 | 293 | static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) |
91eee546 DB |
294 | { |
295 | if (argc != 2) | |
296 | goto usage; | |
297 | if (strncmp(argv[1], "hw", 2) == 0) | |
298 | omap_nand_switch_ecc(1); | |
299 | else if (strncmp(argv[1], "sw", 2) == 0) | |
300 | omap_nand_switch_ecc(0); | |
301 | else | |
302 | goto usage; | |
303 | ||
304 | return 0; | |
305 | ||
306 | usage: | |
36003268 | 307 | printf ("Usage: nandecc %s\n", cmdtp->usage); |
91eee546 DB |
308 | return 1; |
309 | } | |
310 | ||
311 | U_BOOT_CMD( | |
312 | nandecc, 2, 1, do_switch_ecc, | |
a93c92cd | 313 | "switch OMAP3 NAND ECC calculation algorithm", |
a89c33db WD |
314 | "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" |
315 | ); | |
91eee546 | 316 | |
bb085b87 | 317 | #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ |
6a6b62e3 SP |
318 | |
319 | #ifdef CONFIG_DISPLAY_BOARDINFO | |
320 | /** | |
321 | * Print board information | |
322 | */ | |
323 | int checkboard (void) | |
324 | { | |
325 | char *mem_s ; | |
326 | ||
327 | if (is_mem_sdr()) | |
328 | mem_s = "mSDR"; | |
329 | else | |
330 | mem_s = "LPDDR"; | |
331 | ||
332 | printf("%s + %s/%s\n", sysinfo.board_string, mem_s, | |
333 | sysinfo.nand_string); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | #endif /* CONFIG_DISPLAY_BOARDINFO */ | |
45bf0585 A |
338 | |
339 | static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) | |
340 | { | |
341 | u32 i, num_params = *parameters; | |
342 | u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA; | |
343 | ||
344 | /* | |
345 | * copy the parameters to an un-cached area to avoid coherency | |
346 | * issues | |
347 | */ | |
348 | for (i = 0; i < num_params; i++) { | |
349 | __raw_writel(*parameters, sram_scratch_space); | |
350 | parameters++; | |
351 | sram_scratch_space++; | |
352 | } | |
353 | ||
354 | /* Now make the PPA call */ | |
355 | do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); | |
356 | } | |
357 | ||
358 | static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) | |
359 | { | |
360 | u32 acr; | |
361 | ||
362 | /* Read ACR */ | |
363 | asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); | |
364 | acr &= ~clear_bits; | |
365 | acr |= set_bits; | |
366 | ||
367 | if (get_device_type() == GP_DEVICE) { | |
368 | omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, | |
369 | acr); | |
370 | } else { | |
371 | struct emu_hal_params emu_romcode_params; | |
372 | emu_romcode_params.num_params = 1; | |
373 | emu_romcode_params.param1 = acr; | |
374 | omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, | |
375 | (u32 *)&emu_romcode_params); | |
376 | } | |
377 | } | |
378 | ||
379 | static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) | |
380 | { | |
381 | u32 acr; | |
382 | ||
383 | /* Read ACR */ | |
384 | asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); | |
385 | acr &= ~clear_bits; | |
386 | acr |= set_bits; | |
387 | ||
388 | /* Write ACR - affects non-secure banked bits */ | |
389 | asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); | |
390 | } | |
391 | ||
392 | static void omap3_setup_aux_cr(void) | |
393 | { | |
394 | /* Workaround for Cortex-A8 errata: #454179 #430973 | |
395 | * Set "IBE" bit | |
396 | * Set "Disable Brach Size Mispredicts" bit | |
397 | * Workaround for erratum #621766 | |
398 | * Enable L1NEON bit | |
399 | * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 | |
400 | */ | |
401 | omap3_update_aux_cr_secure(0xE0, 0); | |
402 | } | |
403 | ||
404 | #ifndef CONFIG_SYS_L2CACHE_OFF | |
405 | /* Invalidate the entire L2 cache from secure mode */ | |
406 | static void omap3_invalidate_l2_cache_secure(void) | |
407 | { | |
408 | if (get_device_type() == GP_DEVICE) { | |
409 | omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, | |
410 | 0); | |
411 | } else { | |
412 | struct emu_hal_params emu_romcode_params; | |
413 | emu_romcode_params.num_params = 1; | |
414 | emu_romcode_params.param1 = 0; | |
415 | omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL, | |
416 | (u32 *)&emu_romcode_params); | |
417 | } | |
418 | } | |
419 | ||
420 | void v7_outer_cache_enable(void) | |
421 | { | |
422 | /* Set L2EN */ | |
423 | omap3_update_aux_cr_secure(0x2, 0); | |
424 | ||
425 | /* | |
426 | * On some revisions L2EN bit is banked on some revisions it's not | |
427 | * No harm in setting both banked bits(in fact this is required | |
428 | * by an erratum) | |
429 | */ | |
430 | omap3_update_aux_cr(0x2, 0); | |
431 | } | |
432 | ||
433 | void v7_outer_cache_disable(void) | |
434 | { | |
435 | /* Clear L2EN */ | |
436 | omap3_update_aux_cr_secure(0, 0x2); | |
437 | ||
438 | /* | |
439 | * On some revisions L2EN bit is banked on some revisions it's not | |
440 | * No harm in clearing both banked bits(in fact this is required | |
441 | * by an erratum) | |
442 | */ | |
443 | omap3_update_aux_cr(0, 0x2); | |
444 | } | |
445 | #endif | |
13d4f9bd A |
446 | |
447 | #ifndef CONFIG_SYS_DCACHE_OFF | |
448 | void enable_caches(void) | |
449 | { | |
450 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
451 | dcache_enable(); | |
452 | } | |
453 | #endif |