[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/omap_common.h>
#include <i2c.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
static void omap3_invalidate_l2_cache_secure(void);

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap3_boot_device = BOOT_DEVICE_NAND;

/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 omap_boot_mode(void)
{
	switch (omap_boot_device()) {
	case BOOT_DEVICE_MMC2:
		return MMCSD_MODE_RAW;
	case BOOT_DEVICE_MMC1:
		return MMCSD_MODE_FAT;
		break;
	case BOOT_DEVICE_NAND:
		return NAND_MODE_HW_ECC;
		break;
	default:
		puts("spl: ERROR:  unknown device - can't select boot mode\n");
		hang();
	}
}

u32 omap_boot_device(void)
{
	return omap3_boot_device;
}

void spl_board_init(void)
{
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
}
#endif /* CONFIG_SPL_BUILD */


/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/* Errata workarounds */
	omap3_setup_aux_cr();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif

#ifdef CONFIG_SPL_BUILD
	preloader_console_init();

	timer_init();
#endif

	if (!in_sdram)
		mem_init();
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
				       acr);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = acr;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
				       (u32 *)&emu_romcode_params);
	}
}

static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	/* Write ACR - affects non-secure banked bits */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}

static void omap3_setup_aux_cr(void)
{
	/* Workaround for Cortex-A8 errata: #454179 #430973
	 *	Set "IBE" bit
	 *	Set "Disable Branch Size Mispredicts" bit
	 * Workaround for erratum #621766
	 *	Enable L1NEON bit
	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
	 */
	omap3_update_aux_cr_secure(0xE0, 0);
}

#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
				      0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{
	/* Set L2EN */
	omap3_update_aux_cr_secure(0x2, 0);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/* Clear L2EN */
	omap3_update_aux_cr_secure(0, 0x2);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
06e758e7	39	#include <asm/cache.h>
45bf0585	40	#include <asm/armv7.h>
080a46ea	41	#include <asm/arch/gpio.h>
bb085b87	42	#include <asm/omap_common.h>
ee08a826	43	#include <i2c.h>
91eee546	44
45bf0585	45	/* Declarations */
91eee546	46	extern omap3_sysinfo sysinfo;
45bf0585 A	47	static void omap3_setup_aux_cr(void);
45bf0585 A	48	static void omap3_invalidate_l2_cache_secure(void);
91eee546	49
25223a68 A	50	static const struct gpio_bank gpio_bank_34xx[6] = {
	51	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	52	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	53	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	54	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	55	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	56	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
	57	};
	58
	59	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	60
bb085b87 SS	61	#ifdef CONFIG_SPL_BUILD
	62	/*
	63	* We use static variables because global data is not ready yet.
	64	* Initialized data is available in SPL right from the beginning.
	65	* We would not typically need to save these parameters in regular
	66	* U-Boot. This is needed only in SPL at the moment.
	67	*/
	68	u32 omap3_boot_device = BOOT_DEVICE_NAND;
	69
	70	/* auto boot mode detection is not possible for OMAP3 - hard code */
	71	u32 omap_boot_mode(void)
	72	{
	73	switch (omap_boot_device()) {
	74	case BOOT_DEVICE_MMC2:
	75	return MMCSD_MODE_RAW;
	76	case BOOT_DEVICE_MMC1:
	77	return MMCSD_MODE_FAT;
	78	break;
	79	case BOOT_DEVICE_NAND:
	80	return NAND_MODE_HW_ECC;
	81	break;
	82	default:
	83	puts("spl: ERROR: unknown device - can't select boot mode\n");
	84	hang();
	85	}
	86	}
	87
	88	u32 omap_boot_device(void)
	89	{
	90	return omap3_boot_device;
	91	}
	92
ee08a826 TR	93	void spl_board_init(void)
	94	{
	95	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	96	}
bb085b87 SS	97	#endif /* CONFIG_SPL_BUILD */
	98
	99
91eee546 DB	100	/******************************************************************************
	101	* Routine: secure_unlock
	102	* Description: Setup security registers for access
	103	* (GP Device only)
	104	*****************************************************************************/
	105	void secure_unlock_mem(void)
	106	{
97a099ea DB	107	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	108	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	109	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	110	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	111	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	112
	113	/* Protection Module Register Target APE (PM_RT) */
	114	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	115	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	116	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	117	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	118
	119	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	120	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	121	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	122
	123	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	124	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	125	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	126	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	127
	128	/* IVA Changes */
	129	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	130	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	131	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	132
	133	/* SDRC region 0 public */
	134	writel(UNLOCK_1, &sms_base->rg_att0);
	135	}
	136
	137	/******************************************************************************
	138	* Routine: secureworld_exit()
	139	* Description: If chip is EMU and boot type is external
	140	* configure secure registers and exit secure world
	141	* general use.
	142	*****************************************************************************/
	143	void secureworld_exit()
	144	{
	145	unsigned long i;
	146
a4958313	147	/* configure non-secure access control register */
91eee546 DB	148	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	149	/* enabling co-processor CP10 and CP11 accesses in NS world */
	150	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	151	/*
	152	* allow allocation of locked TLBs and L2 lines in NS world
	153	* allow use of PLE registers in NS world also
	154	*/
	155	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	156	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	157
	158	/* Enable ASA in ACR register */
	159	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	160	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	161	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	162
	163	/* Exiting secure world */
	164	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	165	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	166	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	167	}
	168
91eee546 DB	169	/******************************************************************************
	170	* Routine: try_unlock_sram()
	171	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	172	* general use.
	173	*****************************************************************************/
	174	void try_unlock_memory()
	175	{
	176	int mode;
	177	int in_sdram = is_running_in_sdram();
	178
	179	/*
	180	* if GP device unlock device SRAM for general use
	181	* secure code breaks for Secure/Emulation device - HS/E/T
	182	*/
	183	mode = get_device_type();
	184	if (mode == GP_DEVICE)
	185	secure_unlock_mem();
	186
	187	/*
	188	* If device is EMU and boot is XIP external booting
	189	* Unlock firewalls and disable L2 and put chip
	190	* out of secure world
	191	*
	192	* Assuming memories are unlocked by the demon who put us in SDRAM
	193	*/
	194	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	195	&& (!in_sdram)) {
	196	secure_unlock_mem();
	197	secureworld_exit();
	198	}
	199
	200	return;
	201	}
	202
	203	/******************************************************************************
	204	* Routine: s_init
	205	* Description: Does early system init of muxing and clocks.
	206	* - Called path is with SRAM stack.
	207	*****************************************************************************/
	208	void s_init(void)
	209	{
	210	int in_sdram = is_running_in_sdram();
	211
	212	watchdog_init();
	213
	214	try_unlock_memory();
	215
45bf0585 A	216	/* Errata workarounds */
45bf0585 A	217	omap3_setup_aux_cr();
91eee546	218
45bf0585 A	219	#ifndef CONFIG_SYS_L2CACHE_OFF
	220	/* Invalidate L2-cache from secure mode */
	221	omap3_invalidate_l2_cache_secure();
91eee546	222	#endif
91eee546 DB	223
91eee546 DB	224	set_muxconf_regs();
86623add	225	sdelay(100);
91eee546 DB	226
	227	prcm_init();
	228
	229	per_clocks_enable();
	230
95f87910 G	231	#ifdef CONFIG_USB_EHCI_OMAP
	232	ehci_clocks_enable();
	233	#endif
	234
bb085b87 SS	235	#ifdef CONFIG_SPL_BUILD
bb085b87 SS	236	preloader_console_init();
8775471b AM	237
8775471b AM	238	timer_init();
bb085b87 SS	239	#endif
bb085b87 SS	240
91eee546	241	if (!in_sdram)
cae377b5	242	mem_init();
91eee546 DB	243	}
	244
	245	/******************************************************************************
	246	* Routine: wait_for_command_complete
	247	* Description: Wait for posting to finish on watchdog
	248	*****************************************************************************/
97a099ea	249	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	250	{
	251	int pending = 1;
	252	do {
	253	pending = readl(&wd_base->wwps);
	254	} while (pending);
	255	}
	256
	257	/******************************************************************************
	258	* Routine: watchdog_init
	259	* Description: Shut down watch dogs
	260	*****************************************************************************/
	261	void watchdog_init(void)
	262	{
97a099ea DB	263	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	264	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	265
	266	/*
	267	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	268	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	269	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	270	* should not be running and does not generate a PRCM reset.
	271	*/
	272
	273	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	274	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	275	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	276
	277	writel(WD_UNLOCK1, &wd2_base->wspr);
	278	wait_for_command_complete(wd2_base);
	279	writel(WD_UNLOCK2, &wd2_base->wspr);
	280	}
	281
91eee546 DB	282	/******************************************************************************
	283	* Dummy function to handle errors for EABI incompatibility
	284	*****************************************************************************/
	285	void abort(void)
	286	{
	287	}
	288
bb085b87	289	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	290	/******************************************************************************
	291	* OMAP3 specific command to switch between NAND HW and SW ecc
	292	*****************************************************************************/
54841ab5	293	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546 DB	294	{
	295	if (argc != 2)
	296	goto usage;
	297	if (strncmp(argv[1], "hw", 2) == 0)
	298	omap_nand_switch_ecc(1);
	299	else if (strncmp(argv[1], "sw", 2) == 0)
	300	omap_nand_switch_ecc(0);
	301	else
	302	goto usage;
	303
	304	return 0;
	305
	306	usage:
36003268	307	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	308	return 1;
	309	}
	310
	311	U_BOOT_CMD(
	312	nandecc, 2, 1, do_switch_ecc,
a93c92cd	313	"switch OMAP3 NAND ECC calculation algorithm",
a89c33db WD	314	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	315	);
91eee546	316
bb085b87	317	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	318
	319	#ifdef CONFIG_DISPLAY_BOARDINFO
	320	/**
	321	* Print board information
	322	*/
	323	int checkboard (void)
	324	{
	325	char *mem_s ;
	326
	327	if (is_mem_sdr())
	328	mem_s = "mSDR";
	329	else
	330	mem_s = "LPDDR";
	331
	332	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	333	sysinfo.nand_string);
	334
	335	return 0;
	336	}
	337	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	338
	339	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	340	{
	341	u32 i, num_params = *parameters;
	342	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	343
	344	/*
	345	* copy the parameters to an un-cached area to avoid coherency
	346	* issues
	347	*/
	348	for (i = 0; i < num_params; i++) {
	349	__raw_writel(*parameters, sram_scratch_space);
	350	parameters++;
	351	sram_scratch_space++;
	352	}
	353
	354	/* Now make the PPA call */
	355	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	356	}
	357
	358	static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
	359	{
	360	u32 acr;
	361
	362	/* Read ACR */
	363	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	364	acr &= ~clear_bits;
	365	acr \|= set_bits;
	366
	367	if (get_device_type() == GP_DEVICE) {
	368	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
	369	acr);
	370	} else {
	371	struct emu_hal_params emu_romcode_params;
	372	emu_romcode_params.num_params = 1;
	373	emu_romcode_params.param1 = acr;
	374	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	375	(u32 *)&emu_romcode_params);
	376	}
	377	}
	378
	379	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	380	{
	381	u32 acr;
	382
	383	/* Read ACR */
	384	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	385	acr &= ~clear_bits;
	386	acr \|= set_bits;
	387
	388	/* Write ACR - affects non-secure banked bits */
	389	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
	390	}
	391
	392	static void omap3_setup_aux_cr(void)
	393	{
	394	/* Workaround for Cortex-A8 errata: #454179 #430973
	395	* Set "IBE" bit
a4958313	396	* Set "Disable Branch Size Mispredicts" bit
45bf0585 A	397	* Workaround for erratum #621766
	398	* Enable L1NEON bit
	399	* ACR \|= (IBE \| DBSM \| L1NEON) => ACR \|= 0xE0
	400	*/
	401	omap3_update_aux_cr_secure(0xE0, 0);
	402	}
	403
	404	#ifndef CONFIG_SYS_L2CACHE_OFF
	405	/* Invalidate the entire L2 cache from secure mode */
	406	static void omap3_invalidate_l2_cache_secure(void)
	407	{
	408	if (get_device_type() == GP_DEVICE) {
	409	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
	410	0);
	411	} else {
	412	struct emu_hal_params emu_romcode_params;
	413	emu_romcode_params.num_params = 1;
	414	emu_romcode_params.param1 = 0;
	415	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	416	(u32 *)&emu_romcode_params);
	417	}
	418	}
	419
	420	void v7_outer_cache_enable(void)
	421	{
	422	/* Set L2EN */
	423	omap3_update_aux_cr_secure(0x2, 0);
	424
	425	/*
	426	* On some revisions L2EN bit is banked on some revisions it's not
	427	* No harm in setting both banked bits(in fact this is required
	428	* by an erratum)
	429	*/
	430	omap3_update_aux_cr(0x2, 0);
	431	}
	432
f1f2c3ca	433	void omap3_outer_cache_disable(void)
45bf0585 A	434	{
	435	/* Clear L2EN */
	436	omap3_update_aux_cr_secure(0, 0x2);
	437
	438	/*
	439	* On some revisions L2EN bit is banked on some revisions it's not
	440	* No harm in clearing both banked bits(in fact this is required
	441	* by an erratum)
	442	*/
	443	omap3_update_aux_cr(0, 0x2);
	444	}
	445	#endif
13d4f9bd A	446
	447	#ifndef CONFIG_SYS_DCACHE_OFF
	448	void enable_caches(void)
	449	{
	450	/* Enable D-cache. I-cache is already enabled in start.S */
	451	dcache_enable();
	452	}
	453	#endif