[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <sunilsaini05@gmail.com>
 *      Shashi Ranjan <shashiranjanmca05@gmail.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/arch/gpio.h>
#include <asm/spl.h>
#include <asm/omap_common.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
#include <linux/compiler.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
static void omap3_setup_aux_cr(void);
static void omap3_invalidate_l2_cache_secure(void);

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#ifdef CONFIG_SPL_BUILD
/*
* We use static variables because global data is not ready yet.
* Initialized data is available in SPL right from the beginning.
* We would not typically need to save these parameters in regular
* U-Boot. This is needed only in SPL at the moment.
*/
u32 omap3_boot_device = BOOT_DEVICE_NAND;

/* auto boot mode detection is not possible for OMAP3 - hard code */
u32 spl_boot_mode(void)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC2:
		return MMCSD_MODE_RAW;
	case BOOT_DEVICE_MMC1:
		return MMCSD_MODE_FAT;
		break;
	default:
		puts("spl: ERROR:  unknown device - can't select boot mode\n");
		hang();
	}
}

u32 spl_boot_device(void)
{
	return omap3_boot_device;
}

int board_mmc_init(bd_t *bis)
{
	switch (spl_boot_device()) {
	case BOOT_DEVICE_MMC1:
		omap_mmc_init(0, 0, 0);
		break;
	case BOOT_DEVICE_MMC2:
	case BOOT_DEVICE_MMC2_2:
		omap_mmc_init(1, 0, 0);
		break;
	}
	return 0;
}

void spl_board_init(void)
{
#ifdef CONFIG_SPL_NAND_SUPPORT
	gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}
#endif /* CONFIG_SPL_BUILD */


/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/* Errata workarounds */
	omap3_setup_aux_cr();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif

#ifdef CONFIG_SPL_BUILD
	preloader_console_init();

	timer_init();
#endif

	if (!in_sdram)
		mem_init();
}

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	dieid_num_r();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
				       acr);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = acr;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
				       (u32 *)&emu_romcode_params);
	}
}

static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;

	/* Write ACR - affects non-secure banked bits */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}

static void omap3_setup_aux_cr(void)
{
	/* Workaround for Cortex-A8 errata: #454179 #430973
	 *	Set "IBE" bit
	 *	Set "Disable Branch Size Mispredicts" bit
	 * Workaround for erratum #621766
	 *	Enable L1NEON bit
	 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
	 */
	omap3_update_aux_cr_secure(0xE0, 0);
}

#ifndef CONFIG_SYS_L2CACHE_OFF
/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
				      0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{
	/* Set L2EN */
	omap3_update_aux_cr_secure(0x2, 0);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/* Clear L2EN */
	omap3_update_aux_cr_secure(0, 0x2);

	/*
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <sunilsaini05@gmail.com>
	10	* Shashi Ranjan <shashiranjanmca05@gmail.com>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <r-woodruff2@ti.com>
	14	* Syed Mohammed Khasim <khasim@ti.com>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
06e758e7	39	#include <asm/cache.h>
45bf0585	40	#include <asm/armv7.h>
080a46ea	41	#include <asm/arch/gpio.h>
55cdbb8d	42	#include <asm/spl.h>
bb085b87	43	#include <asm/omap_common.h>
f0881250	44	#include <asm/arch/mmc_host_def.h>
ee08a826	45	#include <i2c.h>
8a87a3d7	46	#include <linux/compiler.h>
91eee546	47
45bf0585	48	/* Declarations */
91eee546	49	extern omap3_sysinfo sysinfo;
45bf0585 A	50	static void omap3_setup_aux_cr(void);
45bf0585 A	51	static void omap3_invalidate_l2_cache_secure(void);
91eee546	52
25223a68 A	53	static const struct gpio_bank gpio_bank_34xx[6] = {
	54	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
	55	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
	56	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
	57	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
	58	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
	59	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
	60	};
	61
	62	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	63
bb085b87 SS	64	#ifdef CONFIG_SPL_BUILD
	65	/*
	66	* We use static variables because global data is not ready yet.
	67	* Initialized data is available in SPL right from the beginning.
	68	* We would not typically need to save these parameters in regular
	69	* U-Boot. This is needed only in SPL at the moment.
	70	*/
	71	u32 omap3_boot_device = BOOT_DEVICE_NAND;
	72
	73	/* auto boot mode detection is not possible for OMAP3 - hard code */
37189a19	74	u32 spl_boot_mode(void)
bb085b87	75	{
8e1b836e	76	switch (spl_boot_device()) {
bb085b87 SS	77	case BOOT_DEVICE_MMC2:
	78	return MMCSD_MODE_RAW;
	79	case BOOT_DEVICE_MMC1:
	80	return MMCSD_MODE_FAT;
	81	break;
bb085b87 SS	82	default:
	83	puts("spl: ERROR: unknown device - can't select boot mode\n");
	84	hang();
	85	}
	86	}
	87
8e1b836e	88	u32 spl_boot_device(void)
bb085b87 SS	89	{
	90	return omap3_boot_device;
	91	}
	92
f0881250 TR	93	int board_mmc_init(bd_t *bis)
	94	{
	95	switch (spl_boot_device()) {
	96	case BOOT_DEVICE_MMC1:
	97	omap_mmc_init(0, 0, 0);
	98	break;
	99	case BOOT_DEVICE_MMC2:
	100	case BOOT_DEVICE_MMC2_2:
	101	omap_mmc_init(1, 0, 0);
	102	break;
	103	}
	104	return 0;
	105	}
	106
ee08a826 TR	107	void spl_board_init(void)
ee08a826 TR	108	{
d7cb93b2 TR	109	#ifdef CONFIG_SPL_NAND_SUPPORT
	110	gpmc_init();
	111	#endif
da521387	112	#ifdef CONFIG_SPL_I2C_SUPPORT
ee08a826	113	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
da521387	114	#endif
ee08a826	115	}
bb085b87 SS	116	#endif /* CONFIG_SPL_BUILD */
	117
	118
91eee546 DB	119	/******************************************************************************
	120	* Routine: secure_unlock
	121	* Description: Setup security registers for access
	122	* (GP Device only)
	123	*****************************************************************************/
	124	void secure_unlock_mem(void)
	125	{
97a099ea DB	126	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	127	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	128	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	129	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	130	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	131
	132	/* Protection Module Register Target APE (PM_RT) */
	133	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	134	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	135	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	136	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	137
	138	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	139	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	140	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	141
	142	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	143	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	144	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	145	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	146
	147	/* IVA Changes */
	148	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	149	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	150	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	151
	152	/* SDRC region 0 public */
	153	writel(UNLOCK_1, &sms_base->rg_att0);
	154	}
	155
	156	/******************************************************************************
	157	* Routine: secureworld_exit()
	158	* Description: If chip is EMU and boot type is external
	159	* configure secure registers and exit secure world
	160	* general use.
	161	*****************************************************************************/
	162	void secureworld_exit()
	163	{
	164	unsigned long i;
	165
a4958313	166	/* configure non-secure access control register */
91eee546 DB	167	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	168	/* enabling co-processor CP10 and CP11 accesses in NS world */
	169	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	170	/*
	171	* allow allocation of locked TLBs and L2 lines in NS world
	172	* allow use of PLE registers in NS world also
	173	*/
	174	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	175	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	176
	177	/* Enable ASA in ACR register */
	178	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	179	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	180	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	181
	182	/* Exiting secure world */
	183	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	184	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	185	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	186	}
	187
91eee546 DB	188	/******************************************************************************
	189	* Routine: try_unlock_sram()
	190	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	191	* general use.
	192	*****************************************************************************/
	193	void try_unlock_memory()
	194	{
	195	int mode;
	196	int in_sdram = is_running_in_sdram();
	197
	198	/*
	199	* if GP device unlock device SRAM for general use
	200	* secure code breaks for Secure/Emulation device - HS/E/T
	201	*/
	202	mode = get_device_type();
	203	if (mode == GP_DEVICE)
	204	secure_unlock_mem();
	205
	206	/*
	207	* If device is EMU and boot is XIP external booting
	208	* Unlock firewalls and disable L2 and put chip
	209	* out of secure world
	210	*
	211	* Assuming memories are unlocked by the demon who put us in SDRAM
	212	*/
	213	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	214	&& (!in_sdram)) {
	215	secure_unlock_mem();
	216	secureworld_exit();
	217	}
	218
	219	return;
	220	}
	221
	222	/******************************************************************************
	223	* Routine: s_init
	224	* Description: Does early system init of muxing and clocks.
	225	* - Called path is with SRAM stack.
	226	*****************************************************************************/
	227	void s_init(void)
	228	{
	229	int in_sdram = is_running_in_sdram();
	230
	231	watchdog_init();
	232
	233	try_unlock_memory();
	234
45bf0585 A	235	/* Errata workarounds */
45bf0585 A	236	omap3_setup_aux_cr();
91eee546	237
45bf0585 A	238	#ifndef CONFIG_SYS_L2CACHE_OFF
	239	/* Invalidate L2-cache from secure mode */
	240	omap3_invalidate_l2_cache_secure();
91eee546	241	#endif
91eee546 DB	242
91eee546 DB	243	set_muxconf_regs();
86623add	244	sdelay(100);
91eee546 DB	245
	246	prcm_init();
	247
	248	per_clocks_enable();
	249
95f87910 G	250	#ifdef CONFIG_USB_EHCI_OMAP
	251	ehci_clocks_enable();
	252	#endif
	253
bb085b87 SS	254	#ifdef CONFIG_SPL_BUILD
bb085b87 SS	255	preloader_console_init();
8775471b AM	256
8775471b AM	257	timer_init();
bb085b87 SS	258	#endif
bb085b87 SS	259
91eee546	260	if (!in_sdram)
cae377b5	261	mem_init();
91eee546 DB	262	}
91eee546 DB	263
8a87a3d7 TR	264	/*
	265	* Routine: misc_init_r
	266	* Description: A basic misc_init_r that just displays the die ID
	267	*/
	268	int __weak misc_init_r(void)
	269	{
	270	dieid_num_r();
	271
	272	return 0;
	273	}
	274
91eee546 DB	275	/******************************************************************************
	276	* Routine: wait_for_command_complete
	277	* Description: Wait for posting to finish on watchdog
	278	*****************************************************************************/
97a099ea	279	void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	280	{
	281	int pending = 1;
	282	do {
	283	pending = readl(&wd_base->wwps);
	284	} while (pending);
	285	}
	286
	287	/******************************************************************************
	288	* Routine: watchdog_init
	289	* Description: Shut down watch dogs
	290	*****************************************************************************/
	291	void watchdog_init(void)
	292	{
97a099ea DB	293	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	294	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	295
	296	/*
	297	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	298	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	299	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	300	* should not be running and does not generate a PRCM reset.
	301	*/
	302
	303	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	304	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	305	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	306
	307	writel(WD_UNLOCK1, &wd2_base->wspr);
	308	wait_for_command_complete(wd2_base);
	309	writel(WD_UNLOCK2, &wd2_base->wspr);
	310	}
	311
91eee546 DB	312	/******************************************************************************
	313	* Dummy function to handle errors for EABI incompatibility
	314	*****************************************************************************/
	315	void abort(void)
	316	{
	317	}
	318
bb085b87	319	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	320	/******************************************************************************
	321	* OMAP3 specific command to switch between NAND HW and SW ecc
	322	*****************************************************************************/
54841ab5	323	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
91eee546 DB	324	{
	325	if (argc != 2)
	326	goto usage;
	327	if (strncmp(argv[1], "hw", 2) == 0)
	328	omap_nand_switch_ecc(1);
	329	else if (strncmp(argv[1], "sw", 2) == 0)
	330	omap_nand_switch_ecc(0);
	331	else
	332	goto usage;
	333
	334	return 0;
	335
	336	usage:
36003268	337	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	338	return 1;
	339	}
	340
	341	U_BOOT_CMD(
	342	nandecc, 2, 1, do_switch_ecc,
a93c92cd	343	"switch OMAP3 NAND ECC calculation algorithm",
a89c33db WD	344	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
a89c33db WD	345	);
91eee546	346
bb085b87	347	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	348
	349	#ifdef CONFIG_DISPLAY_BOARDINFO
	350	/**
	351	* Print board information
	352	*/
	353	int checkboard (void)
	354	{
	355	char *mem_s ;
	356
	357	if (is_mem_sdr())
	358	mem_s = "mSDR";
	359	else
	360	mem_s = "LPDDR";
	361
	362	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	363	sysinfo.nand_string);
	364
	365	return 0;
	366	}
	367	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	368
	369	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	370	{
	371	u32 i, num_params = *parameters;
	372	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	373
	374	/*
	375	* copy the parameters to an un-cached area to avoid coherency
	376	* issues
	377	*/
	378	for (i = 0; i < num_params; i++) {
	379	__raw_writel(*parameters, sram_scratch_space);
	380	parameters++;
	381	sram_scratch_space++;
	382	}
	383
	384	/* Now make the PPA call */
	385	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	386	}
	387
	388	static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
	389	{
	390	u32 acr;
	391
	392	/* Read ACR */
	393	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	394	acr &= ~clear_bits;
	395	acr \|= set_bits;
	396
	397	if (get_device_type() == GP_DEVICE) {
	398	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
	399	acr);
	400	} else {
	401	struct emu_hal_params emu_romcode_params;
	402	emu_romcode_params.num_params = 1;
	403	emu_romcode_params.param1 = acr;
	404	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	405	(u32 *)&emu_romcode_params);
	406	}
	407	}
	408
	409	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	410	{
	411	u32 acr;
	412
	413	/* Read ACR */
	414	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	415	acr &= ~clear_bits;
	416	acr \|= set_bits;
	417
	418	/* Write ACR - affects non-secure banked bits */
	419	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
	420	}
	421
	422	static void omap3_setup_aux_cr(void)
	423	{
	424	/* Workaround for Cortex-A8 errata: #454179 #430973
	425	* Set "IBE" bit
a4958313	426	* Set "Disable Branch Size Mispredicts" bit
45bf0585 A	427	* Workaround for erratum #621766
	428	* Enable L1NEON bit
	429	* ACR \|= (IBE \| DBSM \| L1NEON) => ACR \|= 0xE0
	430	*/
	431	omap3_update_aux_cr_secure(0xE0, 0);
	432	}
	433
	434	#ifndef CONFIG_SYS_L2CACHE_OFF
	435	/* Invalidate the entire L2 cache from secure mode */
	436	static void omap3_invalidate_l2_cache_secure(void)
	437	{
	438	if (get_device_type() == GP_DEVICE) {
	439	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
	440	0);
	441	} else {
	442	struct emu_hal_params emu_romcode_params;
	443	emu_romcode_params.num_params = 1;
	444	emu_romcode_params.param1 = 0;
	445	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	446	(u32 *)&emu_romcode_params);
	447	}
	448	}
	449
	450	void v7_outer_cache_enable(void)
	451	{
	452	/* Set L2EN */
	453	omap3_update_aux_cr_secure(0x2, 0);
	454
	455	/*
	456	* On some revisions L2EN bit is banked on some revisions it's not
	457	* No harm in setting both banked bits(in fact this is required
	458	* by an erratum)
	459	*/
	460	omap3_update_aux_cr(0x2, 0);
	461	}
	462
f1f2c3ca	463	void omap3_outer_cache_disable(void)
45bf0585 A	464	{
	465	/* Clear L2EN */
	466	omap3_update_aux_cr_secure(0, 0x2);
	467
	468	/*
	469	* On some revisions L2EN bit is banked on some revisions it's not
	470	* No harm in clearing both banked bits(in fact this is required
	471	* by an erratum)
	472	*/
	473	omap3_update_aux_cr(0, 0x2);
	474	}
	475	#endif
13d4f9bd A	476
	477	#ifndef CONFIG_SYS_DCACHE_OFF
	478	void enable_caches(void)
	479	{
	480	/* Enable D-cache. I-cache is already enabled in start.S */
	481	dcache_enable();
	482	}
	483	#endif