[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Initial Code by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <khasim@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>

_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */

.global omap3_gp_romcode_call
omap3_gp_romcode_call:
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Service ID in R12
	MOV r0, r1	@ Copy parameter to R0
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}

/*
 * Funtion for making PPA HAL API calls in secure devices
 * Input:
 *	R0 - Service ID
 *	R1 - paramer list
 */
.global do_omap3_emu_romcode_call
do_omap3_emu_romcode_call:
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Secure Service ID in R12
	MOV r3, r1	@ Copy the pointer to va_list in R3
	MOV r1, #0	@ Process ID - 0
	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
							@ to va_list in R3
	MOV r6, #0xFF	@ Indicate new Task call
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}

#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
 * R1 = SRAM destination address.
 *************************************************************************/
.global cpy_clk_code
 cpy_clk_code:
	/* Copy DPLL code into SRAM */
	adr	r0, go_to_speed		/* get addr of clock setting code */
	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
	mov	r1, r1			/* r1 <- dest address (passed in) */
	add	r2, r2, r0		/* r2 <- source end address */
next2:
	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
	cmp	r0, r2			/* until source end address [r2] */
	bne	next2
	mov	pc, lr			/* back to caller */

/* ***************************************************************************
 *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
 *               -executed from SRAM.
 *  R0 = CM_CLKEN_PLL-bypass value
 *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
 *  R2 = CM_CLKSEL_CORE-divider values
 *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
 *
 *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
 *        confused.  A reset of the controller gets it back.  Taking away its
 *        L3 when its not in self refresh seems bad for it.  Normally, this
 *	  code runs from flash before SDR is init so that should be ok.
 ****************************************************************************/
.global go_to_speed
 go_to_speed:
	stmfd sp!, {r4 - r6}

	/* move into fast relock bypass */
	ldr	r4, pll_ctl_add
	str	r0, [r4]
wait1:
	ldr	r5, [r3]		/* get status */
	and	r5, r5, #0x1		/* isolate core status */
	cmp	r5, #0x1		/* still locked? */
	beq	wait1			/* if lock, loop */

	/* set new dpll dividers _after_ in bypass */
	ldr	r5, pll_div_add1
	str	r1, [r5]		/* set m, n, m2 */
	ldr	r5, pll_div_add2
	str	r2, [r5]		/* set l3/l4/.. dividers*/
	ldr	r5, pll_div_add3	/* wkup */
	ldr	r2, pll_div_val3	/* rsm val */
	str	r2, [r5]
	ldr	r5, pll_div_add4	/* gfx */
	ldr	r2, pll_div_val4
	str	r2, [r5]
	ldr	r5, pll_div_add5	/* emu */
	ldr	r2, pll_div_val5
	str	r2, [r5]

	/* now prepare GPMC (flash) for new dpll speed */
	/* flash needs to be stable when we jump back to it */
	ldr	r5, flash_cfg3_addr
	ldr	r2, flash_cfg3_val
	str	r2, [r5]
	ldr	r5, flash_cfg4_addr
	ldr	r2, flash_cfg4_val
	str	r2, [r5]
	ldr	r5, flash_cfg5_addr
	ldr	r2, flash_cfg5_val
	str	r2, [r5]
	ldr	r5, flash_cfg1_addr
	ldr	r2, [r5]
	orr	r2, r2, #0x3		/* up gpmc divider */
	str	r2, [r5]

	/* lock DPLL3 and wait a bit */
	orr	r0, r0, #0x7	/* set up for lock mode */
	str	r0, [r4]	/* lock */
	nop			/* ARM slow at this point working at sys_clk */
	nop
	nop
	nop
wait2:
	ldr	r5, [r3]	/* get status */
	and	r5, r5, #0x1	/* isolate core status */
	cmp	r5, #0x1	/* still locked? */
	bne	wait2		/* if lock, loop */
	nop
	nop
	nop
	nop
	ldmfd	sp!, {r4 - r6}
	mov	pc, lr		/* back to caller, locked */

_go_to_speed: .word go_to_speed

/* these constants need to be close for PIC code */
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
flash_cfg1_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
flash_cfg3_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
flash_cfg3_val:
	.word STNOR_GPMC_CONFIG3
flash_cfg4_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
flash_cfg4_val:
	.word STNOR_GPMC_CONFIG4
flash_cfg5_val:
	.word STNOR_GPMC_CONFIG5
flash_cfg5_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
pll_ctl_add:
	.word CM_CLKEN_PLL
pll_div_add1:
	.word CM_CLKSEL1_PLL
pll_div_add2:
	.word CM_CLKSEL_CORE
pll_div_add3:
	.word CM_CLKSEL_WKUP
pll_div_val3:
	.word (WKUP_RSM << 1)
pll_div_add4:
	.word CM_CLKSEL_GFX
pll_div_val4:
	.word (GFX_DIV << 0)
pll_div_add5:
	.word CM_CLKSEL1_EMU
pll_div_val5:
	.word CLSEL1_EMU_VAL

#endif

.globl lowlevel_init
lowlevel_init:
	ldr	sp, SRAM_STACK
	str	ip, [sp]	/* stash old link register */
	mov	ip, lr		/* save link reg across call */
	bl	s_init		/* go setup pll, mux, memory */
	ldr	ip, [sp]	/* restore save ip */
	mov	lr, ip		/* restore link reg */

	/* back to arch calling code */
	mov	pc, lr

	/* the literal pools origin */
	.ltorg

REG_CONTROL_STATUS:
	.word CONTROL_STATUS
SRAM_STACK:
	.word LOW_LEVEL_SRAM_STACK

/* DPLL(1-4) PARAM TABLES */

/*
 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
 * The values are defined for all possible sysclk and for ES1 and ES2.
 */

mpu_dpll_param:
/* 12MHz */
/* ES1 */
.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
/* ES2 */
.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
/* 3410 */
.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12

/* 13MHz */
/* ES1 */
.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
/* ES2 */
.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
/* 3410 */
.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13

/* 19.2MHz */
/* ES1 */
.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
/* ES2 */
.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
/* 3410 */
.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2

/* 26MHz */
/* ES1 */
.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
/* ES2 */
.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
/* 3410 */
.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26

/* 38.4MHz */
/* ES1 */
.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
/* ES2 */
.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
/* 3410 */
.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4


.globl get_mpu_dpll_param
get_mpu_dpll_param:
	adr	r0, mpu_dpll_param
	mov	pc, lr

iva_dpll_param:
/* 12MHz */
/* ES1 */
.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
/* ES2 */
.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
/* 3410 */
.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12

/* 13MHz */
/* ES1 */
.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
/* ES2 */
.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
/* 3410 */
.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13

/* 19.2MHz */
/* ES1 */
.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
/* ES2 */
.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
/* 3410 */
.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2

/* 26MHz */
/* ES1 */
.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
/* ES2 */
.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
/* 3410 */
.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26

/* 38.4MHz */
/* ES1 */
.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
/* ES2 */
.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
/* 3410 */
.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4


.globl get_iva_dpll_param
get_iva_dpll_param:
	adr	r0, iva_dpll_param
	mov	pc, lr

/* Core DPLL targets for L3 at 166 & L133 */
core_dpll_param:
/* 12MHz */
/* ES1 */
.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
/* ES2 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
/* 3410 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12

/* 13MHz */
/* ES1 */
.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
/* ES2 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
/* 3410 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13

/* 19.2MHz */
/* ES1 */
.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
/* ES2 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
/* 3410 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2

/* 26MHz */
/* ES1 */
.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
/* ES2 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
/* 3410 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26

/* 38.4MHz */
/* ES1 */
.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
/* ES2 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
/* 3410 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4

.globl get_core_dpll_param
get_core_dpll_param:
	adr	r0, core_dpll_param
	mov	pc, lr

/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
/* 12MHz */
.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12

/* 13MHz */
.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13

/* 19.2MHz */
.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2

/* 26MHz */
.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26

/* 38.4MHz */
.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4

.globl get_per_dpll_param
get_per_dpll_param:
	adr	r0, per_dpll_param
	mov	pc, lr

/* PER2 DPLL values */
per2_dpll_param:
/* 12MHz */
.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12

/* 13MHz */
.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13

/* 19.2MHz */
.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2

/* 26MHz */
.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26

/* 38.4MHz */
.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4

.globl get_per2_dpll_param
get_per2_dpll_param:
	adr	r0, per2_dpll_param
	mov	pc, lr

/*
 * Tables for 36XX/37XX devices
 *
 */
mpu_36x_dpll_param:
/* 12MHz */
.word 50, 0, 0, 1
/* 13MHz */
.word 600, 12, 0, 1
/* 19.2MHz */
.word 125, 3, 0, 1
/* 26MHz */
.word 300, 12, 0, 1
/* 38.4MHz */
.word 125, 7, 0, 1

iva_36x_dpll_param:
/* 12MHz */
.word 130, 2, 0, 1
/* 13MHz */
.word 20, 0, 0, 1
/* 19.2MHz */
.word 325, 11, 0, 1
/* 26MHz */
.word 10, 0, 0, 1
/* 38.4MHz */
.word 325, 23, 0, 1

core_36x_dpll_param:
/* 12MHz */
.word 100, 2, 0, 1
/* 13MHz */
.word 400, 12, 0, 1
/* 19.2MHz */
.word 375, 17, 0, 1
/* 26MHz */
.word 200, 12, 0, 1
/* 38.4MHz */
.word 375, 35, 0, 1

per_36x_dpll_param:
/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
.word 38400,    360,   15,     9,      16,     5,     4,      3,      1

.globl get_36x_mpu_dpll_param
get_36x_mpu_dpll_param:
	adr	r0, mpu_36x_dpll_param
	mov	pc, lr

.globl get_36x_iva_dpll_param
get_36x_iva_dpll_param:
	adr	r0, iva_36x_dpll_param
	mov	pc, lr

.globl get_36x_core_dpll_param
get_36x_core_dpll_param:
	adr	r0, core_36x_dpll_param
	mov	pc, lr

.globl get_36x_per_dpll_param
get_36x_per_dpll_param:
	adr	r0, per_36x_dpll_param
	mov	pc, lr
Commit	Line	Data
5ed3e865 DB	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2008
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* Initial Code by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Syed Mohammed Khasim <khasim@ti.com>
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	#include <config.h>
	31	#include <version.h>
	32	#include <asm/arch/mem.h>
	33	#include <asm/arch/clocks_omap3.h>
	34
	35	_TEXT_BASE:
14d0a02a	36	.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
5ed3e865	37
45bf0585 A	38	.global omap3_gp_romcode_call
	39	omap3_gp_romcode_call:
	40	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	41	MOV r12, r0 @ Copy the Service ID in R12
	42	MOV r0, r1 @ Copy parameter to R0
	43	mcr p15, 0, r0, c7, c10, 4 @ DSB
	44	mcr p15, 0, r0, c7, c10, 5 @ DMB
	45	.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
	46	@ because we use -march=armv5
	47	POP {r4-r12, pc}
	48
	49	/*
	50	* Funtion for making PPA HAL API calls in secure devices
	51	* Input:
	52	* R0 - Service ID
	53	* R1 - paramer list
	54	*/
	55	.global do_omap3_emu_romcode_call
	56	do_omap3_emu_romcode_call:
	57	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	58	MOV r12, r0 @ Copy the Secure Service ID in R12
	59	MOV r3, r1 @ Copy the pointer to va_list in R3
	60	MOV r1, #0 @ Process ID - 0
	61	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
	62	@ to va_list in R3
	63	MOV r6, #0xFF @ Indicate new Task call
	64	mcr p15, 0, r0, c7, c10, 4 @ DSB
	65	mcr p15, 0, r0, c7, c10, 5 @ DMB
	66	.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
	67	@ because we use -march=armv5
	68	POP {r4-r12, pc}
	69
5ed3e865 DB	70	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
	71	/**************************************************************************
	72	* cpy_clk_code: relocates clock code into SRAM where its safer to execute
	73	* R1 = SRAM destination address.
	74	*************************************************************************/
	75	.global cpy_clk_code
	76	cpy_clk_code:
	77	/* Copy DPLL code into SRAM */
	78	adr r0, go_to_speed /* get addr of clock setting code */
	79	mov r2, #384 /* r2 size to copy (div by 32 bytes) */
	80	mov r1, r1 /* r1 <- dest address (passed in) */
	81	add r2, r2, r0 /* r2 <- source end address */
	82	next2:
	83	ldmia r0!, {r3 - r10} /* copy from source address [r0] */
	84	stmia r1!, {r3 - r10} /* copy to target address [r1] */
	85	cmp r0, r2 /* until source end address [r2] */
	86	bne next2
	87	mov pc, lr /* back to caller */
	88
	89	/* ***************************************************************************
	90	* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
	91	* -executed from SRAM.
	92	* R0 = CM_CLKEN_PLL-bypass value
	93	* R1 = CM_CLKSEL1_PLL-m, n, and divider values
	94	* R2 = CM_CLKSEL_CORE-divider values
	95	* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
	96	*
	97	* Note: If core unlocks/relocks and SDRAM is running fast already it gets
	98	* confused. A reset of the controller gets it back. Taking away its
	99	* L3 when its not in self refresh seems bad for it. Normally, this
	100	* code runs from flash before SDR is init so that should be ok.
	101	****************************************************************************/
	102	.global go_to_speed
	103	go_to_speed:
	104	stmfd sp!, {r4 - r6}
	105
	106	/* move into fast relock bypass */
	107	ldr r4, pll_ctl_add
	108	str r0, [r4]
	109	wait1:
	110	ldr r5, [r3] /* get status */
	111	and r5, r5, #0x1 /* isolate core status */
	112	cmp r5, #0x1 /* still locked? */
	113	beq wait1 /* if lock, loop */
	114
	115	/* set new dpll dividers _after_ in bypass */
	116	ldr r5, pll_div_add1
	117	str r1, [r5] /* set m, n, m2 */
	118	ldr r5, pll_div_add2
	119	str r2, [r5] /* set l3/l4/.. dividers*/
	120	ldr r5, pll_div_add3 /* wkup */
	121	ldr r2, pll_div_val3 /* rsm val */
	122	str r2, [r5]
	123	ldr r5, pll_div_add4 /* gfx */
	124	ldr r2, pll_div_val4
	125	str r2, [r5]
	126	ldr r5, pll_div_add5 /* emu */
	127	ldr r2, pll_div_val5
	128	str r2, [r5]
	129
	130	/* now prepare GPMC (flash) for new dpll speed */
	131	/* flash needs to be stable when we jump back to it */
	132	ldr r5, flash_cfg3_addr
	133	ldr r2, flash_cfg3_val
134	str r2, [r5]
135	ldr r5, flash_cfg4_addr
136	ldr r2, flash_cfg4_val
137	str r2, [r5]
138	ldr r5, flash_cfg5_addr
139	ldr r2, flash_cfg5_val
140	str r2, [r5]
141	ldr r5, flash_cfg1_addr
142	ldr r2, [r5]
143	orr r2, r2, #0x3 /* up gpmc divider */
144	str r2, [r5]
145
146	/* lock DPLL3 and wait a bit */
147	orr r0, r0, #0x7 /* set up for lock mode */
148	str r0, [r4] /* lock */
149	nop /* ARM slow at this point working at sys_clk */
150	nop
151	nop
152	nop
153	wait2:
154	ldr r5, [r3] /* get status */
155	and r5, r5, #0x1 /* isolate core status */
156	cmp r5, #0x1 /* still locked? */
157	bne wait2 /* if lock, loop */
158	nop
159	nop
160	nop
161	nop
162	ldmfd sp!, {r4 - r6}
163	mov pc, lr /* back to caller, locked */
164
165	_go_to_speed: .word go_to_speed
166
167	/* these constants need to be close for PIC code */
168	/* The Nor has to be in the Flash Base CS0 for this condition to happen */
169	flash_cfg1_addr:
3b9043a7	170	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
5ed3e865	171	flash_cfg3_addr:
3b9043a7	172	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
5ed3e865 DB	173	flash_cfg3_val:
	174	.word STNOR_GPMC_CONFIG3
	175	flash_cfg4_addr:
3b9043a7	176	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
5ed3e865 DB	177	flash_cfg4_val:
	178	.word STNOR_GPMC_CONFIG4
	179	flash_cfg5_val:
	180	.word STNOR_GPMC_CONFIG5
	181	flash_cfg5_addr:
3b9043a7	182	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
5ed3e865 DB	183	pll_ctl_add:
	184	.word CM_CLKEN_PLL
	185	pll_div_add1:
	186	.word CM_CLKSEL1_PLL
	187	pll_div_add2:
	188	.word CM_CLKSEL_CORE
	189	pll_div_add3:
	190	.word CM_CLKSEL_WKUP
	191	pll_div_val3:
	192	.word (WKUP_RSM << 1)
	193	pll_div_add4:
	194	.word CM_CLKSEL_GFX
	195	pll_div_val4:
	196	.word (GFX_DIV << 0)
	197	pll_div_add5:
	198	.word CM_CLKSEL1_EMU
	199	pll_div_val5:
	200	.word CLSEL1_EMU_VAL
	201
	202	#endif
	203
	204	.globl lowlevel_init
	205	lowlevel_init:
	206	ldr sp, SRAM_STACK
	207	str ip, [sp] /* stash old link register */
	208	mov ip, lr /* save link reg across call */
	209	bl s_init /* go setup pll, mux, memory */
	210	ldr ip, [sp] /* restore save ip */
	211	mov lr, ip /* restore link reg */
	212
	213	/* back to arch calling code */
	214	mov pc, lr
	215
	216	/* the literal pools origin */
	217	.ltorg
	218
	219	REG_CONTROL_STATUS:
	220	.word CONTROL_STATUS
	221	SRAM_STACK:
	222	.word LOW_LEVEL_SRAM_STACK
	223
	224	/* DPLL(1-4) PARAM TABLES */
	225
	226	/*
	227	* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
	228	* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
	229	* The values are defined for all possible sysclk and for ES1 and ES2.
	230	*/
	231
	232	mpu_dpll_param:
	233	/* 12MHz */
	234	/* ES1 */
	235	.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
	236	/* ES2 */
	237	.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
	238	/* 3410 */
	239	.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
	240
	241	/* 13MHz */
	242	/* ES1 */
	243	.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
	244	/* ES2 */
	245	.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
	246	/* 3410 */
247	.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
248
249	/* 19.2MHz */
250	/* ES1 */
251	.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
252	/* ES2 */
253	.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
254	/* 3410 */
255	.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
256
257	/* 26MHz */
258	/* ES1 */
259	.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
260	/* ES2 */
261	.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
262	/* 3410 */
263	.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
264
265	/* 38.4MHz */
266	/* ES1 */
267	.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
268	/* ES2 */
269	.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
270	/* 3410 */
271	.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
272
273
274	.globl get_mpu_dpll_param
275	get_mpu_dpll_param:
276	adr r0, mpu_dpll_param
277	mov pc, lr
278
279	iva_dpll_param:
280	/* 12MHz */
281	/* ES1 */
282	.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
283	/* ES2 */
284	.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
285	/* 3410 */
286	.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
287
288	/* 13MHz */
289	/* ES1 */
290	.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
291	/* ES2 */
292	.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
293	/* 3410 */
294	.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
295
296	/* 19.2MHz */
297	/* ES1 */
298	.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
299	/* ES2 */
300	.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
301	/* 3410 */
302	.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
303
304	/* 26MHz */
305	/* ES1 */
306	.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
307	/* ES2 */
308	.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
309	/* 3410 */
310	.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
311
312	/* 38.4MHz */
313	/* ES1 */
314	.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
315	/* ES2 */
316	.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
317	/* 3410 */
318	.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
319
320
321	.globl get_iva_dpll_param
322	get_iva_dpll_param:
323	adr r0, iva_dpll_param
324	mov pc, lr
325
326	/* Core DPLL targets for L3 at 166 & L133 */
327	core_dpll_param:
328	/* 12MHz */
329	/* ES1 */
330	.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
331	/* ES2 */
332	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
333	/* 3410 */
334	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
335
336	/* 13MHz */
337	/* ES1 */
338	.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
339	/* ES2 */
340	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
341	/* 3410 */
342	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
343
344	/* 19.2MHz */
345	/* ES1 */
346	.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
347	/* ES2 */
348	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
349	/* 3410 */
350	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
351
352	/* 26MHz */
353	/* ES1 */
354	.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
355	/* ES2 */
356	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
357	/* 3410 */
358	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
359
360	/* 38.4MHz */
361	/* ES1 */
362	.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
363	/* ES2 */
364	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
365	/* 3410 */
366	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
367
368	.globl get_core_dpll_param
369	get_core_dpll_param:
370	adr r0, core_dpll_param
371	mov pc, lr
372
373	/* PER DPLL values are same for both ES1 and ES2 */
374	per_dpll_param:
375	/* 12MHz */
376	.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
377
378	/* 13MHz */
379	.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
380
381	/* 19.2MHz */
382	.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
383
384	/* 26MHz */
385	.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
386
387	/* 38.4MHz */
388	.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
389
390	.globl get_per_dpll_param
391	get_per_dpll_param:
392	adr r0, per_dpll_param
393	mov pc, lr
7c281c98	394
7b89795f AH	395	/* PER2 DPLL values */
	396	per2_dpll_param:
	397	/* 12MHz */
	398	.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
	399
	400	/* 13MHz */
	401	.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
	402
	403	/* 19.2MHz */
	404	.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
	405
	406	/* 26MHz */
	407	.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
	408
	409	/* 38.4MHz */
	410	.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
	411
	412	.globl get_per2_dpll_param
	413	get_per2_dpll_param:
	414	adr r0, per2_dpll_param
	415	mov pc, lr
	416
7c281c98 SS	417	/*
	418	* Tables for 36XX/37XX devices
	419	*
	420	*/
	421	mpu_36x_dpll_param:
	422	/* 12MHz */
	423	.word 50, 0, 0, 1
	424	/* 13MHz */
	425	.word 600, 12, 0, 1
	426	/* 19.2MHz */
	427	.word 125, 3, 0, 1
	428	/* 26MHz */
	429	.word 300, 12, 0, 1
	430	/* 38.4MHz */
	431	.word 125, 7, 0, 1
	432
	433	iva_36x_dpll_param:
	434	/* 12MHz */
	435	.word 130, 2, 0, 1
	436	/* 13MHz */
	437	.word 20, 0, 0, 1
	438	/* 19.2MHz */
	439	.word 325, 11, 0, 1
	440	/* 26MHz */
	441	.word 10, 0, 0, 1
	442	/* 38.4MHz */
	443	.word 325, 23, 0, 1
	444
	445	core_36x_dpll_param:
	446	/* 12MHz */
	447	.word 100, 2, 0, 1
	448	/* 13MHz */
	449	.word 400, 12, 0, 1
	450	/* 19.2MHz */
	451	.word 375, 17, 0, 1
	452	/* 26MHz */
	453	.word 200, 12, 0, 1
	454	/* 38.4MHz */
	455	.word 375, 35, 0, 1
	456
	457	per_36x_dpll_param:
	458	/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
	459	.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
	460	.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
	461	.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
	462	.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
	463	.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
	464
	465	.globl get_36x_mpu_dpll_param
	466	get_36x_mpu_dpll_param:
	467	adr r0, mpu_36x_dpll_param
	468	mov pc, lr
	469
	470	.globl get_36x_iva_dpll_param
	471	get_36x_iva_dpll_param:
	472	adr r0, iva_36x_dpll_param
	473	mov pc, lr
	474
	475	.globl get_36x_core_dpll_param
	476	get_36x_core_dpll_param:
	477	adr r0, core_36x_dpll_param
	478	mov pc, lr
	479
	480	.globl get_36x_per_dpll_param
481	get_36x_per_dpll_param:
482	adr r0, per_36x_dpll_param
483	mov pc, lr