[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / lowlevel_init.S

/*
 * Board specific setup info
 *
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Initial Code by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <version.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks_omap3.h>
#include <linux/linkage.h>

_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */

#ifdef CONFIG_SPL_BUILD
ENTRY(save_boot_params)
	ldr	r4, =omap3_boot_device
	ldr	r5, [r0, #0x4]
	and	r5, r5, #0xff
	str	r5, [r4]
	bx	lr
ENDPROC(save_boot_params)
#endif

ENTRY(omap3_gp_romcode_call)
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Service ID in R12
	MOV r0, r1	@ Copy parameter to R0
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600070	@ SMC #0 to enter monitor - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}
ENDPROC(omap3_gp_romcode_call)

/*
 * Funtion for making PPA HAL API calls in secure devices
 * Input:
 *	R0 - Service ID
 *	R1 - paramer list
 */
ENTRY(do_omap3_emu_romcode_call)
	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	MOV r12, r0	@ Copy the Secure Service ID in R12
	MOV r3, r1	@ Copy the pointer to va_list in R3
	MOV r1, #0	@ Process ID - 0
	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
							@ to va_list in R3
	MOV r6, #0xFF	@ Indicate new Task call
	mcr     p15, 0, r0, c7, c10, 4	@ DSB
	mcr     p15, 0, r0, c7, c10, 5	@ DMB
	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
				@ because we use -march=armv5
	POP {r4-r12, pc}
ENDPROC(do_omap3_emu_romcode_call)

#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
/**************************************************************************
 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
 * R1 = SRAM destination address.
 *************************************************************************/
ENTRY(cpy_clk_code)
	/* Copy DPLL code into SRAM */
	adr	r0, go_to_speed		/* get addr of clock setting code */
	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
	mov	r1, r1			/* r1 <- dest address (passed in) */
	add	r2, r2, r0		/* r2 <- source end address */
next2:
	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
	cmp	r0, r2			/* until source end address [r2] */
	bne	next2
	mov	pc, lr			/* back to caller */
ENDPROC(cpy_clk_code)

/* ***************************************************************************
 *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
 *               -executed from SRAM.
 *  R0 = CM_CLKEN_PLL-bypass value
 *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
 *  R2 = CM_CLKSEL_CORE-divider values
 *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
 *
 *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
 *        confused.  A reset of the controller gets it back.  Taking away its
 *        L3 when its not in self refresh seems bad for it.  Normally, this
 *	  code runs from flash before SDR is init so that should be ok.
 ****************************************************************************/
ENTRY(go_to_speed)
	stmfd sp!, {r4 - r6}

	/* move into fast relock bypass */
	ldr	r4, pll_ctl_add
	str	r0, [r4]
wait1:
	ldr	r5, [r3]		/* get status */
	and	r5, r5, #0x1		/* isolate core status */
	cmp	r5, #0x1		/* still locked? */
	beq	wait1			/* if lock, loop */

	/* set new dpll dividers _after_ in bypass */
	ldr	r5, pll_div_add1
	str	r1, [r5]		/* set m, n, m2 */
	ldr	r5, pll_div_add2
	str	r2, [r5]		/* set l3/l4/.. dividers*/
	ldr	r5, pll_div_add3	/* wkup */
	ldr	r2, pll_div_val3	/* rsm val */
	str	r2, [r5]
	ldr	r5, pll_div_add4	/* gfx */
	ldr	r2, pll_div_val4
	str	r2, [r5]
	ldr	r5, pll_div_add5	/* emu */
	ldr	r2, pll_div_val5
	str	r2, [r5]

	/* now prepare GPMC (flash) for new dpll speed */
	/* flash needs to be stable when we jump back to it */
	ldr	r5, flash_cfg3_addr
	ldr	r2, flash_cfg3_val
	str	r2, [r5]
	ldr	r5, flash_cfg4_addr
	ldr	r2, flash_cfg4_val
	str	r2, [r5]
	ldr	r5, flash_cfg5_addr
	ldr	r2, flash_cfg5_val
	str	r2, [r5]
	ldr	r5, flash_cfg1_addr
	ldr	r2, [r5]
	orr	r2, r2, #0x3		/* up gpmc divider */
	str	r2, [r5]

	/* lock DPLL3 and wait a bit */
	orr	r0, r0, #0x7	/* set up for lock mode */
	str	r0, [r4]	/* lock */
	nop			/* ARM slow at this point working at sys_clk */
	nop
	nop
	nop
wait2:
	ldr	r5, [r3]	/* get status */
	and	r5, r5, #0x1	/* isolate core status */
	cmp	r5, #0x1	/* still locked? */
	bne	wait2		/* if lock, loop */
	nop
	nop
	nop
	nop
	ldmfd	sp!, {r4 - r6}
	mov	pc, lr		/* back to caller, locked */
ENDPROC(go_to_speed)

_go_to_speed: .word go_to_speed

/* these constants need to be close for PIC code */
/* The Nor has to be in the Flash Base CS0 for this condition to happen */
flash_cfg1_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
flash_cfg3_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
flash_cfg3_val:
	.word STNOR_GPMC_CONFIG3
flash_cfg4_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
flash_cfg4_val:
	.word STNOR_GPMC_CONFIG4
flash_cfg5_val:
	.word STNOR_GPMC_CONFIG5
flash_cfg5_addr:
	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
pll_ctl_add:
	.word CM_CLKEN_PLL
pll_div_add1:
	.word CM_CLKSEL1_PLL
pll_div_add2:
	.word CM_CLKSEL_CORE
pll_div_add3:
	.word CM_CLKSEL_WKUP
pll_div_val3:
	.word (WKUP_RSM << 1)
pll_div_add4:
	.word CM_CLKSEL_GFX
pll_div_val4:
	.word (GFX_DIV << 0)
pll_div_add5:
	.word CM_CLKSEL1_EMU
pll_div_val5:
	.word CLSEL1_EMU_VAL

#endif

ENTRY(lowlevel_init)
	ldr	sp, SRAM_STACK
	str	ip, [sp]	/* stash ip register */
	mov	ip, lr		/* save link reg across call */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/*
 * No need to copy/exec the clock code - DPLL adjust already done
 * in NAND/oneNAND Boot.
 */
	ldr	r1, =SRAM_CLK_CODE
	bl	cpy_clk_code
#endif /* NAND Boot */
	mov	lr, ip		/* restore link reg */
	ldr	ip, [sp]	/* restore save ip */
	/* tail-call s_init to setup pll, mux, memory */
	b	s_init

ENDPROC(lowlevel_init)

	/* the literal pools origin */
	.ltorg

REG_CONTROL_STATUS:
	.word CONTROL_STATUS
SRAM_STACK:
	.word LOW_LEVEL_SRAM_STACK

/* DPLL(1-4) PARAM TABLES */

/*
 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
 * The values are defined for all possible sysclk and for ES1 and ES2.
 */

mpu_dpll_param:
/* 12MHz */
/* ES1 */
.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
/* ES2 */
.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
/* 3410 */
.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12

/* 13MHz */
/* ES1 */
.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
/* ES2 */
.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
/* 3410 */
.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13

/* 19.2MHz */
/* ES1 */
.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
/* ES2 */
.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
/* 3410 */
.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2

/* 26MHz */
/* ES1 */
.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
/* ES2 */
.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
/* 3410 */
.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26

/* 38.4MHz */
/* ES1 */
.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
/* ES2 */
.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
/* 3410 */
.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4


.globl get_mpu_dpll_param
get_mpu_dpll_param:
	adr	r0, mpu_dpll_param
	mov	pc, lr

iva_dpll_param:
/* 12MHz */
/* ES1 */
.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
/* ES2 */
.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
/* 3410 */
.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12

/* 13MHz */
/* ES1 */
.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
/* ES2 */
.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
/* 3410 */
.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13

/* 19.2MHz */
/* ES1 */
.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
/* ES2 */
.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
/* 3410 */
.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2

/* 26MHz */
/* ES1 */
.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
/* ES2 */
.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
/* 3410 */
.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26

/* 38.4MHz */
/* ES1 */
.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
/* ES2 */
.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
/* 3410 */
.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4


.globl get_iva_dpll_param
get_iva_dpll_param:
	adr	r0, iva_dpll_param
	mov	pc, lr

/* Core DPLL targets for L3 at 166 & L133 */
core_dpll_param:
/* 12MHz */
/* ES1 */
.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
/* ES2 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
/* 3410 */
.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12

/* 13MHz */
/* ES1 */
.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
/* ES2 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
/* 3410 */
.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13

/* 19.2MHz */
/* ES1 */
.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
/* ES2 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
/* 3410 */
.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2

/* 26MHz */
/* ES1 */
.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
/* ES2 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
/* 3410 */
.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26

/* 38.4MHz */
/* ES1 */
.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
/* ES2 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
/* 3410 */
.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4

.globl get_core_dpll_param
get_core_dpll_param:
	adr	r0, core_dpll_param
	mov	pc, lr

/* PER DPLL values are same for both ES1 and ES2 */
per_dpll_param:
/* 12MHz */
.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12

/* 13MHz */
.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13

/* 19.2MHz */
.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2

/* 26MHz */
.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26

/* 38.4MHz */
.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4

.globl get_per_dpll_param
get_per_dpll_param:
	adr	r0, per_dpll_param
	mov	pc, lr

/* PER2 DPLL values */
per2_dpll_param:
/* 12MHz */
.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12

/* 13MHz */
.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13

/* 19.2MHz */
.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2

/* 26MHz */
.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26

/* 38.4MHz */
.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4

.globl get_per2_dpll_param
get_per2_dpll_param:
	adr	r0, per2_dpll_param
	mov	pc, lr

/*
 * Tables for 36XX/37XX devices
 *
 */
mpu_36x_dpll_param:
/* 12MHz */
.word 50, 0, 0, 1
/* 13MHz */
.word 600, 12, 0, 1
/* 19.2MHz */
.word 125, 3, 0, 1
/* 26MHz */
.word 300, 12, 0, 1
/* 38.4MHz */
.word 125, 7, 0, 1

iva_36x_dpll_param:
/* 12MHz */
.word 130, 2, 0, 1
/* 13MHz */
.word 20, 0, 0, 1
/* 19.2MHz */
.word 325, 11, 0, 1
/* 26MHz */
.word 10, 0, 0, 1
/* 38.4MHz */
.word 325, 23, 0, 1

core_36x_dpll_param:
/* 12MHz */
.word 100, 2, 0, 1
/* 13MHz */
.word 400, 12, 0, 1
/* 19.2MHz */
.word 375, 17, 0, 1
/* 26MHz */
.word 200, 12, 0, 1
/* 38.4MHz */
.word 375, 35, 0, 1

per_36x_dpll_param:
/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
.word 38400,    360,   15,     9,      16,     5,     4,      3,      1

ENTRY(get_36x_mpu_dpll_param)
	adr	r0, mpu_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_mpu_dpll_param)

ENTRY(get_36x_iva_dpll_param)
	adr	r0, iva_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_iva_dpll_param)

ENTRY(get_36x_core_dpll_param)
	adr	r0, core_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_core_dpll_param)

ENTRY(get_36x_per_dpll_param)
	adr	r0, per_36x_dpll_param
	mov	pc, lr
ENDPROC(get_36x_per_dpll_param)
Commit	Line	Data
5ed3e865 DB	1	/*
	2	* Board specific setup info
	3	*
	4	* (C) Copyright 2008
	5	* Texas Instruments, <www.ti.com>
	6	*
	7	* Initial Code by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Syed Mohammed Khasim <khasim@ti.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
5ed3e865 DB	12	*/
	13
	14	#include <config.h>
	15	#include <version.h>
	16	#include <asm/arch/mem.h>
	17	#include <asm/arch/clocks_omap3.h>
74236aca	18	#include <linux/linkage.h>
5ed3e865 DB	19
5ed3e865 DB	20	_TEXT_BASE:
14d0a02a	21	.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
5ed3e865	22
20470511	23	#ifdef CONFIG_SPL_BUILD
74236aca	24	ENTRY(save_boot_params)
409ef1bc SS	25	ldr r4, =omap3_boot_device
	26	ldr r5, [r0, #0x4]
	27	and r5, r5, #0xff
	28	str r5, [r4]
409ef1bc	29	bx lr
74236aca	30	ENDPROC(save_boot_params)
20470511	31	#endif
78ce9779	32
74236aca	33	ENTRY(omap3_gp_romcode_call)
45bf0585 A	34	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	35	MOV r12, r0 @ Copy the Service ID in R12
	36	MOV r0, r1 @ Copy parameter to R0
	37	mcr p15, 0, r0, c7, c10, 4 @ DSB
	38	mcr p15, 0, r0, c7, c10, 5 @ DMB
	39	.word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
	40	@ because we use -march=armv5
	41	POP {r4-r12, pc}
74236aca	42	ENDPROC(omap3_gp_romcode_call)
45bf0585 A	43
	44	/*
	45	* Funtion for making PPA HAL API calls in secure devices
	46	* Input:
	47	* R0 - Service ID
	48	* R1 - paramer list
	49	*/
74236aca	50	ENTRY(do_omap3_emu_romcode_call)
45bf0585 A	51	PUSH {r4-r12, lr} @ Save all registers from ROM code!
	52	MOV r12, r0 @ Copy the Secure Service ID in R12
	53	MOV r3, r1 @ Copy the pointer to va_list in R3
	54	MOV r1, #0 @ Process ID - 0
	55	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
	56	@ to va_list in R3
	57	MOV r6, #0xFF @ Indicate new Task call
	58	mcr p15, 0, r0, c7, c10, 4 @ DSB
	59	mcr p15, 0, r0, c7, c10, 5 @ DMB
	60	.word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
	61	@ because we use -march=armv5
	62	POP {r4-r12, pc}
74236aca	63	ENDPROC(do_omap3_emu_romcode_call)
45bf0585	64
5ed3e865 DB	65	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
	66	/**************************************************************************
	67	* cpy_clk_code: relocates clock code into SRAM where its safer to execute
	68	* R1 = SRAM destination address.
	69	*************************************************************************/
74236aca	70	ENTRY(cpy_clk_code)
5ed3e865 DB	71	/* Copy DPLL code into SRAM */
	72	adr r0, go_to_speed /* get addr of clock setting code */
	73	mov r2, #384 /* r2 size to copy (div by 32 bytes) */
	74	mov r1, r1 /* r1 <- dest address (passed in) */
	75	add r2, r2, r0 /* r2 <- source end address */
	76	next2:
	77	ldmia r0!, {r3 - r10} /* copy from source address [r0] */
	78	stmia r1!, {r3 - r10} /* copy to target address [r1] */
	79	cmp r0, r2 /* until source end address [r2] */
	80	bne next2
	81	mov pc, lr /* back to caller */
74236aca	82	ENDPROC(cpy_clk_code)
5ed3e865 DB	83
	84	/* ***************************************************************************
	85	* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
	86	* -executed from SRAM.
	87	* R0 = CM_CLKEN_PLL-bypass value
	88	* R1 = CM_CLKSEL1_PLL-m, n, and divider values
	89	* R2 = CM_CLKSEL_CORE-divider values
	90	* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
	91	*
	92	* Note: If core unlocks/relocks and SDRAM is running fast already it gets
	93	* confused. A reset of the controller gets it back. Taking away its
	94	* L3 when its not in self refresh seems bad for it. Normally, this
	95	* code runs from flash before SDR is init so that should be ok.
	96	****************************************************************************/
74236aca	97	ENTRY(go_to_speed)
5ed3e865 DB	98	stmfd sp!, {r4 - r6}
	99
	100	/* move into fast relock bypass */
	101	ldr r4, pll_ctl_add
	102	str r0, [r4]
	103	wait1:
	104	ldr r5, [r3] /* get status */
	105	and r5, r5, #0x1 /* isolate core status */
	106	cmp r5, #0x1 /* still locked? */
	107	beq wait1 /* if lock, loop */
	108
	109	/* set new dpll dividers _after_ in bypass */
	110	ldr r5, pll_div_add1
	111	str r1, [r5] /* set m, n, m2 */
	112	ldr r5, pll_div_add2
	113	str r2, [r5] /* set l3/l4/.. dividers*/
	114	ldr r5, pll_div_add3 /* wkup */
	115	ldr r2, pll_div_val3 /* rsm val */
	116	str r2, [r5]
	117	ldr r5, pll_div_add4 /* gfx */
	118	ldr r2, pll_div_val4
	119	str r2, [r5]
	120	ldr r5, pll_div_add5 /* emu */
	121	ldr r2, pll_div_val5
	122	str r2, [r5]
	123
	124	/* now prepare GPMC (flash) for new dpll speed */
	125	/* flash needs to be stable when we jump back to it */
	126	ldr r5, flash_cfg3_addr
	127	ldr r2, flash_cfg3_val
	128	str r2, [r5]
	129	ldr r5, flash_cfg4_addr
	130	ldr r2, flash_cfg4_val
	131	str r2, [r5]
	132	ldr r5, flash_cfg5_addr
	133	ldr r2, flash_cfg5_val
	134	str r2, [r5]
	135	ldr r5, flash_cfg1_addr
	136	ldr r2, [r5]
	137	orr r2, r2, #0x3 /* up gpmc divider */
	138	str r2, [r5]
	139
	140	/* lock DPLL3 and wait a bit */
	141	orr r0, r0, #0x7 /* set up for lock mode */
	142	str r0, [r4] /* lock */
	143	nop /* ARM slow at this point working at sys_clk */
	144	nop
	145	nop
	146	nop
	147	wait2:
	148	ldr r5, [r3] /* get status */
	149	and r5, r5, #0x1 /* isolate core status */
	150	cmp r5, #0x1 /* still locked? */
	151	bne wait2 /* if lock, loop */
	152	nop
	153	nop
	154	nop
	155	nop
	156	ldmfd sp!, {r4 - r6}
	157	mov pc, lr /* back to caller, locked */
74236aca	158	ENDPROC(go_to_speed)
5ed3e865 DB	159
	160	_go_to_speed: .word go_to_speed
	161
	162	/* these constants need to be close for PIC code */
	163	/* The Nor has to be in the Flash Base CS0 for this condition to happen */
	164	flash_cfg1_addr:
3b9043a7	165	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
5ed3e865	166	flash_cfg3_addr:
3b9043a7	167	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
5ed3e865 DB	168	flash_cfg3_val:
	169	.word STNOR_GPMC_CONFIG3
	170	flash_cfg4_addr:
3b9043a7	171	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
5ed3e865 DB	172	flash_cfg4_val:
	173	.word STNOR_GPMC_CONFIG4
	174	flash_cfg5_val:
	175	.word STNOR_GPMC_CONFIG5
	176	flash_cfg5_addr:
3b9043a7	177	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
5ed3e865 DB	178	pll_ctl_add:
	179	.word CM_CLKEN_PLL
	180	pll_div_add1:
	181	.word CM_CLKSEL1_PLL
	182	pll_div_add2:
	183	.word CM_CLKSEL_CORE
	184	pll_div_add3:
	185	.word CM_CLKSEL_WKUP
	186	pll_div_val3:
	187	.word (WKUP_RSM << 1)
	188	pll_div_add4:
	189	.word CM_CLKSEL_GFX
	190	pll_div_val4:
	191	.word (GFX_DIV << 0)
	192	pll_div_add5:
	193	.word CM_CLKSEL1_EMU
	194	pll_div_val5:
	195	.word CLSEL1_EMU_VAL
	196
	197	#endif
	198
74236aca	199	ENTRY(lowlevel_init)
5ed3e865	200	ldr sp, SRAM_STACK
dec96689	201	str ip, [sp] /* stash ip register */
5ed3e865	202	mov ip, lr /* save link reg across call */
e4fce34e A	203	#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
	204	/*
	205	* No need to copy/exec the clock code - DPLL adjust already done
	206	* in NAND/oneNAND Boot.
	207	*/
	208	ldr r1, =SRAM_CLK_CODE
	209	bl cpy_clk_code
	210	#endif /* NAND Boot */
5ed3e865	211	mov lr, ip /* restore link reg */
dec96689 AA	212	ldr ip, [sp] /* restore save ip */
	213	/* tail-call s_init to setup pll, mux, memory */
	214	b s_init
5ed3e865	215
74236aca	216	ENDPROC(lowlevel_init)
5ed3e865 DB	217
	218	/* the literal pools origin */
	219	.ltorg
	220
	221	REG_CONTROL_STATUS:
	222	.word CONTROL_STATUS
	223	SRAM_STACK:
	224	.word LOW_LEVEL_SRAM_STACK
	225
	226	/* DPLL(1-4) PARAM TABLES */
	227
	228	/*
	229	* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
	230	* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
	231	* The values are defined for all possible sysclk and for ES1 and ES2.
	232	*/
	233
	234	mpu_dpll_param:
	235	/* 12MHz */
	236	/* ES1 */
	237	.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
	238	/* ES2 */
	239	.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
	240	/* 3410 */
	241	.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
	242
	243	/* 13MHz */
	244	/* ES1 */
	245	.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
	246	/* ES2 */
	247	.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
	248	/* 3410 */
	249	.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
	250
	251	/* 19.2MHz */
	252	/* ES1 */
	253	.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
	254	/* ES2 */
	255	.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
	256	/* 3410 */
	257	.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
	258
	259	/* 26MHz */
	260	/* ES1 */
	261	.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
	262	/* ES2 */
	263	.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
	264	/* 3410 */
	265	.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
	266
	267	/* 38.4MHz */
	268	/* ES1 */
	269	.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
	270	/* ES2 */
	271	.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
	272	/* 3410 */
	273	.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
	274
	275
	276	.globl get_mpu_dpll_param
	277	get_mpu_dpll_param:
	278	adr r0, mpu_dpll_param
	279	mov pc, lr
	280
281	iva_dpll_param:
282	/* 12MHz */
283	/* ES1 */
284	.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
285	/* ES2 */
286	.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
287	/* 3410 */
288	.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
289
290	/* 13MHz */
291	/* ES1 */
292	.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
293	/* ES2 */
294	.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
295	/* 3410 */
296	.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
297
298	/* 19.2MHz */
299	/* ES1 */
300	.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
301	/* ES2 */
302	.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
303	/* 3410 */
304	.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
305
306	/* 26MHz */
307	/* ES1 */
308	.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
309	/* ES2 */
310	.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
311	/* 3410 */
312	.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
313
314	/* 38.4MHz */
315	/* ES1 */
316	.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
317	/* ES2 */
318	.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
319	/* 3410 */
320	.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
321
322
323	.globl get_iva_dpll_param
324	get_iva_dpll_param:
325	adr r0, iva_dpll_param
326	mov pc, lr
327
328	/* Core DPLL targets for L3 at 166 & L133 */
329	core_dpll_param:
330	/* 12MHz */
331	/* ES1 */
332	.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
333	/* ES2 */
334	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
335	/* 3410 */
336	.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
337
338	/* 13MHz */
339	/* ES1 */
340	.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
341	/* ES2 */
342	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
343	/* 3410 */
344	.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
345
346	/* 19.2MHz */
347	/* ES1 */
348	.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
349	/* ES2 */
350	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
351	/* 3410 */
352	.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
353
354	/* 26MHz */
355	/* ES1 */
356	.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
357	/* ES2 */
358	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
359	/* 3410 */
360	.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
361
362	/* 38.4MHz */
363	/* ES1 */
364	.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
365	/* ES2 */
366	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
367	/* 3410 */
368	.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
369
370	.globl get_core_dpll_param
371	get_core_dpll_param:
372	adr r0, core_dpll_param
373	mov pc, lr
374
375	/* PER DPLL values are same for both ES1 and ES2 */
376	per_dpll_param:
377	/* 12MHz */
378	.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
379
380	/* 13MHz */
381	.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
382
383	/* 19.2MHz */
384	.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
385
386	/* 26MHz */
387	.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
388
389	/* 38.4MHz */
390	.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
391
392	.globl get_per_dpll_param
393	get_per_dpll_param:
394	adr r0, per_dpll_param
395	mov pc, lr
7c281c98	396
7b89795f AH	397	/* PER2 DPLL values */
	398	per2_dpll_param:
	399	/* 12MHz */
	400	.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
	401
	402	/* 13MHz */
	403	.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
	404
	405	/* 19.2MHz */
	406	.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
	407
	408	/* 26MHz */
	409	.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
	410
	411	/* 38.4MHz */
	412	.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
	413
	414	.globl get_per2_dpll_param
	415	get_per2_dpll_param:
	416	adr r0, per2_dpll_param
	417	mov pc, lr
	418
7c281c98 SS	419	/*
	420	* Tables for 36XX/37XX devices
	421	*
	422	*/
	423	mpu_36x_dpll_param:
	424	/* 12MHz */
	425	.word 50, 0, 0, 1
	426	/* 13MHz */
	427	.word 600, 12, 0, 1
	428	/* 19.2MHz */
	429	.word 125, 3, 0, 1
	430	/* 26MHz */
	431	.word 300, 12, 0, 1
	432	/* 38.4MHz */
	433	.word 125, 7, 0, 1
	434
	435	iva_36x_dpll_param:
	436	/* 12MHz */
	437	.word 130, 2, 0, 1
	438	/* 13MHz */
	439	.word 20, 0, 0, 1
	440	/* 19.2MHz */
	441	.word 325, 11, 0, 1
	442	/* 26MHz */
	443	.word 10, 0, 0, 1
	444	/* 38.4MHz */
	445	.word 325, 23, 0, 1
	446
	447	core_36x_dpll_param:
	448	/* 12MHz */
	449	.word 100, 2, 0, 1
	450	/* 13MHz */
	451	.word 400, 12, 0, 1
	452	/* 19.2MHz */
	453	.word 375, 17, 0, 1
	454	/* 26MHz */
	455	.word 200, 12, 0, 1
	456	/* 38.4MHz */
	457	.word 375, 35, 0, 1
	458
	459	per_36x_dpll_param:
	460	/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
	461	.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
	462	.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
	463	.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
	464	.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
	465	.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
	466
74236aca	467	ENTRY(get_36x_mpu_dpll_param)
7c281c98 SS	468	adr r0, mpu_36x_dpll_param
7c281c98 SS	469	mov pc, lr
74236aca	470	ENDPROC(get_36x_mpu_dpll_param)
7c281c98	471
74236aca	472	ENTRY(get_36x_iva_dpll_param)
7c281c98 SS	473	adr r0, iva_36x_dpll_param
7c281c98 SS	474	mov pc, lr
74236aca	475	ENDPROC(get_36x_iva_dpll_param)
7c281c98	476
74236aca	477	ENTRY(get_36x_core_dpll_param)
7c281c98 SS	478	adr r0, core_36x_dpll_param
7c281c98 SS	479	mov pc, lr
74236aca	480	ENDPROC(get_36x_core_dpll_param)
7c281c98	481
74236aca	482	ENTRY(get_36x_per_dpll_param)
7c281c98 SS	483	adr r0, per_36x_dpll_param
7c281c98 SS	484	mov pc, lr
74236aca	485	ENDPROC(get_36x_per_dpll_param)