projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4e647e12 TR |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * Texas Instruments, <www.ti.com> | |
| 4 | * | |
| 5 | * Author : | |
| 6 | * Tom Rini <trini@ti.com> | |
| 7 | * | |
| 8 | * Initial Code from: | |
| 9 | * Richard Woodruff <r-woodruff2@ti.com> | |
| 10 | * Jian Zhang <jzhang@ti.com> | |
| 11 | * | |
| 1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 4e647e12 TR |
13 | */ |
| 14 | ||
| 15 | #include <common.h> | |
| 16 | #include <linux/mtd/nand.h> | |
| 17 | #include <asm/io.h> | |
| 18 | #include <asm/arch/sys_proto.h> | |
| 19 | #include <asm/arch/mem.h> | |
| 20 | ||
| 21 | static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; | |
| 22 | ||
| 23 | /* nand_command: Send a flash command to the flash chip */ | |
| 24 | static void nand_command(u8 command) | |
| 25 | { | |
| 26 | writeb(command, &gpmc_config->cs[0].nand_cmd); | |
| 27 | ||
| 28 | if (command == NAND_CMD_RESET) { | |
| 29 | unsigned char ret_val; | |
| 30 | writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); | |
| 31 | do { | |
| 32 | /* Wait until ready */ | |
| 33 | ret_val = readl(&gpmc_config->cs[0].nand_dat); | |
| 34 | } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); | |
| 35 | } | |
| 36 | } | |
| 37 | ||
| 38 | /* | |
| 39 | * Many boards will want to know the results of the NAND_CMD_READID command | |
| 40 | * in order to decide what to do about DDR initialization. This function | |
| 41 | * allows us to do that very early and to pass those results back to the | |
| 42 | * board so it can make whatever decisions need to be made. | |
| 43 | */ | |
| 44 | void identify_nand_chip(int *mfr, int *id) | |
| 45 | { | |
| 46 | /* Make sure that we have setup GPMC for NAND correctly. */ | |
| 47 | writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); | |
| 48 | writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); | |
| 49 | writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); | |
| 50 | writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); | |
| 51 | writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); | |
| 52 | writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); | |
| 53 | ||
| 54 | /* | |
| 55 | * Enable the config. The CS size goes in bits 11:8. We set | |
| 56 | * bit 6 to enable the CS and the base address goes into bits 5:0. | |
| 57 | */ | |
| 58 | writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | | |
| 59 | ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), | |
| 60 | &gpmc_config->cs[0].config7); | |
| 61 | ||
| 62 | sdelay(2000); | |
| 63 | ||
| 64 | /* Issue a RESET and then READID */ | |
| 65 | nand_command(NAND_CMD_RESET); | |
| 66 | nand_command(NAND_CMD_READID); | |
| 67 | ||
| 68 | /* Set the address to read to 0x0 */ | |
| 69 | writeb(0x0, &gpmc_config->cs[0].nand_adr); | |
| 70 | ||
| 71 | /* Read off the manufacturer and device id. */ | |
| 72 | *mfr = readb(&gpmc_config->cs[0].nand_dat); | |
| 73 | *id = readb(&gpmc_config->cs[0].nand_dat); | |
| 74 | } |